Add Clock driver for the GCC block found in the SM6350 SoC.
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
The global clock controller on SDM670 is similar to SDM845, so let's add
support here.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: David Wronek <david.wronek@mainlining.org>
Link: https://lore.kernel.org/r/20251003-sdm670-v2-2-52c0fa481286@mainlining.org
Signed-off-by: Casey Connolly <kcxt@postmarketos.org>
Necessary for MMC to successfully probe all clocks.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: David Wronek <david.wronek@mainlining.org>
Link: https://lore.kernel.org/r/20251003-sdm670-v2-1-52c0fa481286@mainlining.org
Signed-off-by: Casey Connolly <kcxt@postmarketos.org>
This reverts commit 644b4650ee57c429bede77f44752cc867dac0e00.
While the intention of the above commit is correct, it leads to test
failures in CI that need to be addressed at the same time.
Signed-off-by: Tom Rini <trini@konsulko.com>
A few clock drivers cannot build without access to some platform
specific header files. Express those requirements in Kconfig as well.
Signed-off-by: Tom Rini <trini@konsulko.com>
In clk_set_default_get_by_id ret is passed to ERR_PTR but nothing is
done with the value that this calculates which is obviously not the
intention of the code. This is confirmed by the code around where this
function is called.
Instead return the value from ERR_PTR.
This issue found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Acked-by: Quentin Schulz <quentin.schulz@cherry.de>
Andrew Goodbody <andrew.goodbody@linaro.org> says:
Should return value calculated by ERR_PTR as calling code attempts to
check for it.
Also do not dereference a pointer that could be an error pointer before
checking it with IS_ERR.
Link: https://lore.kernel.org/r/20250723-clk_versaclock-v1-0-9d70f2530871@linaro.org
In versaclock_probe vc5->pin_xin may be an error pointer so need to
check with IS_ERR before attempting to dereference it.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
In versaclock_get_name -ENOMEM is passed to ERR_PTR but nothing is
done with the value that this calculates which is obviously not the
intention of the code. This is confirmed by the code around where this
function is called.
Instead return the value from ERR_PTR.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Remove default values for PMC PLL Analog Control Register(ACR) as the
values are specific for each SoC and PLL, so load them from PLL
characteristics structure
Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Add ACR in all PLL setting. Add correct ACR value for each PLL used in
different SoCs.
Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
The cv1800b_clk_setfield function returns void, but was doing "return
writel(...);" and while seemingly having a void function return a void
function is not a warning, when readl is a macro this problem is shown.
Correct the code to instead simply call writel.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Yao Zi <ziyao@disroot.org>
Peng Fan (OSS) <peng.fan@oss.nxp.com> says:
Misc update on firmware scmi:
- Typo fix
- Use io helpers
- Use PAGE_SIZE for arm64
- Add IN_USE error code
- Add more error info
- Support scmi max rx timeout in mailbox
- Add myself as scmi maintainer, AKASHI contributed most code, but
seems he is not invovled in the developement anymore, I volunteer to
help here.
Some items on list that I am thinking to add:
- align with linux kernel to use cpu_to_le32 and le32_to_cpu, but have not find
a good way to use the helpers.
- Add SCMI version negotiation as Linux Kernel
Link: https://lore.kernel.org/r/20250927-scmi-v1-0-5e9354fb3bff@nxp.com
Use dev_dbg to dump device name, dev_dbg also a encapsulation call
to log() and print(). So it is ok to use dev_dbg.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Currently xilinx_pm_request API supports four u32 payloads. However the
legacy SMC format supports five u32 request payloads and extended SMC
format supports six u32 request payloads. Add support for the same in
xilinx_pm_request API. Also add two dummy arguments to all the callers
of xilinx_pm_request.
The TF-A always fills seven u32 return payload so add support
for the same in xilinx_pm_request API.
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Acked-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/5ae6b560741f3ca8b89059c4ebb87acf75b4718e.1756388537.git.michal.simek@amd.com
Add "in SPL" to the SPL related driver help texts.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
SoCFPGA updates for v2025.10:
CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27762
This pull request brings a set of updates across SoCFPGA platforms
covering Agilex5, Agilex7, N5X, and Stratix10. The changes include:
* Agilex5 enhancements:
- USB3.1 enablement and DWC3 host driver support
- System Manager register configuration for USB3
- Watchdog timeout increase and SDMMC clock API integration
- dcache handling improvements in SMC mailbox path
- Enable SPL_SYS_DCACHE_OFF in defconfig
* Clock driver improvements:
- Introduce dt-bindings header for Agilex clocks
- Add enable/disable API and EMAC clock selection fixes
- Replace manual shifts with FIELD_GET usage
* DDR updates:
- IOSSM mailbox compatibility check
- Correct DDR calibration status handling
* Device tree changes:
- Agilex5: disable cache allocation for reads
- Stratix10: add NAND IP node
- Enable driver model watchdog
- Enable USB3.1 node for Agilex5
* Config cleanups:
- Simplify Agilex7 VAB defconfig
- Remove obsolete SYS_BOOTM_LEN from N5X VAB config
- Enable CRC32 support for SoCFPGA
- Increase USB hub debounce timeout
Overall this set improves reliability of DDR and cache flows,
adds missing USB and MMC features for Agilex5, and refines clock
and configuration handling across platforms.
This patch set has been tested on Agilex 5 devkit, and Agilex devkit.
A second return following the first return is unreachable code so remove
it.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250723-clk_meson-v1-1-8cd6e73145a4@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
FIELD_GET() macro is used during EMAC clock source selection
for better code readability and maintainability.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Fix the incorrect bit masking and bit shift used to compute EMAC
control which in turn is used to select EMAC clock from EMAC
source A or B.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Update Agilex clock driver to support enabling or disabling
the peripheral clocks via clock driver model APIs.
The caller will pass the clock ID to this driver and the driver
will then proceed to manipulate the desired bit in the Agilex clock
manager peripheral PLL register based on the given clock ID.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Following the work done in commit 7f39ad5a ("clk: imx6q: Add definition
for IMX6QDL_CLK_PWM1"), this commit adds definitions for PWM2, PWM3, and
PWM4 clocks. Allowing one to use these PWM modules together with DM_CLK.
Note that the solution was verified only against PWM3.
Signed-off-by: Ricardo Simoes <ricardo.simoes@pt.bosch.com>
Signed-off-by: Mark Jonas <mark.jonas@de.bosch.com>
clk_set_rate returns the actual clock rate, When assigned clock rate is
higher than 0x7FFFFFFF, the return value will be recognized as error.
Change to IS_ERR_VALUE to check the return value.
Signed-off-by: Ye Li <ye.li@nxp.com>
Add iMX95 blkctrl clock driver which implements clocks for HSIOMIX
blkctrl and LVDS blkctrl.
Since multiple blkctrl device for different blkctrl may be enabled,
and each has dedicated clock id from 0. We must enable CLK_AUTO_ID
to avoid conflict on clock id.
Signed-off-by: Ye Li <ye.li@nxp.com>
It's common that UARTs are bound and probed before U-Boot relocation,
in which case the clocks of UART and UART's pincontroller must be
registered first. Let's apply DM_FLAG_PRE_RELOC to the driver, allowing
it to bind before relocation.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The clk_register_composite() does clk_resolve_parent_clk() look up,
which requires valid udevice pointer. Do not pass NULL, pass a valid
device pointer to prevent hang on registering ck_usbo_48m clock on
STM32MP13xx.
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
In exynos7420_peric1_get_rate the variable ret is declared as an
'unsigned int' but is then used to receive the return value of
clk_get_by_index which returns an int. The value of ret is then tested
for being less than 0 which will always fail for an unsigned variable.
Fix this by declaring ret as an 'int' so that the test for the error
condition is valid.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add dummy support for the CLK_REF_PCIE_INNER_PHY clock to allow probe of
the phy-rockchip-naneng-combphy driver on RK3528.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add dummy support for the CLK_REF_PCIEx_PHY clocks to allow probe of the
phy-rockchip-naneng-combphy driver on RK3576.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
-----BEGIN PGP SIGNATURE-----
iQFNBAABCgA3FiEEqxhEmNJ6d7ZdeFLIHrMeAg6sL8gFAmitZJwZHGV1Z2VuLmhy
aXN0ZXZAbGluYXJvLm9yZwAKCRAesx4CDqwvyLCCB/9G+4rcmySlklflskgpZe/V
6pdMz/9mJOpBCbgTrOOEMGQoQW5xsdU1Jx75daELRSiQenHLaQXx6hU0y8Q+r/c7
Pntxnw99qlCAJSI7J96BvxbKTaRn68EPAcFg8m+AT87nVOmn9O2uu4ioZwWxDb0U
rh7mvLviAMDdYa401JhvGBz+4q8wXNoam5fgfOsjjdm6nETWA2NLwMMgpO0FNgmm
0m/uUV6GhZorzfbbPKEe8QjnmxQkMsBmi8P6SUL3jj187DRjkMTarm/2TTDtUyPC
R7lp3KkNzMKXRPRkHCTXCCcoejuES0/Dmkjj0ddeT0fCUr92zmpb5DaF48OTQ1ZU
=Jb2n
-----END PGP SIGNATURE-----
Merge tag 'u-boot-at91-fixes-2025.10-a' of https://source.denx.de/u-boot/custodians/u-boot-at91
First set of u-boot-at91 fixes for the 2025.10 cycle:
This set includes smatch fixes for clocks and mmc and one QSPI fix.
The use of the unsigned variable 'i' as a loop index leads to the test
for i being non-negative always being true. Instead declare 'i' as an
int so that the for loop will terminate as expected.
If the original for loop completes 'i' will be 1 past the end of the
array so decrement it in the subsequent error path to prevent an out of
bounds access occurring.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
The variable 'index' is declared as unsigned but used to receive the
return value of a function returning 'int'. This value is then tested
for being less than zero to detect an error condition but as index is
unsigned this can never be true. Change the variable 'index' to be an
int so that the error condition can be detected.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
The function dev_read_u32_default does not return an error and the
variable 'val' is unsigned so testing for >= 0 will always be true. It
looks like the code was attempting to return -1 if xtal-load-pf was not
present but that cannot work. Instead use dev_read_u32 which returns an
error code separately from writing the value into the passed pointer.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Fixes: 260777fc2333 ("clk: cdce9xx: add support for cdce9xx clock synthesizer")
Acked-by: Quentin Schulz <quentin.schulz@cherry.de>
This pull request introduces initial U-Boot support for Agilex7 M-series, along
with several enhancements and cleanups across existing Agilex platforms. Key
changes include new board support, DDR driver additions, updated device trees,
and broader SoCFPGA SPL improvements.
Highlights:
- Agilex7 M-series bring-up:
- Basic DT support and board initialization for Agilex7 M-series SoC and
SoCDK.
- New sdram_agilex7m DDR driver with UIBSSM mailbox support and HBM support.
- Clock driver support for Agilex7 M-series.
- New defconfig: socfpga_agilex7m_defconfig.
- Agilex and Agilex5 enhancements:
- Improved SPL support: ASYNC interrupt enabling, system manager init
refactor, and cold scratch register usage.
- Updated firewall probing and watchdog support in SPL.
- Cleaned up DDR code, added secure region support for ATF, and improved warm
reset handling.
- Device Tree and config updates:
- Migration to upstream Linux DT layout for Agilex platforms.
- Consolidated socfpga_agilex_defconfig and removed deprecated configs.
- Platform-specific environment variables for Distro Boot added.
- Driver fixes and cleanups:
- dwc_eth_xgmac and clk-agilex cleanup and improvements.
- Several coverity and style fixes.
Contributions in this PR are from Alif Zakuan Yuslaimi, Tingting Meng, and
Andrew Goodbody. This patch set has been tested on Agilex 5 devkit, Agilex
devkit and Agilex7m devkit.
Passing all pipeline tests at SoCFPGA U-boot custodian
https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27318
Replace cm_wait_for_fsm() function with wait_for_bit_le32() function
which supports accurate timeout.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Update the ARMv8 generic timer frequency register (cntfrq_el0)
with the actual hardware timer frequency (COUNTER_FREQUENCY_REAL).
The generic timer frequency was set to 0x200000000 during boot clk
which needs to be set to 0x400000000 when transition from boot clk
to PLL clk.
This will ensure that subsequent timer operations are based on the
correct frequency, ensuring accurate timekeeping.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
