mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2026-05-05 04:36:13 +02:00
Merge branch 'next'
Merge the outstanding changes from the 'next' branch to master.
This commit is contained in:
Tom Rini
commit
0eaa4b3373
@ -258,11 +258,11 @@ stages:
|
||||
ln -s u_boot_boardenv_qemu_arm64_na.py /tmp/uboot-test-hooks/py/travis-ci/u_boot_boardenv_qemu_arm64_lwip_na.py
|
||||
ln -s travis-ci /tmp/uboot-test-hooks/bin/\`hostname\`
|
||||
ln -s travis-ci /tmp/uboot-test-hooks/py/\`hostname\`
|
||||
if [[ "\${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
|
||||
if [[ "\${TEST_PY_BD}" == "qemu-riscv32_spl" ]] || [[ "\${TEST_PY_BD}" == "xilinx_mbv32_smode" ]]; then
|
||||
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
|
||||
export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
|
||||
fi
|
||||
if [[ "\${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "\${TEST_PY_BD}" == "sifive_unleashed" ]]; then
|
||||
if [[ "\${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "\${TEST_PY_BD}" == "sifive_unleashed" ]] || [[ "\${TEST_PY_BD}" == "xilinx_mbv64_smode" ]]; then
|
||||
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
|
||||
export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
|
||||
fi
|
||||
@ -540,6 +540,22 @@ stages:
|
||||
TEST_PY_BD: "sifive_unleashed"
|
||||
TEST_PY_ID: "--id spi-nor_qemu"
|
||||
TEST_PY_TEST_SPEC: "not sleep"
|
||||
xilinx_mbv32:
|
||||
TEST_PY_BD: "xilinx_mbv32"
|
||||
TEST_PY_ID: "--id qemu"
|
||||
TEST_PY_TEST_SPEC: "not sleep"
|
||||
xilinx_mbv32_smode test.py:
|
||||
TEST_PY_BD: "xilinx_mbv32_smode"
|
||||
TEST_PY_ID: "--id qemu"
|
||||
TEST_PY_TEST_SPEC: "not sleep"
|
||||
xilinx_mbv64 test.py:
|
||||
TEST_PY_BD: "xilinx_mbv64"
|
||||
TEST_PY_ID: "--id qemu"
|
||||
TEST_PY_TEST_SPEC: "not sleep"
|
||||
xilinx_mbv64_smode test.py:
|
||||
TEST_PY_BD: "xilinx_mbv64_smode"
|
||||
TEST_PY_ID: "--id qemu"
|
||||
TEST_PY_TEST_SPEC: "not sleep"
|
||||
xilinx_zynq_virt:
|
||||
TEST_PY_BD: "xilinx_zynq_virt"
|
||||
TEST_PY_ID: "--id qemu"
|
||||
|
||||
@ -19,6 +19,9 @@
|
||||
# Not Linux, so we don't recommend usleep_range() over udelay()
|
||||
--ignore USLEEP_RANGE
|
||||
|
||||
# We also do not have a functionally different mdelay() and udelay()
|
||||
--ignore LONG_UDELAY
|
||||
|
||||
# Ignore networking block comment style
|
||||
--ignore NETWORKING_BLOCK_COMMENT_STYLE
|
||||
|
||||
|
||||
804
.clang-format
Normal file
804
.clang-format
Normal file
@ -0,0 +1,804 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
#
|
||||
# clang-format configuration file. Intended for clang-format >= 11.
|
||||
#
|
||||
# For more information, see:
|
||||
#
|
||||
# Documentation/dev-tools/clang-format.rst
|
||||
# https://clang.llvm.org/docs/ClangFormat.html
|
||||
# https://clang.llvm.org/docs/ClangFormatStyleOptions.html
|
||||
#
|
||||
---
|
||||
AccessModifierOffset: -4
|
||||
AlignAfterOpenBracket: Align
|
||||
AlignConsecutiveAssignments: false
|
||||
AlignConsecutiveDeclarations: false
|
||||
AlignEscapedNewlines: Left
|
||||
AlignOperands: true
|
||||
AlignTrailingComments: false
|
||||
AllowAllParametersOfDeclarationOnNextLine: false
|
||||
AllowShortBlocksOnASingleLine: false
|
||||
AllowShortCaseLabelsOnASingleLine: false
|
||||
AllowShortFunctionsOnASingleLine: None
|
||||
AllowShortIfStatementsOnASingleLine: false
|
||||
AllowShortLoopsOnASingleLine: false
|
||||
AlwaysBreakAfterDefinitionReturnType: None
|
||||
AlwaysBreakAfterReturnType: None
|
||||
AlwaysBreakBeforeMultilineStrings: false
|
||||
AlwaysBreakTemplateDeclarations: false
|
||||
BinPackArguments: true
|
||||
BinPackParameters: true
|
||||
BraceWrapping:
|
||||
AfterClass: false
|
||||
AfterControlStatement: false
|
||||
AfterEnum: false
|
||||
AfterFunction: true
|
||||
AfterNamespace: true
|
||||
AfterObjCDeclaration: false
|
||||
AfterStruct: false
|
||||
AfterUnion: false
|
||||
AfterExternBlock: false
|
||||
BeforeCatch: false
|
||||
BeforeElse: false
|
||||
IndentBraces: false
|
||||
SplitEmptyFunction: true
|
||||
SplitEmptyRecord: true
|
||||
SplitEmptyNamespace: true
|
||||
BreakBeforeBinaryOperators: None
|
||||
BreakBeforeBraces: Custom
|
||||
BreakBeforeInheritanceComma: false
|
||||
BreakBeforeTernaryOperators: false
|
||||
BreakConstructorInitializersBeforeComma: false
|
||||
BreakConstructorInitializers: BeforeComma
|
||||
BreakAfterJavaFieldAnnotations: false
|
||||
BreakStringLiterals: false
|
||||
ColumnLimit: 80
|
||||
CommentPragmas: '^ IWYU pragma:'
|
||||
CompactNamespaces: false
|
||||
ConstructorInitializerAllOnOneLineOrOnePerLine: false
|
||||
ConstructorInitializerIndentWidth: 8
|
||||
ContinuationIndentWidth: 8
|
||||
Cpp11BracedListStyle: false
|
||||
DerivePointerAlignment: false
|
||||
DisableFormat: false
|
||||
ExperimentalAutoDetectBinPacking: false
|
||||
FixNamespaceComments: false
|
||||
|
||||
# Taken from:
|
||||
# git grep -h '^#define [^[:space:]]*for_each[^[:space:]]*(' include/ tools/ \
|
||||
# | sed "s,^#define \([^[:space:]]*for_each[^[:space:]]*\)(.*$, - '\1'," \
|
||||
# | LC_ALL=C sort -u
|
||||
ForEachMacros:
|
||||
- '__ata_qc_for_each'
|
||||
- '__bio_for_each_bvec'
|
||||
- '__bio_for_each_segment'
|
||||
- '__evlist__for_each_entry'
|
||||
- '__evlist__for_each_entry_continue'
|
||||
- '__evlist__for_each_entry_from'
|
||||
- '__evlist__for_each_entry_reverse'
|
||||
- '__evlist__for_each_entry_safe'
|
||||
- '__for_each_mem_range'
|
||||
- '__for_each_mem_range_rev'
|
||||
- '__for_each_thread'
|
||||
- '__hlist_for_each_rcu'
|
||||
- '__map__for_each_symbol_by_name'
|
||||
- '__pci_bus_for_each_res0'
|
||||
- '__pci_bus_for_each_res1'
|
||||
- '__pci_dev_for_each_res0'
|
||||
- '__pci_dev_for_each_res1'
|
||||
- '__perf_evlist__for_each_entry'
|
||||
- '__perf_evlist__for_each_entry_reverse'
|
||||
- '__perf_evlist__for_each_entry_safe'
|
||||
- '__rq_for_each_bio'
|
||||
- '__shost_for_each_device'
|
||||
- '__sym_for_each'
|
||||
- '_for_each_counter'
|
||||
- 'apei_estatus_for_each_section'
|
||||
- 'ata_for_each_dev'
|
||||
- 'ata_for_each_link'
|
||||
- 'ata_qc_for_each'
|
||||
- 'ata_qc_for_each_raw'
|
||||
- 'ata_qc_for_each_with_internal'
|
||||
- 'ax25_for_each'
|
||||
- 'ax25_uid_for_each'
|
||||
- 'bio_for_each_bvec'
|
||||
- 'bio_for_each_bvec_all'
|
||||
- 'bio_for_each_folio_all'
|
||||
- 'bio_for_each_integrity_vec'
|
||||
- 'bio_for_each_segment'
|
||||
- 'bio_for_each_segment_all'
|
||||
- 'bio_list_for_each'
|
||||
- 'bip_for_each_vec'
|
||||
- 'bond_for_each_slave'
|
||||
- 'bond_for_each_slave_rcu'
|
||||
- 'bpf_for_each'
|
||||
- 'bpf_for_each_reg_in_vstate'
|
||||
- 'bpf_for_each_reg_in_vstate_mask'
|
||||
- 'bpf_for_each_spilled_reg'
|
||||
- 'bpf_object__for_each_map'
|
||||
- 'bpf_object__for_each_program'
|
||||
- 'btree_for_each_safe128'
|
||||
- 'btree_for_each_safe32'
|
||||
- 'btree_for_each_safe64'
|
||||
- 'btree_for_each_safel'
|
||||
- 'card_for_each_dev'
|
||||
- 'cgroup_taskset_for_each'
|
||||
- 'cgroup_taskset_for_each_leader'
|
||||
- 'cpu_aggr_map__for_each_idx'
|
||||
- 'cpufreq_for_each_efficient_entry_idx'
|
||||
- 'cpufreq_for_each_entry'
|
||||
- 'cpufreq_for_each_entry_idx'
|
||||
- 'cpufreq_for_each_valid_entry'
|
||||
- 'cpufreq_for_each_valid_entry_idx'
|
||||
- 'css_for_each_child'
|
||||
- 'css_for_each_descendant_post'
|
||||
- 'css_for_each_descendant_pre'
|
||||
- 'damon_for_each_region'
|
||||
- 'damon_for_each_region_from'
|
||||
- 'damon_for_each_region_safe'
|
||||
- 'damon_for_each_scheme'
|
||||
- 'damon_for_each_scheme_safe'
|
||||
- 'damon_for_each_target'
|
||||
- 'damon_for_each_target_safe'
|
||||
- 'damos_for_each_filter'
|
||||
- 'damos_for_each_filter_safe'
|
||||
- 'damos_for_each_ops_filter'
|
||||
- 'damos_for_each_ops_filter_safe'
|
||||
- 'damos_for_each_quota_goal'
|
||||
- 'damos_for_each_quota_goal_safe'
|
||||
- 'data__for_each_file'
|
||||
- 'data__for_each_file_new'
|
||||
- 'data__for_each_file_start'
|
||||
- 'def_for_each_cpu'
|
||||
- 'device_for_each_child_node'
|
||||
- 'device_for_each_child_node_scoped'
|
||||
- 'dma_fence_array_for_each'
|
||||
- 'dma_fence_chain_for_each'
|
||||
- 'dma_fence_unwrap_for_each'
|
||||
- 'dma_resv_for_each_fence'
|
||||
- 'dma_resv_for_each_fence_unlocked'
|
||||
- 'do_for_each_ftrace_op'
|
||||
- 'drm_atomic_crtc_for_each_plane'
|
||||
- 'drm_atomic_crtc_state_for_each_plane'
|
||||
- 'drm_atomic_crtc_state_for_each_plane_state'
|
||||
- 'drm_atomic_for_each_plane_damage'
|
||||
- 'drm_client_for_each_connector_iter'
|
||||
- 'drm_client_for_each_modeset'
|
||||
- 'drm_connector_for_each_possible_encoder'
|
||||
- 'drm_exec_for_each_locked_object'
|
||||
- 'drm_exec_for_each_locked_object_reverse'
|
||||
- 'drm_for_each_bridge_in_chain'
|
||||
- 'drm_for_each_connector_iter'
|
||||
- 'drm_for_each_crtc'
|
||||
- 'drm_for_each_crtc_reverse'
|
||||
- 'drm_for_each_encoder'
|
||||
- 'drm_for_each_encoder_mask'
|
||||
- 'drm_for_each_fb'
|
||||
- 'drm_for_each_legacy_plane'
|
||||
- 'drm_for_each_plane'
|
||||
- 'drm_for_each_plane_mask'
|
||||
- 'drm_for_each_privobj'
|
||||
- 'drm_gem_for_each_gpuvm_bo'
|
||||
- 'drm_gem_for_each_gpuvm_bo_safe'
|
||||
- 'drm_gpusvm_for_each_range'
|
||||
- 'drm_gpuva_for_each_op'
|
||||
- 'drm_gpuva_for_each_op_from_reverse'
|
||||
- 'drm_gpuva_for_each_op_reverse'
|
||||
- 'drm_gpuva_for_each_op_safe'
|
||||
- 'drm_gpuvm_bo_for_each_va'
|
||||
- 'drm_gpuvm_bo_for_each_va_safe'
|
||||
- 'drm_gpuvm_for_each_va'
|
||||
- 'drm_gpuvm_for_each_va_range'
|
||||
- 'drm_gpuvm_for_each_va_range_safe'
|
||||
- 'drm_gpuvm_for_each_va_safe'
|
||||
- 'drm_mm_for_each_hole'
|
||||
- 'drm_mm_for_each_node'
|
||||
- 'drm_mm_for_each_node_in_range'
|
||||
- 'drm_mm_for_each_node_safe'
|
||||
- 'dsa_switch_for_each_available_port'
|
||||
- 'dsa_switch_for_each_cpu_port'
|
||||
- 'dsa_switch_for_each_cpu_port_continue_reverse'
|
||||
- 'dsa_switch_for_each_port'
|
||||
- 'dsa_switch_for_each_port_continue_reverse'
|
||||
- 'dsa_switch_for_each_port_safe'
|
||||
- 'dsa_switch_for_each_user_port'
|
||||
- 'dsa_switch_for_each_user_port_continue_reverse'
|
||||
- 'dsa_tree_for_each_cpu_port'
|
||||
- 'dsa_tree_for_each_user_port'
|
||||
- 'dsa_tree_for_each_user_port_continue_reverse'
|
||||
- 'dso__for_each_symbol'
|
||||
- 'elf_hash_for_each_possible'
|
||||
- 'elf_symtab__for_each_symbol'
|
||||
- 'evlist__for_each_cpu'
|
||||
- 'evlist__for_each_entry'
|
||||
- 'evlist__for_each_entry_continue'
|
||||
- 'evlist__for_each_entry_from'
|
||||
- 'evlist__for_each_entry_reverse'
|
||||
- 'evlist__for_each_entry_safe'
|
||||
- 'flow_action_for_each'
|
||||
- 'for_each_acpi_consumer_dev'
|
||||
- 'for_each_acpi_dev_match'
|
||||
- 'for_each_active_dev_scope'
|
||||
- 'for_each_active_drhd_unit'
|
||||
- 'for_each_active_iommu'
|
||||
- 'for_each_active_irq'
|
||||
- 'for_each_active_route'
|
||||
- 'for_each_aggr_pgid'
|
||||
- 'for_each_alloc_capable_rdt_resource'
|
||||
- 'for_each_and_bit'
|
||||
- 'for_each_andnot_bit'
|
||||
- 'for_each_available_child_of_node'
|
||||
- 'for_each_available_child_of_node_scoped'
|
||||
- 'for_each_bench'
|
||||
- 'for_each_bio'
|
||||
- 'for_each_board_func_rsrc'
|
||||
- 'for_each_btf_ext_rec'
|
||||
- 'for_each_btf_ext_sec'
|
||||
- 'for_each_bvec'
|
||||
- 'for_each_capable_rdt_resource'
|
||||
- 'for_each_card_auxs'
|
||||
- 'for_each_card_auxs_safe'
|
||||
- 'for_each_card_components'
|
||||
- 'for_each_card_dapms'
|
||||
- 'for_each_card_pre_auxs'
|
||||
- 'for_each_card_prelinks'
|
||||
- 'for_each_card_rtds'
|
||||
- 'for_each_card_rtds_safe'
|
||||
- 'for_each_card_widgets'
|
||||
- 'for_each_card_widgets_safe'
|
||||
- 'for_each_cgroup_storage_type'
|
||||
- 'for_each_child_of_node'
|
||||
- 'for_each_child_of_node_scoped'
|
||||
- 'for_each_child_of_node_with_prefix'
|
||||
- 'for_each_clear_bit'
|
||||
- 'for_each_clear_bit_from'
|
||||
- 'for_each_clear_bitrange'
|
||||
- 'for_each_clear_bitrange_from'
|
||||
- 'for_each_cmd'
|
||||
- 'for_each_cmsghdr'
|
||||
- 'for_each_collection'
|
||||
- 'for_each_comp_order'
|
||||
- 'for_each_compatible_node'
|
||||
- 'for_each_component_dais'
|
||||
- 'for_each_component_dais_safe'
|
||||
- 'for_each_conduit'
|
||||
- 'for_each_console'
|
||||
- 'for_each_console_srcu'
|
||||
- 'for_each_cpu'
|
||||
- 'for_each_cpu_and'
|
||||
- 'for_each_cpu_andnot'
|
||||
- 'for_each_cpu_from'
|
||||
- 'for_each_cpu_or'
|
||||
- 'for_each_cpu_wrap'
|
||||
- 'for_each_dapm_widgets'
|
||||
- 'for_each_dedup_cand'
|
||||
- 'for_each_dev_addr'
|
||||
- 'for_each_dev_scope'
|
||||
- 'for_each_dma_cap_mask'
|
||||
- 'for_each_dpcm_be'
|
||||
- 'for_each_dpcm_be_rollback'
|
||||
- 'for_each_dpcm_be_safe'
|
||||
- 'for_each_dpcm_fe'
|
||||
- 'for_each_drhd_unit'
|
||||
- 'for_each_dss_dev'
|
||||
- 'for_each_efi_memory_desc'
|
||||
- 'for_each_efi_memory_desc_in_map'
|
||||
- 'for_each_element'
|
||||
- 'for_each_element_extid'
|
||||
- 'for_each_element_id'
|
||||
- 'for_each_enabled_cpu'
|
||||
- 'for_each_endpoint_of_node'
|
||||
- 'for_each_event'
|
||||
- 'for_each_event_tps'
|
||||
- 'for_each_evictable_lru'
|
||||
- 'for_each_fib6_node_rt_rcu'
|
||||
- 'for_each_fib6_walker_rt'
|
||||
- 'for_each_file_lock'
|
||||
- 'for_each_free_mem_pfn_range_in_zone_from'
|
||||
- 'for_each_free_mem_range'
|
||||
- 'for_each_free_mem_range_reverse'
|
||||
- 'for_each_func_rsrc'
|
||||
- 'for_each_gpiochip_node'
|
||||
- 'for_each_group_evsel'
|
||||
- 'for_each_group_evsel_head'
|
||||
- 'for_each_group_member'
|
||||
- 'for_each_group_member_head'
|
||||
- 'for_each_hstate'
|
||||
- 'for_each_hwgpio'
|
||||
- 'for_each_hwgpio_in_range'
|
||||
- 'for_each_if'
|
||||
- 'for_each_inject_fn'
|
||||
- 'for_each_insn'
|
||||
- 'for_each_insn_op_loc'
|
||||
- 'for_each_insn_prefix'
|
||||
- 'for_each_intid'
|
||||
- 'for_each_iommu'
|
||||
- 'for_each_ip_tunnel_rcu'
|
||||
- 'for_each_irq_desc'
|
||||
- 'for_each_irq_nr'
|
||||
- 'for_each_lang'
|
||||
- 'for_each_link_ch_maps'
|
||||
- 'for_each_link_codecs'
|
||||
- 'for_each_link_cpus'
|
||||
- 'for_each_link_platforms'
|
||||
- 'for_each_lru'
|
||||
- 'for_each_matching_node'
|
||||
- 'for_each_matching_node_and_match'
|
||||
- 'for_each_media_entity_data_link'
|
||||
- 'for_each_mem_pfn_range'
|
||||
- 'for_each_mem_range'
|
||||
- 'for_each_mem_range_rev'
|
||||
- 'for_each_mem_region'
|
||||
- 'for_each_member'
|
||||
- 'for_each_memory'
|
||||
- 'for_each_migratetype_order'
|
||||
- 'for_each_missing_reg'
|
||||
- 'for_each_mle_subelement'
|
||||
- 'for_each_mod_mem_type'
|
||||
- 'for_each_mon_capable_rdt_resource'
|
||||
- 'for_each_mp_bvec'
|
||||
- 'for_each_net'
|
||||
- 'for_each_net_continue_reverse'
|
||||
- 'for_each_net_rcu'
|
||||
- 'for_each_netdev'
|
||||
- 'for_each_netdev_continue'
|
||||
- 'for_each_netdev_continue_rcu'
|
||||
- 'for_each_netdev_continue_reverse'
|
||||
- 'for_each_netdev_dump'
|
||||
- 'for_each_netdev_feature'
|
||||
- 'for_each_netdev_in_bond_rcu'
|
||||
- 'for_each_netdev_rcu'
|
||||
- 'for_each_netdev_reverse'
|
||||
- 'for_each_netdev_safe'
|
||||
- 'for_each_new_connector_in_state'
|
||||
- 'for_each_new_crtc_in_state'
|
||||
- 'for_each_new_mst_mgr_in_state'
|
||||
- 'for_each_new_plane_in_state'
|
||||
- 'for_each_new_plane_in_state_reverse'
|
||||
- 'for_each_new_private_obj_in_state'
|
||||
- 'for_each_new_reg'
|
||||
- 'for_each_nhlt_endpoint'
|
||||
- 'for_each_nhlt_endpoint_fmtcfg'
|
||||
- 'for_each_nhlt_fmtcfg'
|
||||
- 'for_each_node'
|
||||
- 'for_each_node_by_name'
|
||||
- 'for_each_node_by_type'
|
||||
- 'for_each_node_mask'
|
||||
- 'for_each_node_numadist'
|
||||
- 'for_each_node_state'
|
||||
- 'for_each_node_with_cpus'
|
||||
- 'for_each_node_with_property'
|
||||
- 'for_each_nonreserved_multicast_dest_pgid'
|
||||
- 'for_each_numa_hop_mask'
|
||||
- 'for_each_of_allnodes'
|
||||
- 'for_each_of_allnodes_from'
|
||||
- 'for_each_of_cpu_node'
|
||||
- 'for_each_of_graph_port'
|
||||
- 'for_each_of_graph_port_endpoint'
|
||||
- 'for_each_of_pci_range'
|
||||
- 'for_each_old_connector_in_state'
|
||||
- 'for_each_old_crtc_in_state'
|
||||
- 'for_each_old_mst_mgr_in_state'
|
||||
- 'for_each_old_plane_in_state'
|
||||
- 'for_each_old_private_obj_in_state'
|
||||
- 'for_each_oldnew_connector_in_state'
|
||||
- 'for_each_oldnew_crtc_in_state'
|
||||
- 'for_each_oldnew_mst_mgr_in_state'
|
||||
- 'for_each_oldnew_plane_in_state'
|
||||
- 'for_each_oldnew_plane_in_state_reverse'
|
||||
- 'for_each_oldnew_private_obj_in_state'
|
||||
- 'for_each_online_cpu'
|
||||
- 'for_each_online_cpu_wrap'
|
||||
- 'for_each_online_node'
|
||||
- 'for_each_online_pgdat'
|
||||
- 'for_each_or_bit'
|
||||
- 'for_each_page_ext'
|
||||
- 'for_each_path'
|
||||
- 'for_each_pci_bridge'
|
||||
- 'for_each_pci_dev'
|
||||
- 'for_each_pcm_streams'
|
||||
- 'for_each_physmem_range'
|
||||
- 'for_each_populated_zone'
|
||||
- 'for_each_possible_cpu'
|
||||
- 'for_each_possible_cpu_wrap'
|
||||
- 'for_each_present_blessed_reg'
|
||||
- 'for_each_present_cpu'
|
||||
- 'for_each_present_section_nr'
|
||||
- 'for_each_prime_number'
|
||||
- 'for_each_prime_number_from'
|
||||
- 'for_each_probe_cache_entry'
|
||||
- 'for_each_process'
|
||||
- 'for_each_process_thread'
|
||||
- 'for_each_prop_codec_conf'
|
||||
- 'for_each_prop_dai_codec'
|
||||
- 'for_each_prop_dai_cpu'
|
||||
- 'for_each_prop_dlc_codecs'
|
||||
- 'for_each_prop_dlc_cpus'
|
||||
- 'for_each_prop_dlc_platforms'
|
||||
- 'for_each_property_of_node'
|
||||
- 'for_each_rdt_resource'
|
||||
- 'for_each_reg'
|
||||
- 'for_each_reg_filtered'
|
||||
- 'for_each_reloc'
|
||||
- 'for_each_reloc_from'
|
||||
- 'for_each_requested_gpio'
|
||||
- 'for_each_requested_gpio_in_range'
|
||||
- 'for_each_reserved_child_of_node'
|
||||
- 'for_each_reserved_mem_range'
|
||||
- 'for_each_reserved_mem_region'
|
||||
- 'for_each_rtd_ch_maps'
|
||||
- 'for_each_rtd_codec_dais'
|
||||
- 'for_each_rtd_components'
|
||||
- 'for_each_rtd_cpu_dais'
|
||||
- 'for_each_rtd_dais'
|
||||
- 'for_each_rtd_dais_reverse'
|
||||
- 'for_each_sband_iftype_data'
|
||||
- 'for_each_script'
|
||||
- 'for_each_sec'
|
||||
- 'for_each_set_bit'
|
||||
- 'for_each_set_bit_from'
|
||||
- 'for_each_set_bit_wrap'
|
||||
- 'for_each_set_bitrange'
|
||||
- 'for_each_set_bitrange_from'
|
||||
- 'for_each_set_clump8'
|
||||
- 'for_each_sg'
|
||||
- 'for_each_sg_dma_page'
|
||||
- 'for_each_sg_page'
|
||||
- 'for_each_sgtable_dma_page'
|
||||
- 'for_each_sgtable_dma_sg'
|
||||
- 'for_each_sgtable_page'
|
||||
- 'for_each_sgtable_sg'
|
||||
- 'for_each_sibling_event'
|
||||
- 'for_each_sta_active_link'
|
||||
- 'for_each_subelement'
|
||||
- 'for_each_subelement_extid'
|
||||
- 'for_each_subelement_id'
|
||||
- 'for_each_sublist'
|
||||
- 'for_each_subsystem'
|
||||
- 'for_each_suite'
|
||||
- 'for_each_supported_activate_fn'
|
||||
- 'for_each_supported_inject_fn'
|
||||
- 'for_each_sym'
|
||||
- 'for_each_thread'
|
||||
- 'for_each_token'
|
||||
- 'for_each_unicast_dest_pgid'
|
||||
- 'for_each_valid_link'
|
||||
- 'for_each_vif_active_link'
|
||||
- 'for_each_vma'
|
||||
- 'for_each_vma_range'
|
||||
- 'for_each_vsi'
|
||||
- 'for_each_wakeup_source'
|
||||
- 'for_each_zone'
|
||||
- 'for_each_zone_zonelist'
|
||||
- 'for_each_zone_zonelist_nodemask'
|
||||
- 'func_for_each_insn'
|
||||
- 'fwnode_for_each_available_child_node'
|
||||
- 'fwnode_for_each_child_node'
|
||||
- 'fwnode_for_each_parent_node'
|
||||
- 'fwnode_graph_for_each_endpoint'
|
||||
- 'gadget_for_each_ep'
|
||||
- 'genradix_for_each'
|
||||
- 'genradix_for_each_from'
|
||||
- 'genradix_for_each_reverse'
|
||||
- 'hash_for_each'
|
||||
- 'hash_for_each_possible'
|
||||
- 'hash_for_each_possible_rcu'
|
||||
- 'hash_for_each_possible_rcu_notrace'
|
||||
- 'hash_for_each_possible_safe'
|
||||
- 'hash_for_each_rcu'
|
||||
- 'hash_for_each_safe'
|
||||
- 'hashmap__for_each_entry'
|
||||
- 'hashmap__for_each_entry_safe'
|
||||
- 'hashmap__for_each_key_entry'
|
||||
- 'hashmap__for_each_key_entry_safe'
|
||||
- 'hctx_for_each_ctx'
|
||||
- 'hists__for_each_format'
|
||||
- 'hists__for_each_sort_list'
|
||||
- 'hlist_bl_for_each_entry'
|
||||
- 'hlist_bl_for_each_entry_rcu'
|
||||
- 'hlist_bl_for_each_entry_safe'
|
||||
- 'hlist_for_each'
|
||||
- 'hlist_for_each_entry'
|
||||
- 'hlist_for_each_entry_continue'
|
||||
- 'hlist_for_each_entry_continue_rcu'
|
||||
- 'hlist_for_each_entry_continue_rcu_bh'
|
||||
- 'hlist_for_each_entry_from'
|
||||
- 'hlist_for_each_entry_from_rcu'
|
||||
- 'hlist_for_each_entry_rcu'
|
||||
- 'hlist_for_each_entry_rcu_bh'
|
||||
- 'hlist_for_each_entry_rcu_notrace'
|
||||
- 'hlist_for_each_entry_safe'
|
||||
- 'hlist_for_each_entry_srcu'
|
||||
- 'hlist_for_each_safe'
|
||||
- 'hlist_nulls_for_each_entry'
|
||||
- 'hlist_nulls_for_each_entry_from'
|
||||
- 'hlist_nulls_for_each_entry_rcu'
|
||||
- 'hlist_nulls_for_each_entry_safe'
|
||||
- 'i3c_bus_for_each_i2cdev'
|
||||
- 'i3c_bus_for_each_i3cdev'
|
||||
- 'idr_for_each_entry'
|
||||
- 'idr_for_each_entry_continue'
|
||||
- 'idr_for_each_entry_continue_ul'
|
||||
- 'idr_for_each_entry_ul'
|
||||
- 'iio_for_each_active_channel'
|
||||
- 'in_dev_for_each_ifa_rcu'
|
||||
- 'in_dev_for_each_ifa_rtnl'
|
||||
- 'in_dev_for_each_ifa_rtnl_net'
|
||||
- 'inet_bind_bucket_for_each'
|
||||
- 'interval_tree_for_each_span'
|
||||
- 'intlist__for_each_entry'
|
||||
- 'intlist__for_each_entry_safe'
|
||||
- 'kcore_copy__for_each_phdr'
|
||||
- 'key_for_each'
|
||||
- 'key_for_each_safe'
|
||||
- 'klp_for_each_func'
|
||||
- 'klp_for_each_func_safe'
|
||||
- 'klp_for_each_func_static'
|
||||
- 'klp_for_each_object'
|
||||
- 'klp_for_each_object_safe'
|
||||
- 'klp_for_each_object_static'
|
||||
- 'kunit_suite_for_each_test_case'
|
||||
- 'kvm_for_each_memslot'
|
||||
- 'kvm_for_each_memslot_in_gfn_range'
|
||||
- 'kvm_for_each_vcpu'
|
||||
- 'libbpf_nla_for_each_attr'
|
||||
- 'list_for_each'
|
||||
- 'list_for_each_codec'
|
||||
- 'list_for_each_codec_safe'
|
||||
- 'list_for_each_continue'
|
||||
- 'list_for_each_entry'
|
||||
- 'list_for_each_entry_continue'
|
||||
- 'list_for_each_entry_continue_rcu'
|
||||
- 'list_for_each_entry_continue_reverse'
|
||||
- 'list_for_each_entry_from'
|
||||
- 'list_for_each_entry_from_rcu'
|
||||
- 'list_for_each_entry_from_reverse'
|
||||
- 'list_for_each_entry_lockless'
|
||||
- 'list_for_each_entry_rcu'
|
||||
- 'list_for_each_entry_reverse'
|
||||
- 'list_for_each_entry_safe'
|
||||
- 'list_for_each_entry_safe_continue'
|
||||
- 'list_for_each_entry_safe_from'
|
||||
- 'list_for_each_entry_safe_reverse'
|
||||
- 'list_for_each_entry_srcu'
|
||||
- 'list_for_each_from'
|
||||
- 'list_for_each_prev'
|
||||
- 'list_for_each_prev_safe'
|
||||
- 'list_for_each_rcu'
|
||||
- 'list_for_each_safe'
|
||||
- 'llist_for_each'
|
||||
- 'llist_for_each_entry'
|
||||
- 'llist_for_each_entry_safe'
|
||||
- 'llist_for_each_safe'
|
||||
- 'lwq_for_each_safe'
|
||||
- 'map__for_each_symbol'
|
||||
- 'map__for_each_symbol_by_name'
|
||||
- 'mas_for_each'
|
||||
- 'mas_for_each_rev'
|
||||
- 'mci_for_each_dimm'
|
||||
- 'media_device_for_each_entity'
|
||||
- 'media_device_for_each_intf'
|
||||
- 'media_device_for_each_link'
|
||||
- 'media_device_for_each_pad'
|
||||
- 'media_entity_for_each_pad'
|
||||
- 'media_pipeline_for_each_entity'
|
||||
- 'media_pipeline_for_each_pad'
|
||||
- 'mlx5_lag_for_each_peer_mdev'
|
||||
- 'mptcp_for_each_subflow'
|
||||
- 'msi_domain_for_each_desc'
|
||||
- 'msi_for_each_desc'
|
||||
- 'mt_for_each'
|
||||
- 'nanddev_io_for_each_block'
|
||||
- 'nanddev_io_for_each_page'
|
||||
- 'neigh_for_each_in_bucket'
|
||||
- 'neigh_for_each_in_bucket_rcu'
|
||||
- 'neigh_for_each_in_bucket_safe'
|
||||
- 'netdev_for_each_lower_dev'
|
||||
- 'netdev_for_each_lower_private'
|
||||
- 'netdev_for_each_lower_private_rcu'
|
||||
- 'netdev_for_each_mc_addr'
|
||||
- 'netdev_for_each_synced_mc_addr'
|
||||
- 'netdev_for_each_synced_uc_addr'
|
||||
- 'netdev_for_each_uc_addr'
|
||||
- 'netdev_for_each_upper_dev_rcu'
|
||||
- 'netdev_hw_addr_list_for_each'
|
||||
- 'nft_rule_for_each_expr'
|
||||
- 'nla_for_each_attr'
|
||||
- 'nla_for_each_attr_type'
|
||||
- 'nla_for_each_nested'
|
||||
- 'nla_for_each_nested_type'
|
||||
- 'nlmsg_for_each_attr'
|
||||
- 'nlmsg_for_each_msg'
|
||||
- 'nr_neigh_for_each'
|
||||
- 'nr_neigh_for_each_safe'
|
||||
- 'nr_node_for_each'
|
||||
- 'nr_node_for_each_safe'
|
||||
- 'of_for_each_phandle'
|
||||
- 'of_property_for_each_string'
|
||||
- 'of_property_for_each_u32'
|
||||
- 'pci_bus_for_each_resource'
|
||||
- 'pci_dev_for_each_resource'
|
||||
- 'pcl_for_each_chunk'
|
||||
- 'pcl_for_each_segment'
|
||||
- 'pcm_for_each_format'
|
||||
- 'perf_config_items__for_each_entry'
|
||||
- 'perf_config_sections__for_each_entry'
|
||||
- 'perf_config_set__for_each_entry'
|
||||
- 'perf_cpu_map__for_each_cpu'
|
||||
- 'perf_cpu_map__for_each_cpu_skip_any'
|
||||
- 'perf_cpu_map__for_each_idx'
|
||||
- 'perf_evlist__for_each_entry'
|
||||
- 'perf_evlist__for_each_entry_reverse'
|
||||
- 'perf_evlist__for_each_entry_safe'
|
||||
- 'perf_evlist__for_each_evsel'
|
||||
- 'perf_evlist__for_each_mmap'
|
||||
- 'perf_evsel_for_each_per_thread_period_safe'
|
||||
- 'perf_hpp_list__for_each_format'
|
||||
- 'perf_hpp_list__for_each_format_safe'
|
||||
- 'perf_hpp_list__for_each_sort_list'
|
||||
- 'perf_hpp_list__for_each_sort_list_safe'
|
||||
- 'plist_for_each'
|
||||
- 'plist_for_each_continue'
|
||||
- 'plist_for_each_entry'
|
||||
- 'plist_for_each_entry_continue'
|
||||
- 'plist_for_each_entry_safe'
|
||||
- 'plist_for_each_safe'
|
||||
- 'pnp_for_each_card'
|
||||
- 'pnp_for_each_dev'
|
||||
- 'protocol_for_each_card'
|
||||
- 'protocol_for_each_dev'
|
||||
- 'queue_for_each_hw_ctx'
|
||||
- 'radix_tree_for_each_slot'
|
||||
- 'radix_tree_for_each_tagged'
|
||||
- 'rb_for_each'
|
||||
- 'rbtree_postorder_for_each_entry_safe'
|
||||
- 'rdma_for_each_block'
|
||||
- 'rdma_for_each_port'
|
||||
- 'rdma_umem_for_each_dma_block'
|
||||
- 'resource_list_for_each_entry'
|
||||
- 'resource_list_for_each_entry_safe'
|
||||
- 'rhl_for_each_entry_rcu'
|
||||
- 'rhl_for_each_rcu'
|
||||
- 'rht_for_each'
|
||||
- 'rht_for_each_entry'
|
||||
- 'rht_for_each_entry_from'
|
||||
- 'rht_for_each_entry_rcu'
|
||||
- 'rht_for_each_entry_rcu_from'
|
||||
- 'rht_for_each_entry_safe'
|
||||
- 'rht_for_each_from'
|
||||
- 'rht_for_each_rcu'
|
||||
- 'rht_for_each_rcu_from'
|
||||
- 'rq_for_each_bvec'
|
||||
- 'rq_for_each_segment'
|
||||
- 'rq_list_for_each'
|
||||
- 'rq_list_for_each_safe'
|
||||
- 'sample_read_group__for_each'
|
||||
- 'scsi_for_each_prot_sg'
|
||||
- 'scsi_for_each_sg'
|
||||
- 'sctp_for_each_hentry'
|
||||
- 'sctp_skb_for_each'
|
||||
- 'sec_for_each_insn'
|
||||
- 'sec_for_each_insn_continue'
|
||||
- 'sec_for_each_insn_from'
|
||||
- 'sec_for_each_sym'
|
||||
- 'shdma_for_each_chan'
|
||||
- 'shost_for_each_device'
|
||||
- 'sk_for_each'
|
||||
- 'sk_for_each_bound'
|
||||
- 'sk_for_each_bound_safe'
|
||||
- 'sk_for_each_entry_offset_rcu'
|
||||
- 'sk_for_each_from'
|
||||
- 'sk_for_each_rcu'
|
||||
- 'sk_for_each_safe'
|
||||
- 'sk_nulls_for_each'
|
||||
- 'sk_nulls_for_each_from'
|
||||
- 'sk_nulls_for_each_rcu'
|
||||
- 'snd_array_for_each'
|
||||
- 'snd_pcm_group_for_each_entry'
|
||||
- 'snd_soc_dapm_widget_for_each_path'
|
||||
- 'snd_soc_dapm_widget_for_each_path_safe'
|
||||
- 'snd_soc_dapm_widget_for_each_sink_path'
|
||||
- 'snd_soc_dapm_widget_for_each_source_path'
|
||||
- 'sparsebit_for_each_set_range'
|
||||
- 'strlist__for_each_entry'
|
||||
- 'strlist__for_each_entry_safe'
|
||||
- 'sym_for_each_insn'
|
||||
- 'sym_for_each_insn_continue_reverse'
|
||||
- 'symbols__for_each_entry'
|
||||
- 'tb_property_for_each'
|
||||
- 'tcf_act_for_each_action'
|
||||
- 'tcf_exts_for_each_action'
|
||||
- 'test_suite__for_each_test_case'
|
||||
- 'tool_pmu__for_each_event'
|
||||
- 'ttm_bo_lru_for_each_reserved_guarded'
|
||||
- 'ttm_resource_manager_for_each_res'
|
||||
- 'udp_lrpa_for_each_entry_rcu'
|
||||
- 'udp_portaddr_for_each_entry'
|
||||
- 'udp_portaddr_for_each_entry_rcu'
|
||||
- 'usb_hub_for_each_child'
|
||||
- 'v4l2_device_for_each_subdev'
|
||||
- 'v4l2_m2m_for_each_dst_buf'
|
||||
- 'v4l2_m2m_for_each_dst_buf_safe'
|
||||
- 'v4l2_m2m_for_each_src_buf'
|
||||
- 'v4l2_m2m_for_each_src_buf_safe'
|
||||
- 'virtio_device_for_each_vq'
|
||||
- 'vkms_config_for_each_connector'
|
||||
- 'vkms_config_for_each_crtc'
|
||||
- 'vkms_config_for_each_encoder'
|
||||
- 'vkms_config_for_each_plane'
|
||||
- 'vkms_config_connector_for_each_possible_encoder'
|
||||
- 'vkms_config_encoder_for_each_possible_crtc'
|
||||
- 'vkms_config_plane_for_each_possible_crtc'
|
||||
- 'while_for_each_ftrace_op'
|
||||
- 'workloads__for_each'
|
||||
- 'xa_for_each'
|
||||
- 'xa_for_each_marked'
|
||||
- 'xa_for_each_range'
|
||||
- 'xa_for_each_start'
|
||||
- 'xas_for_each'
|
||||
- 'xas_for_each_conflict'
|
||||
- 'xas_for_each_marked'
|
||||
- 'xbc_array_for_each_value'
|
||||
- 'xbc_for_each_key_value'
|
||||
- 'xbc_node_for_each_array_value'
|
||||
- 'xbc_node_for_each_child'
|
||||
- 'xbc_node_for_each_key_value'
|
||||
- 'xbc_node_for_each_subkey'
|
||||
- 'ynl_attr_for_each'
|
||||
- 'ynl_attr_for_each_nested'
|
||||
- 'ynl_attr_for_each_payload'
|
||||
- 'zorro_for_each_dev'
|
||||
|
||||
IncludeBlocks: Preserve
|
||||
IncludeCategories:
|
||||
- Regex: '.*'
|
||||
Priority: 1
|
||||
IncludeIsMainRegex: '(Test)?$'
|
||||
IndentCaseLabels: false
|
||||
IndentGotoLabels: false
|
||||
IndentPPDirectives: None
|
||||
IndentWidth: 8
|
||||
IndentWrappedFunctionNames: false
|
||||
JavaScriptQuotes: Leave
|
||||
JavaScriptWrapImports: true
|
||||
KeepEmptyLinesAtTheStartOfBlocks: false
|
||||
MacroBlockBegin: ''
|
||||
MacroBlockEnd: ''
|
||||
MaxEmptyLinesToKeep: 1
|
||||
NamespaceIndentation: None
|
||||
ObjCBinPackProtocolList: Auto
|
||||
ObjCBlockIndentWidth: 8
|
||||
ObjCSpaceAfterProperty: true
|
||||
ObjCSpaceBeforeProtocolList: true
|
||||
|
||||
# Taken from git's rules
|
||||
PenaltyBreakAssignment: 10
|
||||
PenaltyBreakBeforeFirstCallParameter: 30
|
||||
PenaltyBreakComment: 10
|
||||
PenaltyBreakFirstLessLess: 0
|
||||
PenaltyBreakString: 10
|
||||
PenaltyExcessCharacter: 100
|
||||
PenaltyReturnTypeOnItsOwnLine: 60
|
||||
|
||||
PointerAlignment: Right
|
||||
ReflowComments: false
|
||||
SortIncludes: false
|
||||
SortUsingDeclarations: false
|
||||
SpaceAfterCStyleCast: false
|
||||
SpaceAfterTemplateKeyword: true
|
||||
SpaceBeforeAssignmentOperators: true
|
||||
SpaceBeforeCtorInitializerColon: true
|
||||
SpaceBeforeInheritanceColon: true
|
||||
SpaceBeforeParens: ControlStatementsExceptForEachMacros
|
||||
SpaceBeforeRangeBasedForLoopColon: true
|
||||
SpaceInEmptyParentheses: false
|
||||
SpacesBeforeTrailingComments: 1
|
||||
SpacesInAngles: false
|
||||
SpacesInContainerLiterals: false
|
||||
SpacesInCStyleCastParentheses: false
|
||||
SpacesInParentheses: false
|
||||
SpacesInSquareBrackets: false
|
||||
Standard: Cpp03
|
||||
TabWidth: 8
|
||||
UseTab: Always
|
||||
...
|
||||
1
.gitignore
vendored
1
.gitignore
vendored
@ -58,6 +58,7 @@ fit-dtb.blob*
|
||||
#
|
||||
# We don't want to ignore the following even if they are dot-files
|
||||
#
|
||||
!.clang-format
|
||||
!.get_maintainer.*
|
||||
!.gitattributes
|
||||
!.gitignore
|
||||
|
||||
@ -43,11 +43,11 @@ stages:
|
||||
- ln -s u_boot_boardenv_qemu_arm64_na.py /tmp/uboot-test-hooks/py/travis-ci/u_boot_boardenv_qemu_arm64_lwip_na.py
|
||||
- ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
|
||||
- ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
|
||||
- if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
|
||||
- if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]] || [[ "${TEST_PY_BD}" == "xilinx_mbv32_smode" ]]; then
|
||||
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
|
||||
export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
|
||||
fi
|
||||
- if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
|
||||
- if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]] || [[ "${TEST_PY_BD}" == "xilinx_mbv64_smode" ]]; then
|
||||
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
|
||||
export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
|
||||
fi
|
||||
@ -550,6 +550,34 @@ vexpress_fvp_bloblist test.py:
|
||||
- ${DEFAULT_AMD64_TAG}
|
||||
<<: *buildman_and_testpy_dfn
|
||||
|
||||
xilinx_mbv32 test.py:
|
||||
variables:
|
||||
TEST_PY_BD: "xilinx_mbv32"
|
||||
TEST_PY_TEST_SPEC: "not sleep"
|
||||
TEST_PY_ID: "--id qemu"
|
||||
<<: *buildman_and_testpy_dfn
|
||||
|
||||
xilinx_mbv32_smode test.py:
|
||||
variables:
|
||||
TEST_PY_BD: "xilinx_mbv32_smode"
|
||||
TEST_PY_TEST_SPEC: "not sleep"
|
||||
TEST_PY_ID: "--id qemu"
|
||||
<<: *buildman_and_testpy_dfn
|
||||
|
||||
xilinx_mbv64 test.py:
|
||||
variables:
|
||||
TEST_PY_BD: "xilinx_mbv64"
|
||||
TEST_PY_TEST_SPEC: "not sleep"
|
||||
TEST_PY_ID: "--id qemu"
|
||||
<<: *buildman_and_testpy_dfn
|
||||
|
||||
xilinx_mbv64_smode test.py:
|
||||
variables:
|
||||
TEST_PY_BD: "xilinx_mbv64_smode"
|
||||
TEST_PY_TEST_SPEC: "not sleep"
|
||||
TEST_PY_ID: "--id qemu"
|
||||
<<: *buildman_and_testpy_dfn
|
||||
|
||||
xilinx_zynq_virt test.py:
|
||||
variables:
|
||||
TEST_PY_BD: "xilinx_zynq_virt"
|
||||
|
||||
@ -422,6 +422,8 @@ F: drivers/clk/mediatek/
|
||||
F: drivers/cpu/mtk_cpu.c
|
||||
F: drivers/i2c/mtk_i2c.c
|
||||
F: drivers/mmc/mtk-sd.c
|
||||
F: drivers/net/mtk_eth/
|
||||
F: drivers/net/phy/mediatek/
|
||||
F: drivers/phy/phy-mtk-*
|
||||
F: drivers/pinctrl/mediatek/
|
||||
F: drivers/power/domain/mtk-power-domain.c
|
||||
@ -436,8 +438,6 @@ F: drivers/timer/mtk_timer.c
|
||||
F: drivers/usb/host/xhci-mtk.c
|
||||
F: drivers/usb/mtu3/
|
||||
F: drivers/watchdog/mtk_wdt.c
|
||||
F: drivers/net/mtk_eth.c
|
||||
F: drivers/net/mtk_eth.h
|
||||
F: drivers/reset/reset-mediatek.c
|
||||
F: drivers/serial/serial_mtk.c
|
||||
F: include/dt-bindings/clock/mediatek,*
|
||||
@ -708,6 +708,7 @@ F: drivers/gpio/stm32_gpio.c
|
||||
F: drivers/hwspinlock/stm32_hwspinlock.c
|
||||
F: drivers/i2c/stm32f7_i2c.c
|
||||
F: drivers/mailbox/stm32-ipcc.c
|
||||
F: drivers/memory/stm32-omm.c
|
||||
F: drivers/misc/stm32mp_fuse.c
|
||||
F: drivers/misc/stm32_rcc.c
|
||||
F: drivers/mmc/stm32_sdmmc2.c
|
||||
@ -724,6 +725,7 @@ F: drivers/rng/optee_rng.c
|
||||
F: drivers/rng/stm32_rng.c
|
||||
F: drivers/rtc/stm32_rtc.c
|
||||
F: drivers/serial/serial_stm32.*
|
||||
F: drivers/spi/stm32_ospi.c
|
||||
F: drivers/spi/stm32_qspi.c
|
||||
F: drivers/spi/stm32_spi.c
|
||||
F: drivers/video/stm32/stm32_ltdc.c
|
||||
|
||||
11
README
11
README
@ -390,17 +390,6 @@ The following options need to be configured:
|
||||
CONFIG_TPM_TIS_I2C_BURST_LIMITATION
|
||||
Define the burst count bytes upper limit
|
||||
|
||||
CONFIG_TPM_ST33ZP24
|
||||
Support for STMicroelectronics TPM devices. Requires DM_TPM support.
|
||||
|
||||
CONFIG_TPM_ST33ZP24_I2C
|
||||
Support for STMicroelectronics ST33ZP24 I2C devices.
|
||||
Requires TPM_ST33ZP24 and I2C.
|
||||
|
||||
CONFIG_TPM_ST33ZP24_SPI
|
||||
Support for STMicroelectronics ST33ZP24 SPI devices.
|
||||
Requires TPM_ST33ZP24 and SPI.
|
||||
|
||||
CONFIG_TPM_ATMEL_TWI
|
||||
Support for Atmel TWI TPM device. Requires I2C support.
|
||||
|
||||
|
||||
@ -68,10 +68,10 @@ config INIT_SP_RELATIVE
|
||||
SYS_INIT_SP_BSS_OFFSET.
|
||||
|
||||
config SYS_INIT_SP_BSS_OFFSET
|
||||
int "Early stack offset from the .bss base address"
|
||||
hex "Early stack offset from the .bss base address"
|
||||
depends on ARM64
|
||||
depends on INIT_SP_RELATIVE
|
||||
default 524288
|
||||
default 0x80000
|
||||
help
|
||||
This option's value is the offset added to &_bss_start in order to
|
||||
calculate the stack pointer. This offset should be large enough so
|
||||
@ -1418,6 +1418,8 @@ config ARCH_VEXPRESS64
|
||||
select MTD_NOR_FLASH if MTD
|
||||
select FLASH_CFI_DRIVER if MTD
|
||||
select ENV_IS_IN_FLASH if MTD
|
||||
select SYSRESET
|
||||
select SYSRESET_PSCI if ARM_PSCI_FW
|
||||
imply DISTRO_DEFAULTS
|
||||
|
||||
config TARGET_CORSTONE1000
|
||||
|
||||
@ -32,7 +32,6 @@ ifneq (,$(filter s5pc1xx exynos,$(SOC)))
|
||||
obj-y += s5p-common/
|
||||
endif
|
||||
|
||||
obj-$(if $(filter bcm235xx,$(SOC)),y) += bcm235xx/
|
||||
obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
|
||||
obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
|
||||
obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
|
||||
|
||||
@ -1,10 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright 2013 Broadcom Corporation.
|
||||
|
||||
obj-y += clk-core.o
|
||||
obj-y += clk-bcm235xx.o
|
||||
obj-y += clk-sdio.o
|
||||
obj-y += clk-bsc.o
|
||||
obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
|
||||
obj-y += clk-usb-otg.o
|
||||
@ -1,567 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2013 Broadcom Corporation.
|
||||
*/
|
||||
|
||||
/*
|
||||
*
|
||||
* bcm235xx-specific clock tables
|
||||
*
|
||||
*/
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <linux/errno.h>
|
||||
#include <asm/arch/sysmap.h>
|
||||
#include <asm/kona-common/clk.h>
|
||||
#include "clk-core.h"
|
||||
|
||||
#define CLOCK_1K 1000
|
||||
#define CLOCK_1M (CLOCK_1K * 1000)
|
||||
|
||||
/* declare a reference clock */
|
||||
#define DECLARE_REF_CLK(clk_name, clk_parent, clk_rate, clk_div) \
|
||||
static struct refclk clk_name = { \
|
||||
.clk = { \
|
||||
.name = #clk_name, \
|
||||
.parent = clk_parent, \
|
||||
.rate = clk_rate, \
|
||||
.div = clk_div, \
|
||||
.ops = &ref_clk_ops, \
|
||||
}, \
|
||||
}
|
||||
|
||||
/*
|
||||
* Reference clocks
|
||||
*/
|
||||
|
||||
/* Declare a list of reference clocks */
|
||||
DECLARE_REF_CLK(ref_crystal, 0, 26 * CLOCK_1M, 1);
|
||||
DECLARE_REF_CLK(var_96m, 0, 96 * CLOCK_1M, 1);
|
||||
DECLARE_REF_CLK(ref_96m, 0, 96 * CLOCK_1M, 1);
|
||||
DECLARE_REF_CLK(ref_312m, 0, 312 * CLOCK_1M, 0);
|
||||
DECLARE_REF_CLK(ref_104m, &ref_312m.clk, 104 * CLOCK_1M, 3);
|
||||
DECLARE_REF_CLK(ref_52m, &ref_104m.clk, 52 * CLOCK_1M, 2);
|
||||
DECLARE_REF_CLK(ref_13m, &ref_52m.clk, 13 * CLOCK_1M, 4);
|
||||
DECLARE_REF_CLK(var_312m, 0, 312 * CLOCK_1M, 0);
|
||||
DECLARE_REF_CLK(var_104m, &var_312m.clk, 104 * CLOCK_1M, 3);
|
||||
DECLARE_REF_CLK(var_52m, &var_104m.clk, 52 * CLOCK_1M, 2);
|
||||
DECLARE_REF_CLK(var_13m, &var_52m.clk, 13 * CLOCK_1M, 4);
|
||||
|
||||
struct refclk_lkup {
|
||||
struct refclk *procclk;
|
||||
const char *name;
|
||||
};
|
||||
|
||||
/* Lookup table for string to clk tranlation */
|
||||
#define MKSTR(x) {&x, #x}
|
||||
static struct refclk_lkup refclk_str_tbl[] = {
|
||||
MKSTR(ref_crystal), MKSTR(var_96m), MKSTR(ref_96m),
|
||||
MKSTR(ref_312m), MKSTR(ref_104m), MKSTR(ref_52m),
|
||||
MKSTR(ref_13m), MKSTR(var_312m), MKSTR(var_104m),
|
||||
MKSTR(var_52m), MKSTR(var_13m),
|
||||
};
|
||||
|
||||
int refclk_entries = sizeof(refclk_str_tbl)/sizeof(refclk_str_tbl[0]);
|
||||
|
||||
/* convert ref clock string to clock structure pointer */
|
||||
struct refclk *refclk_str_to_clk(const char *name)
|
||||
{
|
||||
int i;
|
||||
struct refclk_lkup *tblp = refclk_str_tbl;
|
||||
for (i = 0; i < refclk_entries; i++, tblp++) {
|
||||
if (!(strcmp(name, tblp->name)))
|
||||
return tblp->procclk;
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* frequency tables indexed by freq_id */
|
||||
unsigned long master_axi_freq_tbl[8] = {
|
||||
26 * CLOCK_1M,
|
||||
52 * CLOCK_1M,
|
||||
104 * CLOCK_1M,
|
||||
156 * CLOCK_1M,
|
||||
156 * CLOCK_1M,
|
||||
208 * CLOCK_1M,
|
||||
312 * CLOCK_1M,
|
||||
312 * CLOCK_1M
|
||||
};
|
||||
|
||||
unsigned long master_ahb_freq_tbl[8] = {
|
||||
26 * CLOCK_1M,
|
||||
52 * CLOCK_1M,
|
||||
52 * CLOCK_1M,
|
||||
52 * CLOCK_1M,
|
||||
78 * CLOCK_1M,
|
||||
104 * CLOCK_1M,
|
||||
104 * CLOCK_1M,
|
||||
156 * CLOCK_1M
|
||||
};
|
||||
|
||||
unsigned long slave_axi_freq_tbl[8] = {
|
||||
26 * CLOCK_1M,
|
||||
52 * CLOCK_1M,
|
||||
78 * CLOCK_1M,
|
||||
104 * CLOCK_1M,
|
||||
156 * CLOCK_1M,
|
||||
156 * CLOCK_1M
|
||||
};
|
||||
|
||||
unsigned long slave_apb_freq_tbl[8] = {
|
||||
26 * CLOCK_1M,
|
||||
26 * CLOCK_1M,
|
||||
39 * CLOCK_1M,
|
||||
52 * CLOCK_1M,
|
||||
52 * CLOCK_1M,
|
||||
78 * CLOCK_1M
|
||||
};
|
||||
|
||||
unsigned long esub_freq_tbl[8] = {
|
||||
78 * CLOCK_1M,
|
||||
156 * CLOCK_1M,
|
||||
156 * CLOCK_1M,
|
||||
156 * CLOCK_1M,
|
||||
208 * CLOCK_1M,
|
||||
208 * CLOCK_1M,
|
||||
208 * CLOCK_1M
|
||||
};
|
||||
|
||||
static struct bus_clk_data bsc1_apb_data = {
|
||||
.gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
|
||||
};
|
||||
|
||||
static struct bus_clk_data bsc2_apb_data = {
|
||||
.gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1),
|
||||
};
|
||||
|
||||
static struct bus_clk_data bsc3_apb_data = {
|
||||
.gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1),
|
||||
};
|
||||
|
||||
/* * Master CCU clocks */
|
||||
static struct peri_clk_data sdio1_data = {
|
||||
.gate = HW_SW_GATE(0x0358, 18, 2, 3),
|
||||
.clocks = CLOCKS("ref_crystal",
|
||||
"var_52m",
|
||||
"ref_52m",
|
||||
"var_96m",
|
||||
"ref_96m"),
|
||||
.sel = SELECTOR(0x0a28, 0, 3),
|
||||
.div = DIVIDER(0x0a28, 4, 14),
|
||||
.trig = TRIGGER(0x0afc, 9),
|
||||
};
|
||||
|
||||
static struct peri_clk_data sdio2_data = {
|
||||
.gate = HW_SW_GATE(0x035c, 18, 2, 3),
|
||||
.clocks = CLOCKS("ref_crystal",
|
||||
"var_52m",
|
||||
"ref_52m",
|
||||
"var_96m",
|
||||
"ref_96m"),
|
||||
.sel = SELECTOR(0x0a2c, 0, 3),
|
||||
.div = DIVIDER(0x0a2c, 4, 14),
|
||||
.trig = TRIGGER(0x0afc, 10),
|
||||
};
|
||||
|
||||
static struct peri_clk_data sdio3_data = {
|
||||
.gate = HW_SW_GATE(0x0364, 18, 2, 3),
|
||||
.clocks = CLOCKS("ref_crystal",
|
||||
"var_52m",
|
||||
"ref_52m",
|
||||
"var_96m",
|
||||
"ref_96m"),
|
||||
.sel = SELECTOR(0x0a34, 0, 3),
|
||||
.div = DIVIDER(0x0a34, 4, 14),
|
||||
.trig = TRIGGER(0x0afc, 12),
|
||||
};
|
||||
|
||||
static struct peri_clk_data sdio4_data = {
|
||||
.gate = HW_SW_GATE(0x0360, 18, 2, 3),
|
||||
.clocks = CLOCKS("ref_crystal",
|
||||
"var_52m",
|
||||
"ref_52m",
|
||||
"var_96m",
|
||||
"ref_96m"),
|
||||
.sel = SELECTOR(0x0a30, 0, 3),
|
||||
.div = DIVIDER(0x0a30, 4, 14),
|
||||
.trig = TRIGGER(0x0afc, 11),
|
||||
};
|
||||
|
||||
static struct peri_clk_data sdio1_sleep_data = {
|
||||
.clocks = CLOCKS("ref_32k"),
|
||||
.gate = SW_ONLY_GATE(0x0358, 20, 4),
|
||||
};
|
||||
|
||||
static struct peri_clk_data sdio2_sleep_data = {
|
||||
.clocks = CLOCKS("ref_32k"),
|
||||
.gate = SW_ONLY_GATE(0x035c, 20, 4),
|
||||
};
|
||||
|
||||
static struct peri_clk_data sdio3_sleep_data = {
|
||||
.clocks = CLOCKS("ref_32k"),
|
||||
.gate = SW_ONLY_GATE(0x0364, 20, 4),
|
||||
};
|
||||
|
||||
static struct peri_clk_data sdio4_sleep_data = {
|
||||
.clocks = CLOCKS("ref_32k"),
|
||||
.gate = SW_ONLY_GATE(0x0360, 20, 4),
|
||||
};
|
||||
|
||||
static struct bus_clk_data usb_otg_ahb_data = {
|
||||
.gate = HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
|
||||
};
|
||||
|
||||
static struct bus_clk_data sdio1_ahb_data = {
|
||||
.gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
|
||||
};
|
||||
|
||||
static struct bus_clk_data sdio2_ahb_data = {
|
||||
.gate = HW_SW_GATE_AUTO(0x035c, 16, 0, 1),
|
||||
};
|
||||
|
||||
static struct bus_clk_data sdio3_ahb_data = {
|
||||
.gate = HW_SW_GATE_AUTO(0x0364, 16, 0, 1),
|
||||
};
|
||||
|
||||
static struct bus_clk_data sdio4_ahb_data = {
|
||||
.gate = HW_SW_GATE_AUTO(0x0360, 16, 0, 1),
|
||||
};
|
||||
|
||||
/* * Slave CCU clocks */
|
||||
static struct peri_clk_data bsc1_data = {
|
||||
.gate = HW_SW_GATE(0x0458, 18, 2, 3),
|
||||
.clocks = CLOCKS("ref_crystal",
|
||||
"var_104m",
|
||||
"ref_104m",
|
||||
"var_13m",
|
||||
"ref_13m"),
|
||||
.sel = SELECTOR(0x0a64, 0, 3),
|
||||
.trig = TRIGGER(0x0afc, 23),
|
||||
};
|
||||
|
||||
static struct peri_clk_data bsc2_data = {
|
||||
.gate = HW_SW_GATE(0x045c, 18, 2, 3),
|
||||
.clocks = CLOCKS("ref_crystal",
|
||||
"var_104m",
|
||||
"ref_104m",
|
||||
"var_13m",
|
||||
"ref_13m"),
|
||||
.sel = SELECTOR(0x0a68, 0, 3),
|
||||
.trig = TRIGGER(0x0afc, 24),
|
||||
};
|
||||
|
||||
static struct peri_clk_data bsc3_data = {
|
||||
.gate = HW_SW_GATE(0x0484, 18, 2, 3),
|
||||
.clocks = CLOCKS("ref_crystal",
|
||||
"var_104m",
|
||||
"ref_104m",
|
||||
"var_13m",
|
||||
"ref_13m"),
|
||||
.sel = SELECTOR(0x0a84, 0, 3),
|
||||
.trig = TRIGGER(0x0b00, 2),
|
||||
};
|
||||
|
||||
/*
|
||||
* CCU clocks
|
||||
*/
|
||||
|
||||
static struct ccu_clock kpm_ccu_clk = {
|
||||
.clk = {
|
||||
.name = "kpm_ccu_clk",
|
||||
.ops = &ccu_clk_ops,
|
||||
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
|
||||
},
|
||||
.num_policy_masks = 1,
|
||||
.policy_freq_offset = 0x00000008,
|
||||
.freq_bit_shift = 8,
|
||||
.policy_ctl_offset = 0x0000000c,
|
||||
.policy0_mask_offset = 0x00000010,
|
||||
.policy1_mask_offset = 0x00000014,
|
||||
.policy2_mask_offset = 0x00000018,
|
||||
.policy3_mask_offset = 0x0000001c,
|
||||
.lvm_en_offset = 0x00000034,
|
||||
.freq_id = 2,
|
||||
.freq_tbl = master_axi_freq_tbl,
|
||||
};
|
||||
|
||||
static struct ccu_clock kps_ccu_clk = {
|
||||
.clk = {
|
||||
.name = "kps_ccu_clk",
|
||||
.ops = &ccu_clk_ops,
|
||||
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
|
||||
},
|
||||
.num_policy_masks = 1,
|
||||
.policy_freq_offset = 0x00000008,
|
||||
.freq_bit_shift = 8,
|
||||
.policy_ctl_offset = 0x0000000c,
|
||||
.policy0_mask_offset = 0x00000010,
|
||||
.policy1_mask_offset = 0x00000014,
|
||||
.policy2_mask_offset = 0x00000018,
|
||||
.policy3_mask_offset = 0x0000001c,
|
||||
.lvm_en_offset = 0x00000034,
|
||||
.freq_id = 2,
|
||||
.freq_tbl = slave_axi_freq_tbl,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_BCM_SF2_ETH
|
||||
static struct ccu_clock esub_ccu_clk = {
|
||||
.clk = {
|
||||
.name = "esub_ccu_clk",
|
||||
.ops = &ccu_clk_ops,
|
||||
.ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR,
|
||||
},
|
||||
.num_policy_masks = 1,
|
||||
.policy_freq_offset = 0x00000008,
|
||||
.freq_bit_shift = 8,
|
||||
.policy_ctl_offset = 0x0000000c,
|
||||
.policy0_mask_offset = 0x00000010,
|
||||
.policy1_mask_offset = 0x00000014,
|
||||
.policy2_mask_offset = 0x00000018,
|
||||
.policy3_mask_offset = 0x0000001c,
|
||||
.lvm_en_offset = 0x00000034,
|
||||
.freq_id = 2,
|
||||
.freq_tbl = esub_freq_tbl,
|
||||
};
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Bus clocks
|
||||
*/
|
||||
|
||||
/* KPM bus clocks */
|
||||
static struct bus_clock usb_otg_ahb_clk = {
|
||||
.clk = {
|
||||
.name = "usb_otg_ahb_clk",
|
||||
.parent = &kpm_ccu_clk.clk,
|
||||
.ops = &bus_clk_ops,
|
||||
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
|
||||
},
|
||||
.freq_tbl = master_ahb_freq_tbl,
|
||||
.data = &usb_otg_ahb_data,
|
||||
};
|
||||
|
||||
static struct bus_clock sdio1_ahb_clk = {
|
||||
.clk = {
|
||||
.name = "sdio1_ahb_clk",
|
||||
.parent = &kpm_ccu_clk.clk,
|
||||
.ops = &bus_clk_ops,
|
||||
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
|
||||
},
|
||||
.freq_tbl = master_ahb_freq_tbl,
|
||||
.data = &sdio1_ahb_data,
|
||||
};
|
||||
|
||||
static struct bus_clock sdio2_ahb_clk = {
|
||||
.clk = {
|
||||
.name = "sdio2_ahb_clk",
|
||||
.parent = &kpm_ccu_clk.clk,
|
||||
.ops = &bus_clk_ops,
|
||||
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
|
||||
},
|
||||
.freq_tbl = master_ahb_freq_tbl,
|
||||
.data = &sdio2_ahb_data,
|
||||
};
|
||||
|
||||
static struct bus_clock sdio3_ahb_clk = {
|
||||
.clk = {
|
||||
.name = "sdio3_ahb_clk",
|
||||
.parent = &kpm_ccu_clk.clk,
|
||||
.ops = &bus_clk_ops,
|
||||
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
|
||||
},
|
||||
.freq_tbl = master_ahb_freq_tbl,
|
||||
.data = &sdio3_ahb_data,
|
||||
};
|
||||
|
||||
static struct bus_clock sdio4_ahb_clk = {
|
||||
.clk = {
|
||||
.name = "sdio4_ahb_clk",
|
||||
.parent = &kpm_ccu_clk.clk,
|
||||
.ops = &bus_clk_ops,
|
||||
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
|
||||
},
|
||||
.freq_tbl = master_ahb_freq_tbl,
|
||||
.data = &sdio4_ahb_data,
|
||||
};
|
||||
|
||||
static struct bus_clock bsc1_apb_clk = {
|
||||
.clk = {
|
||||
.name = "bsc1_apb_clk",
|
||||
.parent = &kps_ccu_clk.clk,
|
||||
.ops = &bus_clk_ops,
|
||||
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
|
||||
},
|
||||
.freq_tbl = slave_apb_freq_tbl,
|
||||
.data = &bsc1_apb_data,
|
||||
};
|
||||
|
||||
static struct bus_clock bsc2_apb_clk = {
|
||||
.clk = {
|
||||
.name = "bsc2_apb_clk",
|
||||
.parent = &kps_ccu_clk.clk,
|
||||
.ops = &bus_clk_ops,
|
||||
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
|
||||
},
|
||||
.freq_tbl = slave_apb_freq_tbl,
|
||||
.data = &bsc2_apb_data,
|
||||
};
|
||||
|
||||
static struct bus_clock bsc3_apb_clk = {
|
||||
.clk = {
|
||||
.name = "bsc3_apb_clk",
|
||||
.parent = &kps_ccu_clk.clk,
|
||||
.ops = &bus_clk_ops,
|
||||
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
|
||||
},
|
||||
.freq_tbl = slave_apb_freq_tbl,
|
||||
.data = &bsc3_apb_data,
|
||||
};
|
||||
|
||||
/* KPM peripheral */
|
||||
static struct peri_clock sdio1_clk = {
|
||||
.clk = {
|
||||
.name = "sdio1_clk",
|
||||
.parent = &ref_52m.clk,
|
||||
.ops = &peri_clk_ops,
|
||||
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
|
||||
},
|
||||
.data = &sdio1_data,
|
||||
};
|
||||
|
||||
static struct peri_clock sdio2_clk = {
|
||||
.clk = {
|
||||
.name = "sdio2_clk",
|
||||
.parent = &ref_52m.clk,
|
||||
.ops = &peri_clk_ops,
|
||||
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
|
||||
},
|
||||
.data = &sdio2_data,
|
||||
};
|
||||
|
||||
static struct peri_clock sdio3_clk = {
|
||||
.clk = {
|
||||
.name = "sdio3_clk",
|
||||
.parent = &ref_52m.clk,
|
||||
.ops = &peri_clk_ops,
|
||||
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
|
||||
},
|
||||
.data = &sdio3_data,
|
||||
};
|
||||
|
||||
static struct peri_clock sdio4_clk = {
|
||||
.clk = {
|
||||
.name = "sdio4_clk",
|
||||
.parent = &ref_52m.clk,
|
||||
.ops = &peri_clk_ops,
|
||||
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
|
||||
},
|
||||
.data = &sdio4_data,
|
||||
};
|
||||
|
||||
static struct peri_clock sdio1_sleep_clk = {
|
||||
.clk = {
|
||||
.name = "sdio1_sleep_clk",
|
||||
.parent = &kpm_ccu_clk.clk,
|
||||
.ops = &bus_clk_ops,
|
||||
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
|
||||
},
|
||||
.data = &sdio1_sleep_data,
|
||||
};
|
||||
|
||||
static struct peri_clock sdio2_sleep_clk = {
|
||||
.clk = {
|
||||
.name = "sdio2_sleep_clk",
|
||||
.parent = &kpm_ccu_clk.clk,
|
||||
.ops = &bus_clk_ops,
|
||||
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
|
||||
},
|
||||
.data = &sdio2_sleep_data,
|
||||
};
|
||||
|
||||
static struct peri_clock sdio3_sleep_clk = {
|
||||
.clk = {
|
||||
.name = "sdio3_sleep_clk",
|
||||
.parent = &kpm_ccu_clk.clk,
|
||||
.ops = &bus_clk_ops,
|
||||
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
|
||||
},
|
||||
.data = &sdio3_sleep_data,
|
||||
};
|
||||
|
||||
static struct peri_clock sdio4_sleep_clk = {
|
||||
.clk = {
|
||||
.name = "sdio4_sleep_clk",
|
||||
.parent = &kpm_ccu_clk.clk,
|
||||
.ops = &bus_clk_ops,
|
||||
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
|
||||
},
|
||||
.data = &sdio4_sleep_data,
|
||||
};
|
||||
|
||||
/* KPS peripheral clock */
|
||||
static struct peri_clock bsc1_clk = {
|
||||
.clk = {
|
||||
.name = "bsc1_clk",
|
||||
.parent = &ref_13m.clk,
|
||||
.rate = 13 * CLOCK_1M,
|
||||
.div = 1,
|
||||
.ops = &peri_clk_ops,
|
||||
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
|
||||
},
|
||||
.data = &bsc1_data,
|
||||
};
|
||||
|
||||
static struct peri_clock bsc2_clk = {
|
||||
.clk = {
|
||||
.name = "bsc2_clk",
|
||||
.parent = &ref_13m.clk,
|
||||
.rate = 13 * CLOCK_1M,
|
||||
.div = 1,
|
||||
.ops = &peri_clk_ops,
|
||||
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
|
||||
},
|
||||
.data = &bsc2_data,
|
||||
};
|
||||
|
||||
static struct peri_clock bsc3_clk = {
|
||||
.clk = {
|
||||
.name = "bsc3_clk",
|
||||
.parent = &ref_13m.clk,
|
||||
.rate = 13 * CLOCK_1M,
|
||||
.div = 1,
|
||||
.ops = &peri_clk_ops,
|
||||
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
|
||||
},
|
||||
.data = &bsc3_data,
|
||||
};
|
||||
|
||||
/* public table for registering clocks */
|
||||
struct clk_lookup arch_clk_tbl[] = {
|
||||
/* Peripheral clocks */
|
||||
CLK_LK(sdio1),
|
||||
CLK_LK(sdio2),
|
||||
CLK_LK(sdio3),
|
||||
CLK_LK(sdio4),
|
||||
CLK_LK(sdio1_sleep),
|
||||
CLK_LK(sdio2_sleep),
|
||||
CLK_LK(sdio3_sleep),
|
||||
CLK_LK(sdio4_sleep),
|
||||
CLK_LK(bsc1),
|
||||
CLK_LK(bsc2),
|
||||
CLK_LK(bsc3),
|
||||
/* Bus clocks */
|
||||
CLK_LK(usb_otg_ahb),
|
||||
CLK_LK(sdio1_ahb),
|
||||
CLK_LK(sdio2_ahb),
|
||||
CLK_LK(sdio3_ahb),
|
||||
CLK_LK(sdio4_ahb),
|
||||
CLK_LK(bsc1_apb),
|
||||
CLK_LK(bsc2_apb),
|
||||
CLK_LK(bsc3_apb),
|
||||
#ifdef CONFIG_BCM_SF2_ETH
|
||||
CLK_LK(esub_ccu),
|
||||
#endif
|
||||
};
|
||||
|
||||
/* public array size */
|
||||
unsigned int arch_clk_tbl_array_size = ARRAY_SIZE(arch_clk_tbl);
|
||||
@ -1,50 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2013 Broadcom Corporation.
|
||||
*/
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <linux/errno.h>
|
||||
#include <asm/arch/sysmap.h>
|
||||
#include <asm/kona-common/clk.h>
|
||||
#include "clk-core.h"
|
||||
|
||||
/* Enable appropriate clocks for a BSC/I2C port */
|
||||
int clk_bsc_enable(void *base)
|
||||
{
|
||||
int ret;
|
||||
char *bscstr, *apbstr;
|
||||
|
||||
switch ((u32) base) {
|
||||
case PMU_BSC_BASE_ADDR:
|
||||
/* PMU clock is always enabled */
|
||||
return 0;
|
||||
case BSC1_BASE_ADDR:
|
||||
bscstr = "bsc1_clk";
|
||||
apbstr = "bsc1_apb_clk";
|
||||
break;
|
||||
case BSC2_BASE_ADDR:
|
||||
bscstr = "bsc2_clk";
|
||||
apbstr = "bsc2_apb_clk";
|
||||
break;
|
||||
case BSC3_BASE_ADDR:
|
||||
bscstr = "bsc3_clk";
|
||||
apbstr = "bsc3_apb_clk";
|
||||
break;
|
||||
default:
|
||||
printf("%s: base 0x%p not found\n", __func__, base);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Note that the bus clock must be enabled first */
|
||||
|
||||
ret = clk_get_and_enable(apbstr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_get_and_enable(bscstr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1,512 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2013 Broadcom Corporation.
|
||||
*/
|
||||
|
||||
/*
|
||||
*
|
||||
* bcm235xx architecture clock framework
|
||||
*
|
||||
*/
|
||||
|
||||
#include <log.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/errno.h>
|
||||
#include <bitfield.h>
|
||||
#include <asm/arch/sysmap.h>
|
||||
#include <asm/kona-common/clk.h>
|
||||
#include "clk-core.h"
|
||||
|
||||
#define CLK_WR_ACCESS_PASSWORD 0x00a5a501
|
||||
#define WR_ACCESS_OFFSET 0 /* common to all clock blocks */
|
||||
#define POLICY_CTL_GO 1 /* Load and refresh policy masks */
|
||||
#define POLICY_CTL_GO_ATL 4 /* Active Load */
|
||||
|
||||
/* Helper function */
|
||||
int clk_get_and_enable(char *clkstr)
|
||||
{
|
||||
int ret = 0;
|
||||
struct clk *c;
|
||||
|
||||
debug("%s: %s\n", __func__, clkstr);
|
||||
|
||||
c = clk_get(clkstr);
|
||||
if (c) {
|
||||
ret = clk_enable(c);
|
||||
if (ret)
|
||||
return ret;
|
||||
} else {
|
||||
printf("%s: Couldn't find %s\n", __func__, clkstr);
|
||||
return -EINVAL;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Poll a register in a CCU's address space, returning when the
|
||||
* specified bit in that register's value is set (or clear). Delay
|
||||
* a microsecond after each read of the register. Returns true if
|
||||
* successful, or false if we gave up trying.
|
||||
*
|
||||
* Caller must ensure the CCU lock is held.
|
||||
*/
|
||||
#define CLK_GATE_DELAY_USEC 2000
|
||||
static inline int wait_bit(void *base, u32 offset, u32 bit, bool want)
|
||||
{
|
||||
unsigned int tries;
|
||||
u32 bit_mask = 1 << bit;
|
||||
|
||||
for (tries = 0; tries < CLK_GATE_DELAY_USEC; tries++) {
|
||||
u32 val;
|
||||
bool bit_val;
|
||||
|
||||
val = readl(base + offset);
|
||||
bit_val = (val & bit_mask) ? 1 : 0;
|
||||
if (bit_val == want)
|
||||
return 0; /* success */
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
debug("%s: timeout on addr 0x%p, waiting for bit %d to go to %d\n",
|
||||
__func__, base + offset, bit, want);
|
||||
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
/* Enable a peripheral clock */
|
||||
static int peri_clk_enable(struct clk *c, int enable)
|
||||
{
|
||||
int ret = 0;
|
||||
u32 reg;
|
||||
struct peri_clock *peri_clk = to_peri_clk(c);
|
||||
struct peri_clk_data *cd = peri_clk->data;
|
||||
struct bcm_clk_gate *gate = &cd->gate;
|
||||
void *base = (void *)c->ccu_clk_mgr_base;
|
||||
|
||||
debug("%s: %s\n", __func__, c->name);
|
||||
|
||||
clk_get_rate(c); /* Make sure rate and sel are filled in */
|
||||
|
||||
/* enable access */
|
||||
writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
|
||||
|
||||
if (enable) {
|
||||
debug("%s %s set rate %lu div %lu sel %d parent %lu\n",
|
||||
__func__, c->name, c->rate, c->div, c->sel,
|
||||
c->parent->rate);
|
||||
|
||||
/*
|
||||
* clkgate - only software controllable gates are
|
||||
* supported by u-boot which includes all clocks
|
||||
* that matter. This avoids bringing in a lot of extra
|
||||
* complexity as done in the kernel framework.
|
||||
*/
|
||||
if (gate_exists(gate)) {
|
||||
reg = readl(base + cd->gate.offset);
|
||||
reg |= (1 << cd->gate.en_bit);
|
||||
writel(reg, base + cd->gate.offset);
|
||||
}
|
||||
|
||||
/* div and pll select */
|
||||
if (divider_exists(&cd->div)) {
|
||||
reg = readl(base + cd->div.offset);
|
||||
bitfield_replace(reg, cd->div.shift, cd->div.width,
|
||||
c->div - 1);
|
||||
writel(reg, base + cd->div.offset);
|
||||
}
|
||||
|
||||
/* frequency selector */
|
||||
if (selector_exists(&cd->sel)) {
|
||||
reg = readl(base + cd->sel.offset);
|
||||
bitfield_replace(reg, cd->sel.shift, cd->sel.width,
|
||||
c->sel);
|
||||
writel(reg, base + cd->sel.offset);
|
||||
}
|
||||
|
||||
/* trigger */
|
||||
if (trigger_exists(&cd->trig)) {
|
||||
writel((1 << cd->trig.bit), base + cd->trig.offset);
|
||||
|
||||
/* wait for trigger status bit to go to 0 */
|
||||
ret = wait_bit(base, cd->trig.offset, cd->trig.bit, 0);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* wait for running (status_bit = 1) */
|
||||
ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
} else {
|
||||
debug("%s disable clock %s\n", __func__, c->name);
|
||||
|
||||
/* clkgate */
|
||||
reg = readl(base + cd->gate.offset);
|
||||
reg &= ~(1 << cd->gate.en_bit);
|
||||
writel(reg, base + cd->gate.offset);
|
||||
|
||||
/* wait for stop (status_bit = 0) */
|
||||
ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0);
|
||||
}
|
||||
|
||||
/* disable access */
|
||||
writel(0, base + WR_ACCESS_OFFSET);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Set the rate of a peripheral clock */
|
||||
static int peri_clk_set_rate(struct clk *c, unsigned long rate)
|
||||
{
|
||||
int ret = 0;
|
||||
int i;
|
||||
unsigned long diff;
|
||||
unsigned long new_rate = 0, div = 1;
|
||||
struct peri_clock *peri_clk = to_peri_clk(c);
|
||||
struct peri_clk_data *cd = peri_clk->data;
|
||||
const char **clock;
|
||||
|
||||
debug("%s: %s\n", __func__, c->name);
|
||||
diff = rate;
|
||||
|
||||
i = 0;
|
||||
for (clock = cd->clocks; *clock; clock++, i++) {
|
||||
struct refclk *ref = refclk_str_to_clk(*clock);
|
||||
if (!ref) {
|
||||
printf("%s: Lookup of %s failed\n", __func__, *clock);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* round to the new rate */
|
||||
div = ref->clk.rate / rate;
|
||||
if (div == 0)
|
||||
div = 1;
|
||||
|
||||
new_rate = ref->clk.rate / div;
|
||||
|
||||
/* get the min diff */
|
||||
if (abs(new_rate - rate) < diff) {
|
||||
diff = abs(new_rate - rate);
|
||||
c->sel = i;
|
||||
c->parent = &ref->clk;
|
||||
c->rate = new_rate;
|
||||
c->div = div;
|
||||
}
|
||||
}
|
||||
|
||||
debug("%s %s set rate %lu div %lu sel %d parent %lu\n", __func__,
|
||||
c->name, c->rate, c->div, c->sel, c->parent->rate);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Get the rate of a peripheral clock */
|
||||
static unsigned long peri_clk_get_rate(struct clk *c)
|
||||
{
|
||||
struct peri_clock *peri_clk = to_peri_clk(c);
|
||||
struct peri_clk_data *cd = peri_clk->data;
|
||||
void *base = (void *)c->ccu_clk_mgr_base;
|
||||
int div = 1;
|
||||
const char **clock;
|
||||
struct refclk *ref;
|
||||
u32 reg;
|
||||
|
||||
debug("%s: %s\n", __func__, c->name);
|
||||
if (selector_exists(&cd->sel)) {
|
||||
reg = readl(base + cd->sel.offset);
|
||||
c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width);
|
||||
} else {
|
||||
/*
|
||||
* For peri clocks that don't have a selector, the single
|
||||
* reference clock will always exist at index 0.
|
||||
*/
|
||||
c->sel = 0;
|
||||
}
|
||||
|
||||
if (divider_exists(&cd->div)) {
|
||||
reg = readl(base + cd->div.offset);
|
||||
div = bitfield_extract(reg, cd->div.shift, cd->div.width);
|
||||
div += 1;
|
||||
}
|
||||
|
||||
clock = cd->clocks;
|
||||
ref = refclk_str_to_clk(clock[c->sel]);
|
||||
if (!ref) {
|
||||
printf("%s: Can't lookup %s\n", __func__, clock[c->sel]);
|
||||
return 0;
|
||||
}
|
||||
|
||||
c->parent = &ref->clk;
|
||||
c->div = div;
|
||||
c->rate = c->parent->rate / c->div;
|
||||
debug("%s parent rate %lu div %d sel %d rate %lu\n", __func__,
|
||||
c->parent->rate, div, c->sel, c->rate);
|
||||
|
||||
return c->rate;
|
||||
}
|
||||
|
||||
/* Peripheral clock operations */
|
||||
struct clk_ops peri_clk_ops = {
|
||||
.enable = peri_clk_enable,
|
||||
.set_rate = peri_clk_set_rate,
|
||||
.get_rate = peri_clk_get_rate,
|
||||
};
|
||||
|
||||
/* Enable a CCU clock */
|
||||
static int ccu_clk_enable(struct clk *c, int enable)
|
||||
{
|
||||
struct ccu_clock *ccu_clk = to_ccu_clk(c);
|
||||
void *base = (void *)c->ccu_clk_mgr_base;
|
||||
int ret = 0;
|
||||
u32 reg;
|
||||
|
||||
debug("%s: %s\n", __func__, c->name);
|
||||
if (!enable)
|
||||
return -EINVAL; /* CCU clock cannot shutdown */
|
||||
|
||||
/* enable access */
|
||||
writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
|
||||
|
||||
/* config enable for policy engine */
|
||||
writel(1, base + ccu_clk->lvm_en_offset);
|
||||
|
||||
/* wait for bit to go to 0 */
|
||||
ret = wait_bit(base, ccu_clk->lvm_en_offset, 0, 0);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* freq ID */
|
||||
if (!ccu_clk->freq_bit_shift)
|
||||
ccu_clk->freq_bit_shift = 8;
|
||||
|
||||
/* Set frequency id for each of the 4 policies */
|
||||
reg = ccu_clk->freq_id |
|
||||
(ccu_clk->freq_id << (ccu_clk->freq_bit_shift)) |
|
||||
(ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 2)) |
|
||||
(ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 3));
|
||||
writel(reg, base + ccu_clk->policy_freq_offset);
|
||||
|
||||
/* enable all clock mask */
|
||||
writel(0x7fffffff, base + ccu_clk->policy0_mask_offset);
|
||||
writel(0x7fffffff, base + ccu_clk->policy1_mask_offset);
|
||||
writel(0x7fffffff, base + ccu_clk->policy2_mask_offset);
|
||||
writel(0x7fffffff, base + ccu_clk->policy3_mask_offset);
|
||||
|
||||
if (ccu_clk->num_policy_masks == 2) {
|
||||
writel(0x7fffffff, base + ccu_clk->policy0_mask2_offset);
|
||||
writel(0x7fffffff, base + ccu_clk->policy1_mask2_offset);
|
||||
writel(0x7fffffff, base + ccu_clk->policy2_mask2_offset);
|
||||
writel(0x7fffffff, base + ccu_clk->policy3_mask2_offset);
|
||||
}
|
||||
|
||||
/* start policy engine */
|
||||
reg = readl(base + ccu_clk->policy_ctl_offset);
|
||||
reg |= (POLICY_CTL_GO + POLICY_CTL_GO_ATL);
|
||||
writel(reg, base + ccu_clk->policy_ctl_offset);
|
||||
|
||||
/* wait till started */
|
||||
ret = wait_bit(base, ccu_clk->policy_ctl_offset, 0, 0);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* disable access */
|
||||
writel(0, base + WR_ACCESS_OFFSET);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Get the CCU clock rate */
|
||||
static unsigned long ccu_clk_get_rate(struct clk *c)
|
||||
{
|
||||
struct ccu_clock *ccu_clk = to_ccu_clk(c);
|
||||
debug("%s: %s\n", __func__, c->name);
|
||||
c->rate = ccu_clk->freq_tbl[ccu_clk->freq_id];
|
||||
return c->rate;
|
||||
}
|
||||
|
||||
/* CCU clock operations */
|
||||
struct clk_ops ccu_clk_ops = {
|
||||
.enable = ccu_clk_enable,
|
||||
.get_rate = ccu_clk_get_rate,
|
||||
};
|
||||
|
||||
/* Enable a bus clock */
|
||||
static int bus_clk_enable(struct clk *c, int enable)
|
||||
{
|
||||
struct bus_clock *bus_clk = to_bus_clk(c);
|
||||
struct bus_clk_data *cd = bus_clk->data;
|
||||
void *base = (void *)c->ccu_clk_mgr_base;
|
||||
int ret = 0;
|
||||
u32 reg;
|
||||
|
||||
debug("%s: %s\n", __func__, c->name);
|
||||
/* enable access */
|
||||
writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
|
||||
|
||||
/* enable gating */
|
||||
reg = readl(base + cd->gate.offset);
|
||||
if (!!(reg & (1 << cd->gate.status_bit)) == !!enable)
|
||||
debug("%s already %s\n", c->name,
|
||||
enable ? "enabled" : "disabled");
|
||||
else {
|
||||
int want = (enable) ? 1 : 0;
|
||||
reg |= (1 << cd->gate.hw_sw_sel_bit);
|
||||
|
||||
if (enable)
|
||||
reg |= (1 << cd->gate.en_bit);
|
||||
else
|
||||
reg &= ~(1 << cd->gate.en_bit);
|
||||
|
||||
writel(reg, base + cd->gate.offset);
|
||||
ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit,
|
||||
want);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* disable access */
|
||||
writel(0, base + WR_ACCESS_OFFSET);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Get the rate of a bus clock */
|
||||
static unsigned long bus_clk_get_rate(struct clk *c)
|
||||
{
|
||||
struct bus_clock *bus_clk = to_bus_clk(c);
|
||||
struct ccu_clock *ccu_clk;
|
||||
|
||||
debug("%s: %s\n", __func__, c->name);
|
||||
ccu_clk = to_ccu_clk(c->parent);
|
||||
|
||||
c->rate = bus_clk->freq_tbl[ccu_clk->freq_id];
|
||||
c->div = ccu_clk->freq_tbl[ccu_clk->freq_id] / c->rate;
|
||||
return c->rate;
|
||||
}
|
||||
|
||||
/* Bus clock operations */
|
||||
struct clk_ops bus_clk_ops = {
|
||||
.enable = bus_clk_enable,
|
||||
.get_rate = bus_clk_get_rate,
|
||||
};
|
||||
|
||||
/* Enable a reference clock */
|
||||
static int ref_clk_enable(struct clk *c, int enable)
|
||||
{
|
||||
debug("%s: %s\n", __func__, c->name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Reference clock operations */
|
||||
struct clk_ops ref_clk_ops = {
|
||||
.enable = ref_clk_enable,
|
||||
};
|
||||
|
||||
/*
|
||||
* clk.h implementation follows
|
||||
*/
|
||||
|
||||
/* Initialize the clock framework */
|
||||
int clk_init(void)
|
||||
{
|
||||
debug("%s:\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Get a clock handle, give a name string */
|
||||
struct clk *clk_get(const char *con_id)
|
||||
{
|
||||
int i;
|
||||
struct clk_lookup *clk_tblp;
|
||||
|
||||
debug("%s: %s\n", __func__, con_id);
|
||||
|
||||
clk_tblp = arch_clk_tbl;
|
||||
for (i = 0; i < arch_clk_tbl_array_size; i++, clk_tblp++) {
|
||||
if (clk_tblp->con_id) {
|
||||
if (!con_id || strcmp(clk_tblp->con_id, con_id))
|
||||
continue;
|
||||
return clk_tblp->clk;
|
||||
}
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Enable a clock */
|
||||
int clk_enable(struct clk *c)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
debug("%s: %s\n", __func__, c->name);
|
||||
if (!c->ops || !c->ops->enable)
|
||||
return -1;
|
||||
|
||||
/* enable parent clock first */
|
||||
if (c->parent)
|
||||
ret = clk_enable(c->parent);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (!c->use_cnt)
|
||||
ret = c->ops->enable(c, 1);
|
||||
c->use_cnt++;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Disable a clock */
|
||||
void clk_disable(struct clk *c)
|
||||
{
|
||||
debug("%s: %s\n", __func__, c->name);
|
||||
if (!c->ops || !c->ops->enable)
|
||||
return;
|
||||
|
||||
if (c->use_cnt > 0) {
|
||||
c->use_cnt--;
|
||||
if (c->use_cnt == 0)
|
||||
c->ops->enable(c, 0);
|
||||
}
|
||||
|
||||
/* disable parent */
|
||||
if (c->parent)
|
||||
clk_disable(c->parent);
|
||||
}
|
||||
|
||||
/* Get the clock rate */
|
||||
unsigned long clk_get_rate(struct clk *c)
|
||||
{
|
||||
unsigned long rate;
|
||||
|
||||
if (!c || !c->ops || !c->ops->get_rate)
|
||||
return 0;
|
||||
debug("%s: %s\n", __func__, c->name);
|
||||
|
||||
rate = c->ops->get_rate(c);
|
||||
debug("%s: rate = %ld\n", __func__, rate);
|
||||
return rate;
|
||||
}
|
||||
|
||||
/* Set the clock rate */
|
||||
int clk_set_rate(struct clk *c, unsigned long rate)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (!c || !c->ops || !c->ops->set_rate)
|
||||
return -EINVAL;
|
||||
debug("%s: %s rate=%ld\n", __func__, c->name, rate);
|
||||
|
||||
if (c->use_cnt)
|
||||
return -EINVAL;
|
||||
|
||||
ret = c->ops->set_rate(c, rate);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Not required for this arch */
|
||||
/*
|
||||
long clk_round_rate(struct clk *clk, unsigned long rate);
|
||||
int clk_set_parent(struct clk *clk, struct clk *parent);
|
||||
struct clk *clk_get_parent(struct clk *clk);
|
||||
*/
|
||||
@ -1,491 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2013 Broadcom Corporation.
|
||||
*/
|
||||
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/stringify.h>
|
||||
|
||||
#ifdef CONFIG_CLK_DEBUG
|
||||
#undef writel
|
||||
#undef readl
|
||||
static inline void writel(u32 val, void *addr)
|
||||
{
|
||||
printf("Write [0x%p] = 0x%08x\n", addr, val);
|
||||
*(u32 *)addr = val;
|
||||
}
|
||||
|
||||
static inline u32 readl(void *addr)
|
||||
{
|
||||
u32 val = *(u32 *)addr;
|
||||
printf("Read [0x%p] = 0x%08x\n", addr, val);
|
||||
return val;
|
||||
}
|
||||
#endif
|
||||
|
||||
struct clk;
|
||||
|
||||
struct clk_lookup {
|
||||
const char *dev_id;
|
||||
const char *con_id;
|
||||
struct clk *clk;
|
||||
};
|
||||
|
||||
extern struct clk_lookup arch_clk_tbl[];
|
||||
extern unsigned int arch_clk_tbl_array_size;
|
||||
|
||||
/**
|
||||
* struct clk_ops - standard clock operations
|
||||
* @enable: enable/disable clock, see clk_enable() and clk_disable()
|
||||
* @set_rate: set the clock rate, see clk_set_rate().
|
||||
* @get_rate: get the clock rate, see clk_get_rate().
|
||||
* @round_rate: round a given clock rate, see clk_round_rate().
|
||||
* @set_parent: set the clock's parent, see clk_set_parent().
|
||||
*
|
||||
* Group the common clock implementations together so that we
|
||||
* don't have to keep setting the same fiels again. We leave
|
||||
* enable in struct clk.
|
||||
*
|
||||
*/
|
||||
struct clk_ops {
|
||||
int (*enable)(struct clk *c, int enable);
|
||||
int (*set_rate)(struct clk *c, unsigned long rate);
|
||||
unsigned long (*get_rate)(struct clk *c);
|
||||
unsigned long (*round_rate)(struct clk *c, unsigned long rate);
|
||||
int (*set_parent)(struct clk *c, struct clk *parent);
|
||||
};
|
||||
|
||||
struct clk {
|
||||
struct clk *parent;
|
||||
const char *name;
|
||||
int use_cnt;
|
||||
unsigned long rate; /* in HZ */
|
||||
|
||||
/* programmable divider. 0 means fixed ratio to parent clock */
|
||||
unsigned long div;
|
||||
|
||||
struct clk_src *src;
|
||||
struct clk_ops *ops;
|
||||
|
||||
unsigned long ccu_clk_mgr_base;
|
||||
int sel;
|
||||
};
|
||||
|
||||
struct refclk *refclk_str_to_clk(const char *name);
|
||||
|
||||
/* The common clock framework uses u8 to represent a parent index */
|
||||
#define PARENT_COUNT_MAX ((u32)U8_MAX)
|
||||
|
||||
#define BAD_CLK_INDEX U8_MAX /* Can't ever be valid */
|
||||
#define BAD_CLK_NAME ((const char *)-1)
|
||||
|
||||
#define BAD_SCALED_DIV_VALUE U64_MAX
|
||||
|
||||
/*
|
||||
* Utility macros for object flag management. If possible, flags
|
||||
* should be defined such that 0 is the desired default value.
|
||||
*/
|
||||
#define FLAG(type, flag) BCM_CLK_ ## type ## _FLAGS_ ## flag
|
||||
#define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
|
||||
#define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
|
||||
#define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
|
||||
#define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
|
||||
|
||||
/* Clock field state tests */
|
||||
|
||||
#define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS)
|
||||
#define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED)
|
||||
#define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW)
|
||||
#define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW)
|
||||
#define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED)
|
||||
#define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE)
|
||||
|
||||
#define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED)
|
||||
|
||||
#define divider_exists(div) FLAG_TEST(div, DIV, EXISTS)
|
||||
#define divider_is_fixed(div) FLAG_TEST(div, DIV, FIXED)
|
||||
#define divider_has_fraction(div) (!divider_is_fixed(div) && \
|
||||
(div)->frac_width > 0)
|
||||
|
||||
#define selector_exists(sel) ((sel)->width != 0)
|
||||
#define trigger_exists(trig) FLAG_TEST(trig, TRIG, EXISTS)
|
||||
|
||||
/* Clock type, used to tell common block what it's part of */
|
||||
enum bcm_clk_type {
|
||||
bcm_clk_none, /* undefined clock type */
|
||||
bcm_clk_bus,
|
||||
bcm_clk_core,
|
||||
bcm_clk_peri
|
||||
};
|
||||
|
||||
/*
|
||||
* Gating control and status is managed by a 32-bit gate register.
|
||||
*
|
||||
* There are several types of gating available:
|
||||
* - (no gate)
|
||||
* A clock with no gate is assumed to be always enabled.
|
||||
* - hardware-only gating (auto-gating)
|
||||
* Enabling or disabling clocks with this type of gate is
|
||||
* managed automatically by the hardware. Such clocks can be
|
||||
* considered by the software to be enabled. The current status
|
||||
* of auto-gated clocks can be read from the gate status bit.
|
||||
* - software-only gating
|
||||
* Auto-gating is not available for this type of clock.
|
||||
* Instead, software manages whether it's enabled by setting or
|
||||
* clearing the enable bit. The current gate status of a gate
|
||||
* under software control can be read from the gate status bit.
|
||||
* To ensure a change to the gating status is complete, the
|
||||
* status bit can be polled to verify that the gate has entered
|
||||
* the desired state.
|
||||
* - selectable hardware or software gating
|
||||
* Gating for this type of clock can be configured to be either
|
||||
* under software or hardware control. Which type is in use is
|
||||
* determined by the hw_sw_sel bit of the gate register.
|
||||
*/
|
||||
struct bcm_clk_gate {
|
||||
u32 offset; /* gate register offset */
|
||||
u32 status_bit; /* 0: gate is disabled; 0: gatge is enabled */
|
||||
u32 en_bit; /* 0: disable; 1: enable */
|
||||
u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */
|
||||
u32 flags; /* BCM_CLK_GATE_FLAGS_* below */
|
||||
};
|
||||
|
||||
/*
|
||||
* Gate flags:
|
||||
* HW means this gate can be auto-gated
|
||||
* SW means the state of this gate can be software controlled
|
||||
* NO_DISABLE means this gate is (only) enabled if under software control
|
||||
* SW_MANAGED means the status of this gate is under software control
|
||||
* ENABLED means this software-managed gate is *supposed* to be enabled
|
||||
*/
|
||||
#define BCM_CLK_GATE_FLAGS_EXISTS ((u32)1 << 0) /* Gate is valid */
|
||||
#define BCM_CLK_GATE_FLAGS_HW ((u32)1 << 1) /* Can auto-gate */
|
||||
#define BCM_CLK_GATE_FLAGS_SW ((u32)1 << 2) /* Software control */
|
||||
#define BCM_CLK_GATE_FLAGS_NO_DISABLE ((u32)1 << 3) /* HW or enabled */
|
||||
#define BCM_CLK_GATE_FLAGS_SW_MANAGED ((u32)1 << 4) /* SW now in control */
|
||||
#define BCM_CLK_GATE_FLAGS_ENABLED ((u32)1 << 5) /* If SW_MANAGED */
|
||||
|
||||
/*
|
||||
* Gate initialization macros.
|
||||
*
|
||||
* Any gate initially under software control will be enabled.
|
||||
*/
|
||||
|
||||
/* A hardware/software gate initially under software control */
|
||||
#define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
|
||||
{ \
|
||||
.offset = (_offset), \
|
||||
.status_bit = (_status_bit), \
|
||||
.en_bit = (_en_bit), \
|
||||
.hw_sw_sel_bit = (_hw_sw_sel_bit), \
|
||||
.flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
|
||||
FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)| \
|
||||
FLAG(GATE, EXISTS), \
|
||||
}
|
||||
|
||||
/* A hardware/software gate initially under hardware control */
|
||||
#define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
|
||||
{ \
|
||||
.offset = (_offset), \
|
||||
.status_bit = (_status_bit), \
|
||||
.en_bit = (_en_bit), \
|
||||
.hw_sw_sel_bit = (_hw_sw_sel_bit), \
|
||||
.flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
|
||||
FLAG(GATE, EXISTS), \
|
||||
}
|
||||
|
||||
/* A hardware-or-enabled gate (enabled if not under hardware control) */
|
||||
#define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
|
||||
{ \
|
||||
.offset = (_offset), \
|
||||
.status_bit = (_status_bit), \
|
||||
.en_bit = (_en_bit), \
|
||||
.hw_sw_sel_bit = (_hw_sw_sel_bit), \
|
||||
.flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
|
||||
FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS), \
|
||||
}
|
||||
|
||||
/* A software-only gate */
|
||||
#define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \
|
||||
{ \
|
||||
.offset = (_offset), \
|
||||
.status_bit = (_status_bit), \
|
||||
.en_bit = (_en_bit), \
|
||||
.flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \
|
||||
FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS), \
|
||||
}
|
||||
|
||||
/* A hardware-only gate */
|
||||
#define HW_ONLY_GATE(_offset, _status_bit) \
|
||||
{ \
|
||||
.offset = (_offset), \
|
||||
.status_bit = (_status_bit), \
|
||||
.flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \
|
||||
}
|
||||
|
||||
/*
|
||||
* Each clock can have zero, one, or two dividers which change the
|
||||
* output rate of the clock. Each divider can be either fixed or
|
||||
* variable. If there are two dividers, they are the "pre-divider"
|
||||
* and the "regular" or "downstream" divider. If there is only one,
|
||||
* there is no pre-divider.
|
||||
*
|
||||
* A fixed divider is any non-zero (positive) value, and it
|
||||
* indicates how the input rate is affected by the divider.
|
||||
*
|
||||
* The value of a variable divider is maintained in a sub-field of a
|
||||
* 32-bit divider register. The position of the field in the
|
||||
* register is defined by its offset and width. The value recorded
|
||||
* in this field is always 1 less than the value it represents.
|
||||
*
|
||||
* In addition, a variable divider can indicate that some subset
|
||||
* of its bits represent a "fractional" part of the divider. Such
|
||||
* bits comprise the low-order portion of the divider field, and can
|
||||
* be viewed as representing the portion of the divider that lies to
|
||||
* the right of the decimal point. Most variable dividers have zero
|
||||
* fractional bits. Variable dividers with non-zero fraction width
|
||||
* still record a value 1 less than the value they represent; the
|
||||
* added 1 does *not* affect the low-order bit in this case, it
|
||||
* affects the bits above the fractional part only. (Often in this
|
||||
* code a divider field value is distinguished from the value it
|
||||
* represents by referring to the latter as a "divisor".)
|
||||
*
|
||||
* In order to avoid dealing with fractions, divider arithmetic is
|
||||
* performed using "scaled" values. A scaled value is one that's
|
||||
* been left-shifted by the fractional width of a divider. Dividing
|
||||
* a scaled value by a scaled divisor produces the desired quotient
|
||||
* without loss of precision and without any other special handling
|
||||
* for fractions.
|
||||
*
|
||||
* The recorded value of a variable divider can be modified. To
|
||||
* modify either divider (or both), a clock must be enabled (i.e.,
|
||||
* using its gate). In addition, a trigger register (described
|
||||
* below) must be used to commit the change, and polled to verify
|
||||
* the change is complete.
|
||||
*/
|
||||
struct bcm_clk_div {
|
||||
union {
|
||||
struct { /* variable divider */
|
||||
u32 offset; /* divider register offset */
|
||||
u32 shift; /* field shift */
|
||||
u32 width; /* field width */
|
||||
u32 frac_width; /* field fraction width */
|
||||
|
||||
u64 scaled_div; /* scaled divider value */
|
||||
};
|
||||
u32 fixed; /* non-zero fixed divider value */
|
||||
};
|
||||
u32 flags; /* BCM_CLK_DIV_FLAGS_* below */
|
||||
};
|
||||
|
||||
/*
|
||||
* Divider flags:
|
||||
* EXISTS means this divider exists
|
||||
* FIXED means it is a fixed-rate divider
|
||||
*/
|
||||
#define BCM_CLK_DIV_FLAGS_EXISTS ((u32)1 << 0) /* Divider is valid */
|
||||
#define BCM_CLK_DIV_FLAGS_FIXED ((u32)1 << 1) /* Fixed-value */
|
||||
|
||||
/* Divider initialization macros */
|
||||
|
||||
/* A fixed (non-zero) divider */
|
||||
#define FIXED_DIVIDER(_value) \
|
||||
{ \
|
||||
.fixed = (_value), \
|
||||
.flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED), \
|
||||
}
|
||||
|
||||
/* A divider with an integral divisor */
|
||||
#define DIVIDER(_offset, _shift, _width) \
|
||||
{ \
|
||||
.offset = (_offset), \
|
||||
.shift = (_shift), \
|
||||
.width = (_width), \
|
||||
.scaled_div = BAD_SCALED_DIV_VALUE, \
|
||||
.flags = FLAG(DIV, EXISTS), \
|
||||
}
|
||||
|
||||
/* A divider whose divisor has an integer and fractional part */
|
||||
#define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \
|
||||
{ \
|
||||
.offset = (_offset), \
|
||||
.shift = (_shift), \
|
||||
.width = (_width), \
|
||||
.frac_width = (_frac_width), \
|
||||
.scaled_div = BAD_SCALED_DIV_VALUE, \
|
||||
.flags = FLAG(DIV, EXISTS), \
|
||||
}
|
||||
|
||||
/*
|
||||
* Clocks may have multiple "parent" clocks. If there is more than
|
||||
* one, a selector must be specified to define which of the parent
|
||||
* clocks is currently in use. The selected clock is indicated in a
|
||||
* sub-field of a 32-bit selector register. The range of
|
||||
* representable selector values typically exceeds the number of
|
||||
* available parent clocks. Occasionally the reset value of a
|
||||
* selector field is explicitly set to a (specific) value that does
|
||||
* not correspond to a defined input clock.
|
||||
*
|
||||
* We register all known parent clocks with the common clock code
|
||||
* using a packed array (i.e., no empty slots) of (parent) clock
|
||||
* names, and refer to them later using indexes into that array.
|
||||
* We maintain an array of selector values indexed by common clock
|
||||
* index values in order to map between these common clock indexes
|
||||
* and the selector values used by the hardware.
|
||||
*
|
||||
* Like dividers, a selector can be modified, but to do so a clock
|
||||
* must be enabled, and a trigger must be used to commit the change.
|
||||
*/
|
||||
struct bcm_clk_sel {
|
||||
u32 offset; /* selector register offset */
|
||||
u32 shift; /* field shift */
|
||||
u32 width; /* field width */
|
||||
|
||||
u32 parent_count; /* number of entries in parent_sel[] */
|
||||
u32 *parent_sel; /* array of parent selector values */
|
||||
u8 clk_index; /* current selected index in parent_sel[] */
|
||||
};
|
||||
|
||||
/* Selector initialization macro */
|
||||
#define SELECTOR(_offset, _shift, _width) \
|
||||
{ \
|
||||
.offset = (_offset), \
|
||||
.shift = (_shift), \
|
||||
.width = (_width), \
|
||||
.clk_index = BAD_CLK_INDEX, \
|
||||
}
|
||||
|
||||
/*
|
||||
* Making changes to a variable divider or a selector for a clock
|
||||
* requires the use of a trigger. A trigger is defined by a single
|
||||
* bit within a register. To signal a change, a 1 is written into
|
||||
* that bit. To determine when the change has been completed, that
|
||||
* trigger bit is polled; the read value will be 1 while the change
|
||||
* is in progress, and 0 when it is complete.
|
||||
*
|
||||
* Occasionally a clock will have more than one trigger. In this
|
||||
* case, the "pre-trigger" will be used when changing a clock's
|
||||
* selector and/or its pre-divider.
|
||||
*/
|
||||
struct bcm_clk_trig {
|
||||
u32 offset; /* trigger register offset */
|
||||
u32 bit; /* trigger bit */
|
||||
u32 flags; /* BCM_CLK_TRIG_FLAGS_* below */
|
||||
};
|
||||
|
||||
/*
|
||||
* Trigger flags:
|
||||
* EXISTS means this trigger exists
|
||||
*/
|
||||
#define BCM_CLK_TRIG_FLAGS_EXISTS ((u32)1 << 0) /* Trigger is valid */
|
||||
|
||||
/* Trigger initialization macro */
|
||||
#define TRIGGER(_offset, _bit) \
|
||||
{ \
|
||||
.offset = (_offset), \
|
||||
.bit = (_bit), \
|
||||
.flags = FLAG(TRIG, EXISTS), \
|
||||
}
|
||||
|
||||
struct bus_clk_data {
|
||||
struct bcm_clk_gate gate;
|
||||
};
|
||||
|
||||
struct core_clk_data {
|
||||
struct bcm_clk_gate gate;
|
||||
};
|
||||
|
||||
struct peri_clk_data {
|
||||
struct bcm_clk_gate gate;
|
||||
struct bcm_clk_trig pre_trig;
|
||||
struct bcm_clk_div pre_div;
|
||||
struct bcm_clk_trig trig;
|
||||
struct bcm_clk_div div;
|
||||
struct bcm_clk_sel sel;
|
||||
const char *clocks[]; /* must be last; use CLOCKS() to declare */
|
||||
};
|
||||
#define CLOCKS(...) { __VA_ARGS__, NULL, }
|
||||
#define NO_CLOCKS { NULL, } /* Must use of no parent clocks */
|
||||
|
||||
struct refclk {
|
||||
struct clk clk;
|
||||
};
|
||||
|
||||
struct peri_clock {
|
||||
struct clk clk;
|
||||
struct peri_clk_data *data;
|
||||
};
|
||||
|
||||
struct ccu_clock {
|
||||
struct clk clk;
|
||||
|
||||
int num_policy_masks;
|
||||
unsigned long policy_freq_offset;
|
||||
int freq_bit_shift; /* 8 for most CCUs */
|
||||
unsigned long policy_ctl_offset;
|
||||
unsigned long policy0_mask_offset;
|
||||
unsigned long policy1_mask_offset;
|
||||
unsigned long policy2_mask_offset;
|
||||
unsigned long policy3_mask_offset;
|
||||
unsigned long policy0_mask2_offset;
|
||||
unsigned long policy1_mask2_offset;
|
||||
unsigned long policy2_mask2_offset;
|
||||
unsigned long policy3_mask2_offset;
|
||||
unsigned long lvm_en_offset;
|
||||
|
||||
int freq_id;
|
||||
unsigned long *freq_tbl;
|
||||
};
|
||||
|
||||
struct bus_clock {
|
||||
struct clk clk;
|
||||
struct bus_clk_data *data;
|
||||
unsigned long *freq_tbl;
|
||||
};
|
||||
|
||||
struct ref_clock {
|
||||
struct clk clk;
|
||||
};
|
||||
|
||||
static inline int is_same_clock(struct clk *a, struct clk *b)
|
||||
{
|
||||
return a == b;
|
||||
}
|
||||
|
||||
#define to_clk(p) (&((p)->clk))
|
||||
#define name_to_clk(name) (&((name##_clk).clk))
|
||||
/* declare a struct clk_lookup */
|
||||
#define CLK_LK(name) \
|
||||
{.con_id = __stringify(name##_clk), .clk = name_to_clk(name),}
|
||||
|
||||
static inline struct refclk *to_refclk(struct clk *clock)
|
||||
{
|
||||
return container_of(clock, struct refclk, clk);
|
||||
}
|
||||
|
||||
static inline struct peri_clock *to_peri_clk(struct clk *clock)
|
||||
{
|
||||
return container_of(clock, struct peri_clock, clk);
|
||||
}
|
||||
|
||||
static inline struct ccu_clock *to_ccu_clk(struct clk *clock)
|
||||
{
|
||||
return container_of(clock, struct ccu_clock, clk);
|
||||
}
|
||||
|
||||
static inline struct bus_clock *to_bus_clk(struct clk *clock)
|
||||
{
|
||||
return container_of(clock, struct bus_clock, clk);
|
||||
}
|
||||
|
||||
static inline struct ref_clock *to_ref_clk(struct clk *clock)
|
||||
{
|
||||
return container_of(clock, struct ref_clock, clk);
|
||||
}
|
||||
|
||||
extern struct clk_ops peri_clk_ops;
|
||||
extern struct clk_ops ccu_clk_ops;
|
||||
extern struct clk_ops bus_clk_ops;
|
||||
extern struct clk_ops ref_clk_ops;
|
||||
|
||||
int clk_get_and_enable(char *clkstr);
|
||||
@ -1,142 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2014 Broadcom Corporation.
|
||||
*/
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/errno.h>
|
||||
#include <asm/arch/sysmap.h>
|
||||
#include <asm/kona-common/clk.h>
|
||||
#include "clk-core.h"
|
||||
|
||||
#define WR_ACCESS_ADDR ESUB_CLK_BASE_ADDR
|
||||
#define WR_ACCESS_PASSWORD 0xA5A500
|
||||
|
||||
#define PLLE_POST_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C00)
|
||||
|
||||
#define PLLE_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C58)
|
||||
#define PLLE_RESETB_I_PLL_RESETB_PLLE_MASK 0x00010000
|
||||
#define PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK 0x00000001
|
||||
|
||||
#define PLL_LOCK_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C38)
|
||||
#define PLL_LOCK_PLL_LOCK_PLLE_MASK 0x00000001
|
||||
|
||||
#define ESW_SYS_DIV_ADDR (ESUB_CLK_BASE_ADDR + 0x00000A04)
|
||||
#define ESW_SYS_DIV_PLL_SELECT_MASK 0x00000300
|
||||
#define ESW_SYS_DIV_DIV_MASK 0x0000001C
|
||||
#define ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT 0x00000100
|
||||
#define ESW_SYS_DIV_DIV_SELECT 0x4
|
||||
#define ESW_SYS_DIV_TRIGGER_MASK 0x00000001
|
||||
|
||||
#define ESUB_AXI_DIV_DEBUG_ADDR (ESUB_CLK_BASE_ADDR + 0x00000E04)
|
||||
#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK 0x0000001C
|
||||
#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK 0x00000040
|
||||
#define ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT 0x0
|
||||
#define ESUB_AXI_DIV_DEBUG_TRIGGER_MASK 0x00000001
|
||||
|
||||
#define PLL_MAX_RETRY 100
|
||||
|
||||
/* Enable appropriate clocks for Ethernet */
|
||||
int clk_eth_enable(void)
|
||||
{
|
||||
int rc = -1;
|
||||
int retry_count = 0;
|
||||
rc = clk_get_and_enable("esub_ccu_clk");
|
||||
|
||||
/* Enable Access to CCU registers */
|
||||
writel((1 | WR_ACCESS_PASSWORD), WR_ACCESS_ADDR);
|
||||
|
||||
writel(readl(PLLE_POST_RESETB_ADDR) &
|
||||
~PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
|
||||
PLLE_POST_RESETB_ADDR);
|
||||
|
||||
/* Take PLL out of reset and put into normal mode */
|
||||
writel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK,
|
||||
PLLE_RESETB_ADDR);
|
||||
|
||||
/* Wait for PLL lock */
|
||||
rc = -1;
|
||||
while (retry_count < PLL_MAX_RETRY) {
|
||||
udelay(100);
|
||||
if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) {
|
||||
rc = 0;
|
||||
break;
|
||||
}
|
||||
retry_count++;
|
||||
}
|
||||
|
||||
if (rc == -1) {
|
||||
printf("%s: ETH-PLL lock timeout, Ethernet is not enabled!\n",
|
||||
__func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
writel(readl(PLLE_POST_RESETB_ADDR) |
|
||||
PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
|
||||
PLLE_POST_RESETB_ADDR);
|
||||
|
||||
/* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */
|
||||
writel((readl(ESW_SYS_DIV_ADDR) &
|
||||
~(ESW_SYS_DIV_PLL_SELECT_MASK | ESW_SYS_DIV_DIV_MASK)) |
|
||||
ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT | ESW_SYS_DIV_DIV_SELECT,
|
||||
ESW_SYS_DIV_ADDR);
|
||||
|
||||
writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK,
|
||||
ESW_SYS_DIV_ADDR);
|
||||
|
||||
/* Wait for trigger complete */
|
||||
rc = -1;
|
||||
retry_count = 0;
|
||||
while (retry_count < PLL_MAX_RETRY) {
|
||||
udelay(100);
|
||||
if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) {
|
||||
rc = 0;
|
||||
break;
|
||||
}
|
||||
retry_count++;
|
||||
}
|
||||
|
||||
if (rc == -1) {
|
||||
printf("%s: SYS CLK Trigger timeout, Ethernet is not enabled!\n",
|
||||
__func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* switch Esub AXI clock to 208MHz */
|
||||
writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) &
|
||||
~(ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK |
|
||||
ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK |
|
||||
ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) |
|
||||
ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT |
|
||||
ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK,
|
||||
ESUB_AXI_DIV_DEBUG_ADDR);
|
||||
|
||||
writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) |
|
||||
ESUB_AXI_DIV_DEBUG_TRIGGER_MASK,
|
||||
ESUB_AXI_DIV_DEBUG_ADDR);
|
||||
|
||||
/* Wait for trigger complete */
|
||||
rc = -1;
|
||||
retry_count = 0;
|
||||
while (retry_count < PLL_MAX_RETRY) {
|
||||
udelay(100);
|
||||
if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) &
|
||||
ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) {
|
||||
rc = 0;
|
||||
break;
|
||||
}
|
||||
retry_count++;
|
||||
}
|
||||
|
||||
if (rc == -1) {
|
||||
printf("%s: AXI CLK Trigger timeout, Ethernet is not enabled!\n",
|
||||
__func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Disable Access to CCU registers */
|
||||
writel(WR_ACCESS_PASSWORD, WR_ACCESS_ADDR);
|
||||
|
||||
return rc;
|
||||
}
|
||||
@ -1,71 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2013 Broadcom Corporation.
|
||||
*/
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <linux/errno.h>
|
||||
#include <asm/arch/sysmap.h>
|
||||
#include <asm/kona-common/clk.h>
|
||||
#include "clk-core.h"
|
||||
|
||||
/* Enable appropriate clocks for an SDIO port */
|
||||
int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep)
|
||||
{
|
||||
int ret;
|
||||
struct clk *c;
|
||||
|
||||
char *clkstr;
|
||||
char *slpstr;
|
||||
char *ahbstr;
|
||||
|
||||
switch ((u32) base) {
|
||||
case CONFIG_SYS_SDIO_BASE0:
|
||||
clkstr = CONFIG_SYS_SDIO0 "_clk";
|
||||
ahbstr = CONFIG_SYS_SDIO0 "_ahb_clk";
|
||||
slpstr = CONFIG_SYS_SDIO0 "_sleep_clk";
|
||||
break;
|
||||
case CONFIG_SYS_SDIO_BASE1:
|
||||
clkstr = CONFIG_SYS_SDIO1 "_clk";
|
||||
ahbstr = CONFIG_SYS_SDIO1 "_ahb_clk";
|
||||
slpstr = CONFIG_SYS_SDIO1 "_sleep_clk";
|
||||
break;
|
||||
case CONFIG_SYS_SDIO_BASE2:
|
||||
clkstr = CONFIG_SYS_SDIO2 "_clk";
|
||||
ahbstr = CONFIG_SYS_SDIO2 "_ahb_clk";
|
||||
slpstr = CONFIG_SYS_SDIO2 "_sleep_clk";
|
||||
break;
|
||||
case CONFIG_SYS_SDIO_BASE3:
|
||||
clkstr = CONFIG_SYS_SDIO3 "_clk";
|
||||
ahbstr = CONFIG_SYS_SDIO3 "_ahb_clk";
|
||||
slpstr = CONFIG_SYS_SDIO3 "_sleep_clk";
|
||||
break;
|
||||
default:
|
||||
printf("%s: base 0x%p not found\n", __func__, base);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = clk_get_and_enable(ahbstr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_get_and_enable(slpstr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
c = clk_get(clkstr);
|
||||
if (c) {
|
||||
ret = clk_set_rate(c, rate);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_enable(c);
|
||||
if (ret)
|
||||
return ret;
|
||||
} else {
|
||||
printf("%s: Couldn't find %s\n", __func__, clkstr);
|
||||
return -EINVAL;
|
||||
}
|
||||
*actual_ratep = rate;
|
||||
return 0;
|
||||
}
|
||||
@ -1,25 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2014 Broadcom Corporation.
|
||||
*/
|
||||
|
||||
#include <linux/errno.h>
|
||||
#include <asm/arch/sysmap.h>
|
||||
#include "clk-core.h"
|
||||
|
||||
/* Enable appropriate clocks for the USB OTG port */
|
||||
int clk_usb_otg_enable(void *base)
|
||||
{
|
||||
char *ahbstr;
|
||||
|
||||
switch ((u32) base) {
|
||||
case HSOTG_BASE_ADDR:
|
||||
ahbstr = "usb_otg_ahb_clk";
|
||||
break;
|
||||
default:
|
||||
printf("%s: base 0x%p not found\n", __func__, base);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return clk_get_and_enable(ahbstr);
|
||||
}
|
||||
@ -1134,11 +1134,6 @@ int icache_status(void)
|
||||
return (get_sctlr() & CR_I) != 0;
|
||||
}
|
||||
|
||||
int mmu_status(void)
|
||||
{
|
||||
return (get_sctlr() & CR_M) != 0;
|
||||
}
|
||||
|
||||
void invalidate_icache_all(void)
|
||||
{
|
||||
__asm_invalidate_icache_all();
|
||||
@ -1160,17 +1155,17 @@ int icache_status(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mmu_status(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void invalidate_icache_all(void)
|
||||
{
|
||||
}
|
||||
|
||||
#endif /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
|
||||
|
||||
int mmu_status(void)
|
||||
{
|
||||
return (get_sctlr() & CR_M) != 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable dCache & iCache, whether cache is actually enabled
|
||||
* depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF
|
||||
|
||||
@ -835,9 +835,7 @@ dtb-$(CONFIG_MX6UL) += \
|
||||
imx6ul-liteboard.dtb \
|
||||
imx6ul-phytec-segin-ff-rdk-nand.dtb \
|
||||
imx6ul-pico-hobbit.dtb \
|
||||
imx6ul-pico-pi.dtb \
|
||||
imx6ul-kontron-bl.dtb \
|
||||
imx6ull-kontron-bl.dtb
|
||||
imx6ul-pico-pi.dtb
|
||||
|
||||
dtb-$(CONFIG_MX6ULL) += \
|
||||
imx6ull-14x14-evk.dtb \
|
||||
|
||||
@ -102,9 +102,9 @@
|
||||
status = "okay";
|
||||
|
||||
max8997-pmic@66 {
|
||||
compatible = "maxim,max8997";
|
||||
compatible = "maxim,max8997-pmic";
|
||||
reg = <0x66 0 0>;
|
||||
voltage-regulators {
|
||||
regulators {
|
||||
valive_reg: LDO2 {
|
||||
regulator-name = "VALIVE_1.1V_C210";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
|
||||
@ -77,7 +77,7 @@
|
||||
max8998-pmic@66 {
|
||||
compatible = "maxim,max8998";
|
||||
reg = <0x66 0 0>;
|
||||
voltage-regulators {
|
||||
regulators {
|
||||
ldo2_reg: LDO2 {
|
||||
regulator-name = "VALIVE_1.2V";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
|
||||
@ -40,7 +40,7 @@
|
||||
s2mps11_pmic@66 {
|
||||
compatible = "samsung,s2mps11-pmic";
|
||||
reg = <0x66>;
|
||||
voltage-regulators {
|
||||
regulators {
|
||||
ldo1_reg: LDO1 {
|
||||
regulator-name = "vdd_ldo1";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
|
||||
@ -1,103 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2017 exceet electronics GmbH
|
||||
* Copyright (C) 2018 Kontron Electronics GmbH
|
||||
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
|
||||
*/
|
||||
|
||||
#include "imx6ul-kontron-bl.dts"
|
||||
|
||||
/ {
|
||||
model = "Kontron BL i.MX6UL 43 (N631X S 43)";
|
||||
compatible = "kontron,bl-imx6ul-43", "kontron,bl-imx6ul",
|
||||
"kontron,sl-imx6ul", "fsl,imx6ul";
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm7 0 5000000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
default-brightness-level = <6>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
touchscreen@5d {
|
||||
compatible = "goodix,gt928";
|
||||
reg = <0x5d>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_cap_touch>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
|
||||
irq-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&lcdif {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
|
||||
/* Leave status disabled because of missing display panel node */
|
||||
};
|
||||
|
||||
&pwm7 {
|
||||
#pwm-cells = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm7>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_cap_touch: captouchgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* Touch Interrupt */
|
||||
MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 /* Touch Reset */
|
||||
MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Touch Wake */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lcdif_ctrl: lcdifctrlgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
|
||||
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
|
||||
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
|
||||
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
|
||||
MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lcdif_dat: lcdifdatgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
|
||||
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
|
||||
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
|
||||
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
|
||||
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
|
||||
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
|
||||
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
|
||||
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
|
||||
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
|
||||
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
|
||||
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
|
||||
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
|
||||
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
|
||||
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
|
||||
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
|
||||
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
|
||||
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
|
||||
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
|
||||
MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
|
||||
MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
|
||||
MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
|
||||
MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
|
||||
MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
|
||||
MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm7: pwm7grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x110b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
@ -30,9 +30,6 @@
|
||||
* in Linux we can't assign the shared reset GPIO to the PHYs, as this
|
||||
* would cause Linux to reset both PHYs every time one of them gets
|
||||
* reinitialized.
|
||||
*
|
||||
* Also we disable the second ethernet as it currently doesn't work with
|
||||
* the devicetree setup in U-Boot.
|
||||
*/
|
||||
|
||||
&fec1 {
|
||||
@ -53,11 +50,16 @@
|
||||
clocks = <&clks IMX6UL_CLK_ENET_REF>;
|
||||
clock-names = "rmii-ref";
|
||||
};
|
||||
|
||||
ethphy2: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
micrel,led-mode = <0>;
|
||||
clocks = <&clks IMX6UL_CLK_ENET2_REF>;
|
||||
clock-names = "rmii-ref";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec2 {
|
||||
status = "disabled";
|
||||
/delete-property/ phy-handle;
|
||||
/delete-node/ mdio;
|
||||
};
|
||||
|
||||
@ -1,406 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2017 exceet electronics GmbH
|
||||
* Copyright (C) 2018 Kontron Electronics GmbH
|
||||
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_leds>;
|
||||
|
||||
led1 {
|
||||
label = "debug-led1";
|
||||
gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
led2 {
|
||||
label = "debug-led2";
|
||||
gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led3 {
|
||||
label = "debug-led3";
|
||||
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
pwm-beeper {
|
||||
compatible = "pwm-beeper";
|
||||
pwms = <&pwm8 0 5000>;
|
||||
};
|
||||
|
||||
reg_3v3: regulator-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
reg_5v: regulator-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "5v";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_otg1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_vref_adc: regulator-vref-adc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vref-adc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
&adc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_adc1>;
|
||||
num-channels = <3>;
|
||||
vref-supply = <®_vref_adc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1>;
|
||||
status = "okay";
|
||||
|
||||
eeprom@0 {
|
||||
compatible = "anvo,anv32e61w", "atmel,at25";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <20000000>;
|
||||
spi-cpha;
|
||||
spi-cpol;
|
||||
pagesize = <1>;
|
||||
size = <8192>;
|
||||
address-width = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-0 = <&pinctrl_enet1>;
|
||||
/delete-node/ mdio;
|
||||
};
|
||||
|
||||
&fec2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <ðphy2>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
micrel,led-mode = <0>;
|
||||
clocks = <&clks IMX6UL_CLK_ENET_REF>;
|
||||
clock-names = "rmii-ref";
|
||||
};
|
||||
|
||||
ethphy2: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
micrel,led-mode = <0>;
|
||||
clocks = <&clks IMX6UL_CLK_ENET2_REF>;
|
||||
clock-names = "rmii-ref";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c4>;
|
||||
status = "okay";
|
||||
|
||||
rtc@32 {
|
||||
compatible = "epson,rx8900";
|
||||
reg = <0x32>;
|
||||
};
|
||||
};
|
||||
|
||||
&pwm8 {
|
||||
#pwm-cells = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
linux,rs485-enabled-at-boot-time;
|
||||
rs485-rx-during-tx;
|
||||
rs485-rts-active-low;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg1>;
|
||||
dr_mode = "otg";
|
||||
srp-disable;
|
||||
hnp-disable;
|
||||
adp-disable;
|
||||
over-current-active-low;
|
||||
vbus-supply = <®_usb_otg1_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg2 {
|
||||
dr_mode = "host";
|
||||
disable-over-current;
|
||||
vbus-supply = <®_5v>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
|
||||
keep-power-in-suspend;
|
||||
wakeup-source;
|
||||
vmmc-supply = <®_3v3>;
|
||||
voltage-ranges = <3300 3300>;
|
||||
no-1-8-v;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
|
||||
non-removable;
|
||||
keep-power-in-suspend;
|
||||
wakeup-source;
|
||||
vmmc-supply = <®_3v3>;
|
||||
voltage-ranges = <3300 3300>;
|
||||
no-1-8-v;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
|
||||
|
||||
pinctrl_adc1: adc1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
|
||||
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
|
||||
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
|
||||
MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
|
||||
MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
|
||||
MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet2: enet2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
|
||||
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
|
||||
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
|
||||
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
|
||||
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
|
||||
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
|
||||
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
|
||||
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet2_mdio: enet2mdiogrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
|
||||
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan2: flexcan2grp{
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
|
||||
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio: gpiogrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
|
||||
MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
|
||||
MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
|
||||
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_leds: gpioledsgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
|
||||
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
|
||||
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
|
||||
MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c4: i2c4grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
|
||||
MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm8: pwm8grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
|
||||
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
|
||||
MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
|
||||
MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
|
||||
/*
|
||||
* mux unused RTS to make sure it doesn't cause
|
||||
* any interrupts when it is undefined
|
||||
*/
|
||||
MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
|
||||
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
|
||||
MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
|
||||
MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart4: uart4grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
|
||||
MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg1: usbotg1 {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
|
||||
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
|
||||
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
|
||||
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
|
||||
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
|
||||
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
|
||||
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
|
||||
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
|
||||
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
|
||||
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
|
||||
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
|
||||
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
|
||||
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
|
||||
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
|
||||
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
|
||||
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
|
||||
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
|
||||
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
|
||||
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
|
||||
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
|
||||
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
|
||||
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
|
||||
>;
|
||||
};
|
||||
};
|
||||
@ -1,16 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2017 exceet electronics GmbH
|
||||
* Copyright (C) 2018 Kontron Electronics GmbH
|
||||
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6ul-kontron-sl.dtsi"
|
||||
#include "imx6ul-kontron-bl-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Kontron BL i.MX6UL (N631X S)";
|
||||
compatible = "kontron,bl-imx6ul", "kontron,sl-imx6ul", "fsl,imx6ul";
|
||||
};
|
||||
@ -1,137 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2017 exceet electronics GmbH
|
||||
* Copyright (C) 2018 Kontron Electronics GmbH
|
||||
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = &uart4;
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
reg = <0x80000000 0x10000000>;
|
||||
device_type = "memory";
|
||||
};
|
||||
};
|
||||
|
||||
&ecspi2 {
|
||||
cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi2>;
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <ðphy1>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
micrel,led-mode = <0>;
|
||||
clocks = <&clks IMX6UL_CLK_ENET_REF>;
|
||||
clock-names = "rmii-ref";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec2 {
|
||||
phy-mode = "rmii";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_qspi>;
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spi-nand";
|
||||
spi-max-frequency = <104000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_reset_out>;
|
||||
|
||||
pinctrl_ecspi2: ecspi2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1
|
||||
MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1
|
||||
MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1
|
||||
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet1: enet1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
|
||||
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
|
||||
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
|
||||
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
|
||||
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
|
||||
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
|
||||
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
|
||||
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet1_mdio: enet1mdiogrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
|
||||
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_qspi: qspigrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
|
||||
MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
|
||||
MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
|
||||
MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
|
||||
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
|
||||
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reset_out: rstoutgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x18b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
@ -1,14 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2017 exceet electronics GmbH
|
||||
* Copyright (C) 2018 Kontron Electronics GmbH
|
||||
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
|
||||
*/
|
||||
|
||||
#include "imx6ul.dtsi"
|
||||
#include "imx6ul-kontron-sl-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Kontron SL i.MX6UL (N631X SOM)";
|
||||
compatible = "kontron,sl-imx6ul", "fsl,imx6ul";
|
||||
};
|
||||
@ -1,15 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2017 exceet electronics GmbH
|
||||
* Copyright (C) 2019 Kontron Electronics GmbH
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6ull-kontron-sl.dtsi"
|
||||
#include "imx6ul-kontron-bl-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Kontron BL i.MX6ULL (N641X S)";
|
||||
compatible = "kontron,bl-imx6ull", "kontron,sl-imx6ull", "fsl,imx6ull";
|
||||
};
|
||||
@ -1,13 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2017 exceet electronics GmbH
|
||||
* Copyright (C) 2018 Kontron Electronics GmbH
|
||||
*/
|
||||
|
||||
#include "imx6ull.dtsi"
|
||||
#include "imx6ul-kontron-sl-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Kontron SL i.MX6ULL (N641X SOM)";
|
||||
compatible = "kontron,sl-imx6ull", "fsl,imx6ull";
|
||||
};
|
||||
@ -344,7 +344,6 @@
|
||||
pinctrl-0 = <&pinctrl_pmic>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
||||
sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
/*
|
||||
* i.MX 8M Plus Data Sheet for Consumer Products
|
||||
|
||||
@ -245,7 +245,6 @@
|
||||
pinctrl-0 = <&pinctrl_pmic>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
||||
sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
/*
|
||||
* i.MX 8M Plus Data Sheet for Consumer Products
|
||||
|
||||
131
arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi
Normal file
131
arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi
Normal file
@ -0,0 +1,131 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
|
||||
*/
|
||||
|
||||
#include "imx8mp-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
wdt-reboot {
|
||||
compatible = "wdt-reboot";
|
||||
wdt = <&wdog1>;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
bootstd {
|
||||
bootph-verify;
|
||||
compatible = "u-boot,boot-std";
|
||||
|
||||
filename-prefixes = "/", "/boot/";
|
||||
bootdev-order = "mmc2", "mmc1", "ethernet";
|
||||
|
||||
efi {
|
||||
compatible = "u-boot,distro-efi";
|
||||
};
|
||||
|
||||
rauc {
|
||||
compatible = "u-boot,distro-rauc";
|
||||
};
|
||||
|
||||
script {
|
||||
compatible = "u-boot,script";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
®_usdhc2_vmmc {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pinctrl_uart4 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc2 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc3 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pinctrl_wdog {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pmic {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
/* USB1 Type-C */
|
||||
&usb3_phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_0 {
|
||||
fsl,over-current-active-low;
|
||||
fsl,power-active-low;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_dwc3_0 {
|
||||
dr_mode = "peripheral";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* USB2 4-port USB3.0 HUB */
|
||||
&usb3_phy1 {
|
||||
vbus-supply = <®_vdd_5v0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_1 {
|
||||
fsl,permanently-attached;
|
||||
fsl,disable-port-power-control;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_dwc3_1 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
@ -69,6 +69,16 @@
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&pinctrl_lpi2c3 {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&pinctrl_pmic {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&pinctrl_reg_usdhc2_vmmc {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
@ -83,6 +93,16 @@
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc1_100mhz {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc1_200mhz {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc2_cd {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
@ -128,31 +148,9 @@
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
/*
|
||||
* Remove once USB support is added to imx93-phyboard-segin.dts upstream.
|
||||
*/
|
||||
&usbotg1 {
|
||||
disable-over-current;
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg2 {
|
||||
disable-over-current;
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
/*
|
||||
* Remove pinctrl assignments once they are added to imx93-phycore-som.dtsi
|
||||
*/
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
@ -174,6 +172,21 @@
|
||||
&lpi2c3 {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
|
||||
pmic@25 {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
|
||||
regulators {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
};
|
||||
|
||||
eeprom@50 {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
};
|
||||
|
||||
&s4muap {
|
||||
@ -209,165 +222,3 @@
|
||||
bootph-all;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
/*
|
||||
* The two nodes below won't be needed once nxp,pca9451a
|
||||
* support is added to the Linux kernel.
|
||||
*/
|
||||
&iomuxc {
|
||||
pinctrl_lpi2c3: lpi2c3grp {
|
||||
bootph-pre-ram;
|
||||
fsl,pins = <
|
||||
MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
|
||||
MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicgrp {
|
||||
bootph-pre-ram;
|
||||
fsl,pins = <
|
||||
MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e
|
||||
>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Remove pinctrl_usdhc1_100mhz and pinctrl_usdhc1_200mhz once they
|
||||
* are added to imx93-phycore-som.dtsi
|
||||
*/
|
||||
/* need to config the SION for data and cmd pad, refer to ERR052021 */
|
||||
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
fsl,pins = <
|
||||
MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be
|
||||
MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
|
||||
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
|
||||
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e
|
||||
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be
|
||||
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e
|
||||
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e
|
||||
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e
|
||||
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e
|
||||
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e
|
||||
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
|
||||
>;
|
||||
};
|
||||
|
||||
/* need to config the SION for data and cmd pad, refer to ERR052021 */
|
||||
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
fsl,pins = <
|
||||
MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be
|
||||
MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
|
||||
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e
|
||||
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be
|
||||
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be
|
||||
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013be
|
||||
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be
|
||||
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be
|
||||
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be
|
||||
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be
|
||||
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&lpi2c3 {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&pinctrl_lpi2c3>;
|
||||
pinctrl-1 = <&pinctrl_lpi2c3>;
|
||||
status = "okay";
|
||||
|
||||
pmic@25 {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
compatible = "nxp,pca9451a";
|
||||
reg = <0x25>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pmic>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
regulators {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
buck1: BUCK1 {
|
||||
regulator-name = "VDD_SOC";
|
||||
regulator-min-microvolt = <610000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <3125>;
|
||||
};
|
||||
|
||||
buck2: BUCK2 {
|
||||
regulator-name = "VDDQ_0V6";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <600000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck4: BUCK4 {
|
||||
regulator-name = "VDD_3V3_BUCK";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck5: BUCK5 {
|
||||
regulator-name = "VDD_1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck6: BUCK6 {
|
||||
regulator-name = "VDD_1V1";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1: LDO1 {
|
||||
regulator-name = "PMIC_SNVS_1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4: LDO4 {
|
||||
regulator-name = "VDD_0V8";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo5: LDO5 {
|
||||
regulator-name = "NVCC_SD2";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
eeprom@50 {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
compatible = "atmel,24c32";
|
||||
reg = <0x50>;
|
||||
pagesize = <32>;
|
||||
vcc-supply = <&buck4>;
|
||||
};
|
||||
};
|
||||
|
||||
62
arch/arm/dts/imx943-evk-u-boot.dtsi
Normal file
62
arch/arm/dts/imx943-evk-u-boot.dtsi
Normal file
@ -0,0 +1,62 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2025 NXP
|
||||
*/
|
||||
|
||||
#include "imx943-u-boot.dtsi"
|
||||
|
||||
&lpuart1 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
®_usdhc2_vmmc {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&wdog3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pinctrl_reg_usdhc2_vmmc {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pinctrl_uart1 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc1 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc1_100mhz {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc1_200mhz {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc2 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc2_100mhz {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc2_200mhz {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc2_gpio {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
212
arch/arm/dts/imx943-u-boot.dtsi
Normal file
212
arch/arm/dts/imx943-u-boot.dtsi
Normal file
@ -0,0 +1,212 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2025 NXP
|
||||
*/
|
||||
|
||||
/ {
|
||||
binman {
|
||||
multiple-images;
|
||||
|
||||
m33-oei-ddrfw {
|
||||
pad-byte = <0x00>;
|
||||
align-size = <0x8>;
|
||||
filename = "m33-oei-ddrfw.bin";
|
||||
|
||||
oei-m33-ddr {
|
||||
align-size = <0x4>;
|
||||
filename = "oei-m33-ddr.bin";
|
||||
type = "blob-ext";
|
||||
};
|
||||
|
||||
imx-lpddr {
|
||||
type = "nxp-header-ddrfw";
|
||||
|
||||
imx-lpddr-imem {
|
||||
filename = "lpddr5_imem_v202409.bin";
|
||||
type = "blob-ext";
|
||||
};
|
||||
|
||||
imx-lpddr-dmem {
|
||||
filename = "lpddr5_dmem_v202409.bin";
|
||||
type = "blob-ext";
|
||||
};
|
||||
};
|
||||
|
||||
imx-lpddr-qb {
|
||||
type = "nxp-header-ddrfw";
|
||||
|
||||
imx-lpddr-imem-qb {
|
||||
filename = "lpddr5_imem_qb_v202409.bin";
|
||||
type = "blob-ext";
|
||||
};
|
||||
|
||||
imx-lpddr-dmem-qb {
|
||||
filename = "lpddr5_dmem_qb_v202409.bin";
|
||||
type = "blob-ext";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
imx-boot {
|
||||
filename = "flash.bin";
|
||||
pad-byte = <0x00>;
|
||||
|
||||
spl {
|
||||
type = "nxp-imx9image";
|
||||
cfg-path = "spl/u-boot-spl.cfgout";
|
||||
args;
|
||||
|
||||
cntr-version = <2>;
|
||||
boot-from = "sd";
|
||||
soc-type = "IMX9";
|
||||
append = "mx943a0-ahab-container.img";
|
||||
container;
|
||||
dummy-ddr;
|
||||
image0 = "oei", "m33-oei-ddrfw.bin", "0x1ffc0000";
|
||||
hold = <0x10000>;
|
||||
image1 = "m33", "m33_image.bin", "0x1ffc0000";
|
||||
image2 = "a55", "spl/u-boot-spl.bin", "0x20480000";
|
||||
dummy-v2x = <0x8b000000>;
|
||||
};
|
||||
|
||||
u-boot {
|
||||
type = "nxp-imx9image";
|
||||
cfg-path = "u-boot-container.cfgout";
|
||||
args;
|
||||
|
||||
cntr-version = <2>;
|
||||
boot-from = "sd";
|
||||
soc-type = "IMX9";
|
||||
container;
|
||||
image0 = "a55", "bl31.bin", "0x8a200000";
|
||||
image1 = "a55", "u-boot.bin", "0x90200000";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
clocks = <&scmi_clk IMX94_CLK_ARMPLL_PFD0>;
|
||||
/delete-property/ power-domains;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
clocks = <&scmi_clk IMX94_CLK_ARMPLL_PFD0>;
|
||||
/delete-property/ power-domains;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
clocks = <&scmi_clk IMX94_CLK_ARMPLL_PFD0>;
|
||||
/delete-property/ power-domains;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
clocks = <&scmi_clk IMX94_CLK_ARMPLL_PFD0>;
|
||||
/delete-property/ power-domains;
|
||||
};
|
||||
|
||||
&aips1 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&aips2 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&aips3 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&clk_ext1 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&dummy {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&{/firmware} {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&{/firmware/scmi} {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&{/firmware/scmi/protocol@11} {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&{/firmware/scmi/protocol@13} {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&{/firmware/scmi/protocol@14} {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&{/firmware/scmi/protocol@19} {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&gpio6 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&gpio7 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&mu2 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&osc_24m {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&scmi_buf0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&scmi_buf1 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&{/soc} {
|
||||
bootph-all;
|
||||
|
||||
elemu1: mailbox@47530000 {
|
||||
compatible = "fsl,imx93-mu-s4";
|
||||
reg = <0x0 0x47530000 0x0 0x10000>;
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
elemu3: mailbox@47550000 {
|
||||
compatible = "fsl,imx93-mu-s4";
|
||||
reg = <0x0 0x47550000 0x0 0x10000>;
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&sram0 {
|
||||
bootph-all;
|
||||
};
|
||||
@ -5,6 +5,13 @@
|
||||
|
||||
#include "imx95-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
pci0 = &netc_bus0;
|
||||
pci1 = &netc_bus1;
|
||||
};
|
||||
};
|
||||
|
||||
&lpuart1 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
@ -202,6 +202,22 @@
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
|
||||
<&scmi_clk IMX95_CLK_HSIOPLL>,
|
||||
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
|
||||
assigned-clock-parents = <0>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
|
||||
<&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
|
||||
<&scmi_clk IMX95_CLK_HSIOPLL>,
|
||||
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
|
||||
assigned-clock-parents = <0>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
|
||||
<&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
|
||||
};
|
||||
|
||||
&{/soc} {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
@ -95,6 +95,22 @@
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_rti1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_rti2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_rti3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_rti15 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
@ -156,6 +156,22 @@
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_rti1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_rti2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_rti3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_rti4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
@ -156,6 +156,10 @@
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_rti1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
@ -139,7 +139,6 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi_flash_pins>;
|
||||
status = "okay";
|
||||
must_tx;
|
||||
enhance_timing;
|
||||
dma_ext;
|
||||
ipm_design;
|
||||
@ -162,7 +161,6 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi2_flash_pins>;
|
||||
status = "okay";
|
||||
must_tx;
|
||||
enhance_timing;
|
||||
dma_ext;
|
||||
ipm_design;
|
||||
|
||||
@ -173,7 +173,6 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi_flash_pins>;
|
||||
status = "okay";
|
||||
must_tx;
|
||||
enhance_timing;
|
||||
dma_ext;
|
||||
ipm_design;
|
||||
|
||||
@ -178,7 +178,6 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi_flash_pins>;
|
||||
status = "okay";
|
||||
must_tx;
|
||||
enhance_timing;
|
||||
dma_ext;
|
||||
ipm_design;
|
||||
|
||||
@ -138,7 +138,6 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi_flash_pins>;
|
||||
status = "okay";
|
||||
must_tx;
|
||||
enhance_timing;
|
||||
dma_ext;
|
||||
ipm_design;
|
||||
|
||||
@ -165,7 +165,6 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi_flash_pins>;
|
||||
status = "okay";
|
||||
must_tx;
|
||||
enhance_timing;
|
||||
dma_ext;
|
||||
ipm_design;
|
||||
|
||||
@ -134,7 +134,6 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi_flash_pins>;
|
||||
status = "okay";
|
||||
must_tx;
|
||||
enhance_timing;
|
||||
dma_ext;
|
||||
ipm_design;
|
||||
|
||||
@ -42,7 +42,6 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
must_tx;
|
||||
enhance_timing;
|
||||
dma_ext;
|
||||
ipm_design;
|
||||
|
||||
@ -28,7 +28,6 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
must_tx;
|
||||
enhance_timing;
|
||||
dma_ext;
|
||||
ipm_design;
|
||||
@ -52,7 +51,6 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
must_tx;
|
||||
enhance_timing;
|
||||
dma_ext;
|
||||
ipm_design;
|
||||
|
||||
@ -40,7 +40,6 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
must_tx;
|
||||
enhance_timing;
|
||||
dma_ext;
|
||||
ipm_design;
|
||||
|
||||
@ -181,7 +181,6 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
must_tx;
|
||||
enhance_timing;
|
||||
dma_ext;
|
||||
ipm_design;
|
||||
@ -204,7 +203,6 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
must_tx;
|
||||
enhance_timing;
|
||||
dma_ext;
|
||||
ipm_design;
|
||||
|
||||
@ -108,7 +108,6 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
must_tx;
|
||||
enhance_timing;
|
||||
dma_ext;
|
||||
ipm_design;
|
||||
|
||||
@ -62,6 +62,11 @@
|
||||
reg = <0x0 0xf0801000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
timer0: timer@f0801068 {
|
||||
compatible = "nuvoton,npcm845-timer";
|
||||
reg = <0x0 0xf0801068 0x0 0x8>;
|
||||
};
|
||||
|
||||
sdhci0: sdhci@f0842000 {
|
||||
compatible = "nuvoton,npcm845-sdhci";
|
||||
reg = <0x0 0xf0842000 0x0 0x100>;
|
||||
@ -136,7 +141,7 @@
|
||||
|
||||
host_intf: host_intf@9f000 {
|
||||
compatible = "nuvoton,npcm845-host-intf";
|
||||
reg = <0x9f000 0x1000>;
|
||||
reg = <0x9f000 0x1000>, <0x7000 0x40>;
|
||||
type = "espi";
|
||||
ioaddr = <0x4e>;
|
||||
channel-support = <0xf>;
|
||||
@ -157,14 +162,6 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer0: timer@8000 {
|
||||
compatible = "nuvoton,npcm845-timer";
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x8000 0x1C>;
|
||||
clocks = <&clk NPCM8XX_CLK_REFCLK>;
|
||||
clock-names = "refclk";
|
||||
};
|
||||
|
||||
serial0: serial@0 {
|
||||
compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
|
||||
reg = <0x0 0x1000>;
|
||||
|
||||
@ -1056,5 +1056,9 @@
|
||||
groups = "jtag2";
|
||||
function = "jtag2";
|
||||
};
|
||||
vcdhs_pins: vcdhs-pins {
|
||||
groups = "vcdhs";
|
||||
function = "vcdhs";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -45,7 +45,7 @@
|
||||
compatible = "maxim,max8998";
|
||||
reg = <0x66 0 0>;
|
||||
|
||||
voltage-regulators {
|
||||
regulators {
|
||||
ldo2_reg: LDO2 {
|
||||
regulator-compatible = "LDO2";
|
||||
regulator-name = "VALIVE_1.1V";
|
||||
|
||||
@ -209,7 +209,7 @@
|
||||
/* DMIUSMCTCR */
|
||||
<0x00000300 0x00000001 0x00000003>,
|
||||
<0x00000300 0x00000003 0x00000003>,
|
||||
<0x00000308 0x00000004 0x0000001F>;
|
||||
<0x00000308 0x0000000C 0x0000001F>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
@ -220,7 +220,7 @@
|
||||
/* DMIUSMCTCR */
|
||||
<0x00000300 0x00000001 0x00000003>,
|
||||
<0x00000300 0x00000003 0x00000003>,
|
||||
<0x00000308 0x00000004 0x0000001F>;
|
||||
<0x00000308 0x0000000C 0x0000001F>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
@ -87,6 +87,10 @@
|
||||
disable-over-current;
|
||||
};
|
||||
|
||||
&usb31 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -232,6 +232,18 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nand: nand@ffb90000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "altr,socfpga-denali-nand";
|
||||
reg = <0xffb90000 0x10000>,
|
||||
<0xffb80000 0x1000>;
|
||||
reg-names = "nand_data", "denali_reg";
|
||||
interrupts = <0 97 4>;
|
||||
resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ocram: sram@ffe00000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0xffe00000 0x100000>;
|
||||
|
||||
@ -137,3 +137,7 @@
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -12,6 +12,47 @@
|
||||
};
|
||||
};
|
||||
|
||||
&flash0 {
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "fsbla1";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
};
|
||||
partition@40000 {
|
||||
label = "fsbla2";
|
||||
reg = <0x00040000 0x00040000>;
|
||||
};
|
||||
partition@80000 {
|
||||
label = "metadata1";
|
||||
reg = <0x00080000 0x00040000>;
|
||||
};
|
||||
partition@C0000 {
|
||||
label = "metadata2";
|
||||
reg = <0x000C0000 0x00040000>;
|
||||
};
|
||||
partition@100000 {
|
||||
label = "fip-a";
|
||||
reg = <0x00100000 0x00400000>;
|
||||
};
|
||||
partition@500000 {
|
||||
label = "fip-b";
|
||||
reg = <0x00500000 0x00400000>;
|
||||
};
|
||||
partition@900000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x00900000 0x00080000>;
|
||||
};
|
||||
partition@980000 {
|
||||
label = "nor-user";
|
||||
reg = <0x00980000 0x03680000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usart2 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
@ -1,10 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2016 Broadcom Corporation.
|
||||
*/
|
||||
|
||||
/* BOOT0 header information */
|
||||
_start:
|
||||
ARM_VECTORS
|
||||
.word 0xbabeface
|
||||
.word _end - _start
|
||||
@ -1,14 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2013 Broadcom Corporation.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_BCM235XX_GPIO_H
|
||||
#define __ARCH_BCM235XX_GPIO_H
|
||||
|
||||
/*
|
||||
* Empty file - cmd_gpio.c requires this. The implementation
|
||||
* is in drivers/gpio/kona_gpio.c instead of inlined here.
|
||||
*/
|
||||
|
||||
#endif
|
||||
@ -1,30 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2013 Broadcom Corporation.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_BCM235XX_SYSMAP_H
|
||||
|
||||
#define BSC1_BASE_ADDR 0x3e016000
|
||||
#define BSC2_BASE_ADDR 0x3e017000
|
||||
#define BSC3_BASE_ADDR 0x3e018000
|
||||
#define GPIO2_BASE_ADDR 0x35003000
|
||||
#define HSOTG_BASE_ADDR 0x3f120000
|
||||
#define HSOTG_CTRL_BASE_ADDR 0x3f130000
|
||||
#define KONA_MST_CLK_BASE_ADDR 0x3f001000
|
||||
#define KONA_SLV_CLK_BASE_ADDR 0x3e011000
|
||||
#define PMU_BSC_BASE_ADDR 0x3500d000
|
||||
#define SDIO1_BASE_ADDR 0x3f180000
|
||||
#define SDIO2_BASE_ADDR 0x3f190000
|
||||
#define SDIO3_BASE_ADDR 0x3f1a0000
|
||||
#define SDIO4_BASE_ADDR 0x3f1b0000
|
||||
#define TIMER_BASE_ADDR 0x3e00d000
|
||||
|
||||
#define HSOTG_DCTL_OFFSET 0x00000804
|
||||
#define HSOTG_DCTL_SFTDISCON_MASK 0x00000002
|
||||
|
||||
#define HSOTG_CTRL_PHY_P1CTL_OFFSET 0x00000008
|
||||
#define HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK 0x00000002
|
||||
#define HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK 0x00000001
|
||||
|
||||
#endif
|
||||
@ -78,6 +78,8 @@
|
||||
|
||||
#define MXC_CPU_IMX95 0x1C1 /* dummy ID */
|
||||
|
||||
#define MXC_CPU_IMX94 0x1C2 /* dummy ID */
|
||||
|
||||
#define MXC_SOC_MX6 0x60
|
||||
#define MXC_SOC_MX7 0x70
|
||||
#define MXC_SOC_IMX8M 0x80
|
||||
|
||||
@ -17,14 +17,23 @@
|
||||
|
||||
#define ANATOP_BASE_ADDR 0x44480000UL
|
||||
|
||||
#ifdef CONFIG_IMX94
|
||||
#define WDG3_BASE_ADDR 0x49220000UL
|
||||
#define WDG4_BASE_ADDR 0x49230000UL
|
||||
#else
|
||||
#define WDG3_BASE_ADDR 0x42490000UL
|
||||
#define WDG4_BASE_ADDR 0x424a0000UL
|
||||
#endif
|
||||
#define WDG5_BASE_ADDR 0x424b0000UL
|
||||
|
||||
#define GPIO2_BASE_ADDR 0x43810000UL
|
||||
#define GPIO3_BASE_ADDR 0x43820000UL
|
||||
#define GPIO4_BASE_ADDR 0x43840000UL
|
||||
#define GPIO5_BASE_ADDR 0x43850000UL
|
||||
#ifdef CONFIG_IMX94
|
||||
#define GPIO6_BASE_ADDR 0x43860000UL
|
||||
#define GPIO7_BASE_ADDR 0x43870000UL
|
||||
#endif
|
||||
|
||||
#define FSB_BASE_ADDR 0x47510000UL
|
||||
|
||||
@ -48,7 +57,7 @@
|
||||
#define SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT BIT(8)
|
||||
#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12)
|
||||
|
||||
#define IMG_CONTAINER_BASE (0x80000000UL)
|
||||
#define IMG_CONTAINER_BASE CFG_SYS_SDRAM_BASE
|
||||
|
||||
#define BCTRL_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 1)
|
||||
#define BCTRL_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1)
|
||||
|
||||
@ -21,6 +21,7 @@ int m33_prepare(void);
|
||||
int low_drive_freq_update(void *blob);
|
||||
|
||||
enum imx9_soc_voltage_mode soc_target_voltage_mode(void);
|
||||
int get_reset_reason(bool sys, bool lm);
|
||||
|
||||
#define is_voltage_mode(mode) (soc_target_voltage_mode() == (mode))
|
||||
|
||||
|
||||
@ -11,6 +11,7 @@
|
||||
#define MIDR_PARTNUM_CORTEX_A73 0xD09
|
||||
#define MIDR_PARTNUM_CORTEX_A75 0xD0A
|
||||
#define MIDR_PARTNUM_CORTEX_A76 0xD0B
|
||||
#define MIDR_PARTNUM_CORTEX_A720 0xD81
|
||||
#define MIDR_PARTNUM_SHIFT 0x4
|
||||
#define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT)
|
||||
|
||||
@ -40,3 +41,4 @@ is_cortex_a(72)
|
||||
is_cortex_a(73)
|
||||
is_cortex_a(75)
|
||||
is_cortex_a(76)
|
||||
is_cortex_a(720)
|
||||
|
||||
@ -386,12 +386,14 @@ void __memcpy_fromio(void *to, const volatile void __iomem *from, size_t count)
|
||||
count--;
|
||||
}
|
||||
|
||||
if (mmu_status()) {
|
||||
while (count >= 8) {
|
||||
*(u64 *)to = __raw_readq(from);
|
||||
from += 8;
|
||||
to += 8;
|
||||
count -= 8;
|
||||
if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) {
|
||||
if (mmu_status()) {
|
||||
while (count >= 8) {
|
||||
*(u64 *)to = __raw_readq(from);
|
||||
from += 8;
|
||||
to += 8;
|
||||
count -= 8;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -416,12 +418,14 @@ void __memcpy_toio(volatile void __iomem *to, const void *from, size_t count)
|
||||
count--;
|
||||
}
|
||||
|
||||
if (mmu_status()) {
|
||||
while (count >= 8) {
|
||||
__raw_writeq(*(u64 *)from, to);
|
||||
from += 8;
|
||||
to += 8;
|
||||
count -= 8;
|
||||
if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) {
|
||||
if (mmu_status()) {
|
||||
while (count >= 8) {
|
||||
__raw_writeq(*(u64 *)from, to);
|
||||
from += 8;
|
||||
to += 8;
|
||||
count -= 8;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -97,6 +97,7 @@ struct bd_info;
|
||||
#define is_imx9302() (is_cpu_type(MXC_CPU_IMX9302))
|
||||
#define is_imx9301() (is_cpu_type(MXC_CPU_IMX9301))
|
||||
|
||||
#define is_imx94() (is_cpu_type(MXC_CPU_IMX94))
|
||||
#define is_imx95() (is_cpu_type(MXC_CPU_IMX95))
|
||||
|
||||
#define is_imx9121() (is_cpu_type(MXC_CPU_IMX9121))
|
||||
|
||||
@ -57,6 +57,7 @@ static void announce_and_cleanup(int fake)
|
||||
#ifdef CONFIG_BOOTSTAGE_FDT
|
||||
bootstage_fdt_add_report();
|
||||
#endif
|
||||
bootstage_stash_default();
|
||||
#ifdef CONFIG_BOOTSTAGE_REPORT
|
||||
bootstage_report();
|
||||
#endif
|
||||
|
||||
@ -158,8 +158,10 @@ relocation_return:
|
||||
/*
|
||||
* Clear BSS section
|
||||
*/
|
||||
ldr x0, =__bss_start /* this is auto-relocated! */
|
||||
ldr x1, =__bss_end /* this is auto-relocated! */
|
||||
adrp x0, __bss_start
|
||||
add x0, x0, #:lo12:__bss_start
|
||||
adrp x1, __bss_end
|
||||
add x1, x1, #:lo12:__bss_end
|
||||
clear_loop:
|
||||
str xzr, [x0], #8
|
||||
cmp x0, x1
|
||||
|
||||
@ -46,8 +46,7 @@ void __weak board_init_f(ulong dummy)
|
||||
}
|
||||
|
||||
/*
|
||||
* This function jumps to an image with argument. Normally an FDT or ATAGS
|
||||
* image.
|
||||
* This function jumps to an image with argument, usually an FDT.
|
||||
*/
|
||||
#if CONFIG_IS_ENABLED(OS_BOOT)
|
||||
#ifdef CONFIG_ARM64
|
||||
|
||||
@ -223,7 +223,7 @@ endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_IMX9)$(CONFIG_ARCH_IMX8ULP), y)
|
||||
|
||||
ifneq ($(and $(CONFIG_IMX95),$(CONFIG_BINMAN)),)
|
||||
ifneq ($(and $(CONFIG_BINMAN),$(or $(CONFIG_IMX95),$(CONFIG_IMX94))),)
|
||||
SPL: spl/u-boot-spl.bin FORCE
|
||||
$(call if_changed,mkimage)
|
||||
else
|
||||
|
||||
@ -411,6 +411,54 @@ static int do_authenticate(struct cmd_tbl *cmdtp, int flag, int argc,
|
||||
return CMD_RET_SUCCESS;
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_IMX95) || IS_ENABLED(CONFIG_IMX94)
|
||||
#define FSB_LC_OFFSET 0x414
|
||||
#define LC_OEM_OPEN 0x10
|
||||
static void display_life_cycle(u32 lc)
|
||||
{
|
||||
printf("Lifecycle: 0x%08X, ", lc);
|
||||
switch (lc) {
|
||||
case 0x1:
|
||||
printf("BLANK\n\n");
|
||||
break;
|
||||
case 0x2:
|
||||
printf("FAB Default\n\n");
|
||||
break;
|
||||
case 0x4:
|
||||
printf("FAB\n\n");
|
||||
break;
|
||||
case 0x8:
|
||||
printf("NXP Provisioned\n\n");
|
||||
break;
|
||||
case 0x10:
|
||||
printf("OEM Open\n\n");
|
||||
break;
|
||||
case 0x20:
|
||||
printf("OEM secure world closed\n\n");
|
||||
break;
|
||||
case 0x40:
|
||||
printf("OEM closed\n\n");
|
||||
break;
|
||||
case 0x80:
|
||||
printf("OEM Locked\n\n");
|
||||
break;
|
||||
case 0x100:
|
||||
printf("Field Return OEM\n\n");
|
||||
break;
|
||||
case 0x200:
|
||||
printf("Field Return NXP\n\n");
|
||||
break;
|
||||
case 0x400:
|
||||
printf("BRICKED\n\n");
|
||||
break;
|
||||
default:
|
||||
printf("Unknown\n\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
#else
|
||||
#define FSB_LC_OFFSET 0x41c
|
||||
#define LC_OEM_OPEN 0x8
|
||||
static void display_life_cycle(u32 lc)
|
||||
{
|
||||
printf("Lifecycle: 0x%08X, ", lc);
|
||||
@ -447,6 +495,7 @@ static void display_life_cycle(u32 lc)
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static int confirm_close(void)
|
||||
{
|
||||
@ -474,10 +523,10 @@ static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc,
|
||||
if (!confirm_close())
|
||||
return -EACCES;
|
||||
|
||||
lc = readl(FSB_BASE_ADDR + 0x41c);
|
||||
lc = readl(FSB_BASE_ADDR + FSB_LC_OFFSET);
|
||||
lc &= 0x3ff;
|
||||
|
||||
if (lc != 0x8) {
|
||||
if (lc != LC_OEM_OPEN) {
|
||||
puts("Current lifecycle is NOT OEM open, can't move to OEM closed\n");
|
||||
display_life_cycle(lc);
|
||||
return -EPERM;
|
||||
@ -540,7 +589,7 @@ static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const
|
||||
u32 cnt = AHAB_MAX_EVENTS;
|
||||
int ret;
|
||||
|
||||
lc = readl(FSB_BASE_ADDR + 0x41c);
|
||||
lc = readl(FSB_BASE_ADDR + FSB_LC_OFFSET);
|
||||
lc &= 0x3ff;
|
||||
|
||||
display_life_cycle(lc);
|
||||
|
||||
@ -297,7 +297,7 @@ static ulong get_imageset_end(void *dev, int dev_type)
|
||||
|
||||
debug("seco container size 0x%x\n", value_container[0]);
|
||||
|
||||
if (is_imx95()) {
|
||||
if (is_imx95() || is_imx94()) {
|
||||
offset[1] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + offset[0];
|
||||
|
||||
value_container[1] = get_dev_container_size(dev, dev_type, offset[1], &hdr_length, &v2x_fw);
|
||||
@ -321,7 +321,7 @@ static ulong get_imageset_end(void *dev, int dev_type)
|
||||
value_container[2] = get_dev_container_size(dev, dev_type, offset[2], &hdr_length, NULL);
|
||||
if (value_container[2] < 0) {
|
||||
debug("Parse scu container image failed %d, only seco container\n", value_container[2]);
|
||||
if (is_imx95())
|
||||
if (is_imx95() || is_imx94())
|
||||
return value_container[1] + offset[1]; /* return seco + v2x container total size */
|
||||
else
|
||||
return value_container[0] + offset[0]; /* return seco container total size */
|
||||
|
||||
@ -401,6 +401,29 @@ static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int do_ahab_commit(struct cmd_tbl *cmdtp, int flag, int argc,
|
||||
char *const argv[])
|
||||
{
|
||||
u32 info;
|
||||
int ret;
|
||||
|
||||
if (argc < 2)
|
||||
return CMD_RET_USAGE;
|
||||
|
||||
info = simple_strtoul(argv[1], NULL, 16);
|
||||
printf("Commit index is 0x%x\n", info);
|
||||
|
||||
ret = sc_seco_commit(-1, &info);
|
||||
if (ret) {
|
||||
printf("Error in AHAB commit\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
printf("AHAB commit succeeded.\n");
|
||||
|
||||
return CMD_RET_SUCCESS;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate,
|
||||
"autenticate OS container via AHAB",
|
||||
"addr\n"
|
||||
@ -416,3 +439,9 @@ U_BOOT_CMD(ahab_close, CONFIG_SYS_MAXARGS, 1, do_ahab_close,
|
||||
"Change AHAB lifecycle to OEM closed",
|
||||
""
|
||||
);
|
||||
|
||||
U_BOOT_CMD(ahab_commit, CONFIG_SYS_MAXARGS, 1, do_ahab_commit,
|
||||
"commit into the fuses any new SRK revocation information that have been found\n"
|
||||
"into the NXP (SECO FW) and OEM containers. For SRK revocation use 0x10 for the value.",
|
||||
""
|
||||
);
|
||||
|
||||
@ -345,6 +345,15 @@ config TARGET_PHYCORE_IMX8MP
|
||||
select IMX8M_LPDDR4
|
||||
imply OF_UPSTREAM
|
||||
|
||||
config TARGET_IMX8MP_LIBRA_FPSC
|
||||
bool "PHYTEC Libra i.MX 8M Plus FPSC"
|
||||
select IMX8MP
|
||||
select SUPPORT_SPL
|
||||
select IMX8M_LPDDR4
|
||||
imply OF_UPSTREAM
|
||||
help
|
||||
Libra i.MX8M Plus FPSC is an SBC based on the NXP i.MX 8M Plus SoC.
|
||||
|
||||
config TARGET_IMX8MM_CL_IOT_GATE
|
||||
bool "CompuLab iot-gate-imx8"
|
||||
select IMX8MM
|
||||
@ -409,6 +418,7 @@ source "board/kontron/sl-mx8mm/Kconfig"
|
||||
source "board/menlo/mx8menlo/Kconfig"
|
||||
source "board/msc/sm2s_imx8mp/Kconfig"
|
||||
source "board/mntre/imx8mq_reform2/Kconfig"
|
||||
source "board/phytec/imx8mp-libra-fpsc/Kconfig"
|
||||
source "board/phytec/phycore_imx8mm/Kconfig"
|
||||
source "board/phytec/phycore_imx8mp/Kconfig"
|
||||
source "board/polyhex/imx8mp_debix_model_a/Kconfig"
|
||||
|
||||
@ -38,6 +38,15 @@ config IMX95
|
||||
select SPL_IMX_CONTAINER_USE_TRAMPOLINE
|
||||
select IMX_PQC_SUPPORT if !IMX95_A0
|
||||
|
||||
config IMX94
|
||||
bool
|
||||
select ARMV8_SPL_EXCEPTION_VECTORS
|
||||
select DM_MAILBOX
|
||||
select IMX9
|
||||
select IMX_PQC_SUPPORT
|
||||
select SCMI_FIRMWARE
|
||||
select SPL_IMX_CONTAINER_USE_TRAMPOLINE
|
||||
|
||||
config SYS_SOC
|
||||
default "imx9"
|
||||
|
||||
@ -97,6 +106,13 @@ config TARGET_IMX95_19X19_EVK
|
||||
imply BOOTSTD_FULL
|
||||
imply OF_UPSTREAM
|
||||
|
||||
config TARGET_IMX943_EVK
|
||||
bool "imx943_evk"
|
||||
select IMX94
|
||||
imply BOOTSTD_BOOTCOMMAND
|
||||
imply BOOTSTD_FULL
|
||||
imply OF_UPSTREAM
|
||||
|
||||
endchoice
|
||||
|
||||
source "board/freescale/imx91_evk/Kconfig"
|
||||
@ -105,6 +121,7 @@ source "board/freescale/imx93_frdm/Kconfig"
|
||||
source "board/freescale/imx93_qsb/Kconfig"
|
||||
source "board/phytec/phycore_imx93/Kconfig"
|
||||
source "board/variscite/imx93_var_som/Kconfig"
|
||||
source "board/freescale/imx94_evk/Kconfig"
|
||||
source "board/freescale/imx95_evk/Kconfig"
|
||||
|
||||
endif
|
||||
|
||||
@ -2,5 +2,8 @@
|
||||
#
|
||||
# Copyright 2025 NXP
|
||||
|
||||
# Add include path for NXP device tree header files from Linux.
|
||||
ccflags-y += -I$(srctree)/dts/upstream/src/arm64/freescale/
|
||||
|
||||
obj-y += soc.o
|
||||
obj-y += clock_scmi.o clock.o
|
||||
|
||||
@ -6,16 +6,17 @@
|
||||
#include <asm/arch/clock.h>
|
||||
#include <dm/uclass.h>
|
||||
#include <scmi_agent.h>
|
||||
#include "../../../../../dts/upstream/src/arm64/freescale/imx95-clock.h"
|
||||
#include <scmi_nxp_protocols.h>
|
||||
#include "common.h"
|
||||
|
||||
u32 get_arm_core_clk(void)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = imx_clk_scmi_get_rate(IMX95_CLK_SEL_A55C0);
|
||||
val = imx_clk_scmi_get_rate(SCMI_CLK(SEL_A55C0));
|
||||
if (val)
|
||||
return val;
|
||||
return imx_clk_scmi_get_rate(IMX95_CLK_A55);
|
||||
return imx_clk_scmi_get_rate(SCMI_CLK(A55));
|
||||
}
|
||||
|
||||
void init_uart_clk(u32 index)
|
||||
@ -24,13 +25,13 @@ void init_uart_clk(u32 index)
|
||||
|
||||
switch (index) {
|
||||
case 0:
|
||||
clock_id = IMX95_CLK_LPUART1;
|
||||
clock_id = SCMI_CLK(LPUART1);
|
||||
break;
|
||||
case 1:
|
||||
clock_id = IMX95_CLK_LPUART2;
|
||||
clock_id = SCMI_CLK(LPUART2);
|
||||
break;
|
||||
case 2:
|
||||
clock_id = IMX95_CLK_LPUART3;
|
||||
clock_id = SCMI_CLK(LPUART3);
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
@ -38,7 +39,7 @@ void init_uart_clk(u32 index)
|
||||
|
||||
/* 24MHz */
|
||||
imx_clk_scmi_enable(clock_id, false);
|
||||
imx_clk_scmi_set_parent(clock_id, IMX95_CLK_24M);
|
||||
imx_clk_scmi_set_parent(clock_id, SCMI_CLK(24M));
|
||||
imx_clk_scmi_set_rate(clock_id, 24000000);
|
||||
imx_clk_scmi_enable(clock_id, true);
|
||||
}
|
||||
@ -49,19 +50,19 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
|
||||
case MXC_ARM_CLK:
|
||||
return get_arm_core_clk();
|
||||
case MXC_IPG_CLK:
|
||||
return imx_clk_scmi_get_rate(IMX95_CLK_BUSWAKEUP);
|
||||
return imx_clk_scmi_get_rate(SCMI_CLK(BUSWAKEUP));
|
||||
case MXC_CSPI_CLK:
|
||||
return imx_clk_scmi_get_rate(IMX95_CLK_LPSPI1);
|
||||
return imx_clk_scmi_get_rate(SCMI_CLK(LPSPI1));
|
||||
case MXC_ESDHC_CLK:
|
||||
return imx_clk_scmi_get_rate(IMX95_CLK_USDHC1);
|
||||
return imx_clk_scmi_get_rate(SCMI_CLK(USDHC1));
|
||||
case MXC_ESDHC2_CLK:
|
||||
return imx_clk_scmi_get_rate(IMX95_CLK_USDHC2);
|
||||
return imx_clk_scmi_get_rate(SCMI_CLK(USDHC2));
|
||||
case MXC_ESDHC3_CLK:
|
||||
return imx_clk_scmi_get_rate(IMX95_CLK_USDHC3);
|
||||
return imx_clk_scmi_get_rate(SCMI_CLK(USDHC3));
|
||||
case MXC_UART_CLK:
|
||||
return imx_clk_scmi_get_rate(IMX95_CLK_LPUART1);
|
||||
return imx_clk_scmi_get_rate(SCMI_CLK(LPUART1));
|
||||
case MXC_FLEXSPI_CLK:
|
||||
return imx_clk_scmi_get_rate(IMX95_CLK_FLEXSPI1);
|
||||
return imx_clk_scmi_get_rate(SCMI_CLK(FLEXSPI1));
|
||||
default:
|
||||
return -1;
|
||||
};
|
||||
|
||||
41
arch/arm/mach-imx/imx9/scmi/common.h
Normal file
41
arch/arm/mach-imx/imx9/scmi/common.h
Normal file
@ -0,0 +1,41 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2025 NXP
|
||||
*/
|
||||
|
||||
#ifndef _SCMI_CLOCK_COMMON_H_
|
||||
#define _SCMI_CLOCK_COMMON_H_
|
||||
|
||||
#ifdef CONFIG_IMX94
|
||||
#define IMX_PLAT 94
|
||||
#include <imx94-clock.h>
|
||||
#include <imx94-power.h>
|
||||
|
||||
#define IMX94_CLK_FLEXSPI1 IMX94_CLK_XSPI1
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMX95
|
||||
#define IMX_PLAT 95
|
||||
#include <imx95-clock.h>
|
||||
#include <imx95-power.h>
|
||||
|
||||
#define IMX95_PD_M70 IMX95_PD_M7
|
||||
#endif
|
||||
|
||||
#define IMX_PLAT_STR__(plat) # plat
|
||||
#define IMX_PLAT_STR_(IMX_PLAT) IMX_PLAT_STR__(IMX_PLAT)
|
||||
#define IMX_PLAT_STR IMX_PLAT_STR_(IMX_PLAT)
|
||||
|
||||
#define SCMI_CLK__(plat, clk) IMX ## plat ## _CLK_ ## clk
|
||||
#define SCMI_CLK_(plat, clk) SCMI_CLK__(plat, clk)
|
||||
#define SCMI_CLK(clk) SCMI_CLK_(IMX_PLAT, clk)
|
||||
|
||||
#define SCMI_PD__(plat, pd) IMX ## plat ## _PD_ ## pd
|
||||
#define SCMI_PD_(plat, pd) SCMI_PD__(plat, pd)
|
||||
#define SCMI_PD(pd) SCMI_PD_(IMX_PLAT, pd)
|
||||
|
||||
#define SCMI_CPU__(plat) MXC_CPU_IMX ## plat
|
||||
#define SCMI_CPU_(plat) SCMI_CPU__(plat)
|
||||
#define SCMI_CPU SCMI_CPU_(IMX_PLAT)
|
||||
|
||||
#endif
|
||||
@ -17,8 +17,11 @@
|
||||
#include <env_internal.h>
|
||||
#include <fuse.h>
|
||||
#include <imx_thermal.h>
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include <scmi_agent.h>
|
||||
#include <scmi_nxp_protocols.h>
|
||||
#include "common.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
@ -174,7 +177,7 @@ u32 get_cpu_rev(void)
|
||||
{
|
||||
u32 rev = (gd->arch.soc_rev >> 24) - 0xa0;
|
||||
|
||||
return (MXC_CPU_IMX95 << 12) | (CHIP_REV_1_0 + rev);
|
||||
return (SCMI_CPU << 12) | (CHIP_REV_1_0 + rev);
|
||||
}
|
||||
|
||||
#define UNLOCK_WORD 0xD928C520
|
||||
@ -254,6 +257,30 @@ static struct mm_region imx9_mem_map[] = {
|
||||
PTE_BLOCK_OUTER_SHARE
|
||||
}, {
|
||||
#endif
|
||||
/* PCIE2 ECAM */
|
||||
.virt = 0x880000000UL,
|
||||
.phys = 0x880000000UL,
|
||||
.size = 0x10000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
}, {
|
||||
/* PCIE1 Outbound */
|
||||
.virt = 0x900000000UL,
|
||||
.phys = 0x900000000UL,
|
||||
.size = 0x100000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
}, {
|
||||
/* PCIE2 Outbound */
|
||||
.virt = 0xA00000000UL,
|
||||
.phys = 0xA00000000UL,
|
||||
.size = 0x100000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
}, {
|
||||
/* empty entry to split table entry 5 if needed when TEEs are used */
|
||||
0,
|
||||
}, {
|
||||
@ -435,12 +462,16 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
|
||||
{
|
||||
u32 val[2] = {};
|
||||
int ret, num_of_macs;
|
||||
u32 bank = 40;
|
||||
|
||||
ret = fuse_read(40, 5, &val[0]);
|
||||
if (is_imx94())
|
||||
bank = 66;
|
||||
|
||||
ret = fuse_read(bank, 5, &val[0]);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
ret = fuse_read(40, 6, &val[1]);
|
||||
ret = fuse_read(bank, 6, &val[1]);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
@ -456,10 +487,32 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
|
||||
mac[3] = (val[0] >> 24) & 0xff;
|
||||
mac[4] = val[1] & 0xff;
|
||||
mac[5] = (val[1] >> 8) & 0xff;
|
||||
if (dev_id == 1)
|
||||
mac[5] = mac[5] + 3;
|
||||
if (dev_id == 2)
|
||||
mac[5] = mac[5] + 6;
|
||||
|
||||
if (is_imx94()) {
|
||||
/*
|
||||
* i.MX94 uses the following mac address offset list:
|
||||
* | No. | Module | Mac address user |
|
||||
* |--------|-------------|---------------------------|
|
||||
* | 0 ~ 1 | ethercat | port0/port1 |
|
||||
* | 2 | netc switch | internal enetc3 mac/swp0 |
|
||||
* | 3 ~ 6 | | enetc3 vf1~3/swp1 |
|
||||
* | 7 | enetc mac | enetc0 pf |
|
||||
* | 8 | | enetc1 pf |
|
||||
* | 9 | | enetc2 pf |
|
||||
* | 10 | netc switch | swp2 |
|
||||
*/
|
||||
if (dev_id == 0)
|
||||
mac[5] = mac[5] + 2; /* enetc3 mac/swp0 */
|
||||
if (dev_id == 1)
|
||||
mac[5] = mac[5] + 8; /* enetc1 */
|
||||
if (dev_id == 2)
|
||||
mac[5] = mac[5] + 9; /* enetc2 */
|
||||
} else {
|
||||
if (dev_id == 1)
|
||||
mac[5] = mac[5] + 3;
|
||||
if (dev_id == 2)
|
||||
mac[5] = mac[5] + 6;
|
||||
}
|
||||
|
||||
debug("%s: MAC%d: %pM\n", __func__, dev_id, mac);
|
||||
return;
|
||||
@ -468,11 +521,149 @@ err:
|
||||
printf("%s: fuse read err: %d\n", __func__, ret);
|
||||
}
|
||||
|
||||
static char *rst_string[32] = {
|
||||
"cm33_lockup",
|
||||
"cm33_swreq",
|
||||
"cm7_lockup",
|
||||
"cm7_swreq",
|
||||
"fccu",
|
||||
"jtag_sw",
|
||||
"ele",
|
||||
"tempsense",
|
||||
"wdog1",
|
||||
"wdog2",
|
||||
"wdog3",
|
||||
"wdog4",
|
||||
"wdog5",
|
||||
"jtag",
|
||||
"cm33_exc",
|
||||
"bbm",
|
||||
"sw",
|
||||
"sm_err", "fusa_sreco", "pmic", "unused", "unused", "unused",
|
||||
"unused", "unused", "unused", "unused", "unused", "unused",
|
||||
"unused", "unused",
|
||||
"por"
|
||||
};
|
||||
|
||||
static char *rst_string_imx94[32] = {
|
||||
"cm33_lockup",
|
||||
"cm33_swreq",
|
||||
"cm70_lockup",
|
||||
"cm70_swreq",
|
||||
"fccu",
|
||||
"jtag_sw",
|
||||
"ele",
|
||||
"tempsense",
|
||||
"wdog1",
|
||||
"wdog2",
|
||||
"wdog3",
|
||||
"wdog4",
|
||||
"wdog5",
|
||||
"jtag",
|
||||
"wdog6",
|
||||
"wdog7",
|
||||
"wdog8",
|
||||
"wo_netc", "cm33s_lockup", "cm33s_swreq", "cm71_lockup", "cm71_swreq", "cm33_exc",
|
||||
"bbm", "sw", "sm_err", "fusa_sreco", "pmic", "unused",
|
||||
"unused", "unused",
|
||||
"por"
|
||||
};
|
||||
|
||||
int get_reset_reason(bool sys, bool lm)
|
||||
{
|
||||
struct scmi_imx_misc_reset_reason_in in = {
|
||||
.flags = MISC_REASON_FLAG_SYSTEM,
|
||||
};
|
||||
|
||||
struct scmi_imx_misc_reset_reason_out out = { 0 };
|
||||
struct scmi_msg msg = {
|
||||
.protocol_id = SCMI_PROTOCOL_ID_IMX_MISC,
|
||||
.message_id = SCMI_IMX_MISC_RESET_REASON,
|
||||
.in_msg = (u8 *)&in,
|
||||
.in_msg_sz = sizeof(in),
|
||||
.out_msg = (u8 *)&out,
|
||||
.out_msg_sz = sizeof(out),
|
||||
};
|
||||
int ret;
|
||||
|
||||
struct udevice *dev;
|
||||
char **rst;
|
||||
|
||||
if (is_imx94())
|
||||
rst = rst_string_imx94;
|
||||
else
|
||||
rst = rst_string;
|
||||
|
||||
ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (sys) {
|
||||
ret = devm_scmi_process_msg(dev, &msg);
|
||||
if (out.status) {
|
||||
printf("%s:%d for SYS\n", __func__, out.status);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (out.bootflags & MISC_BOOT_FLAG_VLD) {
|
||||
printf("SYS Boot reason: %s, origin: %ld, errid: %ld\n",
|
||||
rst[out.bootflags & MISC_BOOT_FLAG_REASON],
|
||||
out.bootflags & MISC_BOOT_FLAG_ORG_VLD ?
|
||||
FIELD_GET(MISC_BOOT_FLAG_ORIGIN, out.bootflags) : -1,
|
||||
out.bootflags & MISC_BOOT_FLAG_ERR_VLD ?
|
||||
FIELD_GET(MISC_BOOT_FLAG_ERR_ID, out.bootflags) : -1
|
||||
);
|
||||
}
|
||||
if (out.shutdownflags & MISC_SHUTDOWN_FLAG_VLD) {
|
||||
printf("SYS shutdown reason: %s, origin: %ld, errid: %ld\n",
|
||||
rst[out.bootflags & MISC_SHUTDOWN_FLAG_REASON],
|
||||
out.bootflags & MISC_SHUTDOWN_FLAG_ORG_VLD ?
|
||||
FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.bootflags) : -1,
|
||||
out.bootflags & MISC_SHUTDOWN_FLAG_ERR_VLD ?
|
||||
FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.bootflags) : -1
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
if (lm) {
|
||||
in.flags = 0;
|
||||
memset(&out, 0, sizeof(struct scmi_imx_misc_reset_reason_out));
|
||||
|
||||
ret = devm_scmi_process_msg(dev, &msg);
|
||||
if (out.status) {
|
||||
printf("%s:%d for LM\n", __func__, out.status);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (out.bootflags & MISC_BOOT_FLAG_VLD) {
|
||||
printf("LM Boot reason: %s, origin: %ld, errid: %ld\n",
|
||||
rst[out.bootflags & MISC_BOOT_FLAG_REASON],
|
||||
out.bootflags & MISC_BOOT_FLAG_ORG_VLD ?
|
||||
FIELD_GET(MISC_BOOT_FLAG_ORIGIN, out.bootflags) : -1,
|
||||
out.bootflags & MISC_BOOT_FLAG_ERR_VLD ?
|
||||
FIELD_GET(MISC_BOOT_FLAG_ERR_ID, out.bootflags) : -1
|
||||
);
|
||||
}
|
||||
|
||||
if (out.shutdownflags & MISC_SHUTDOWN_FLAG_VLD) {
|
||||
printf("LM shutdown reason: %s, origin: %ld, errid: %ld\n",
|
||||
rst[out.bootflags & MISC_SHUTDOWN_FLAG_REASON],
|
||||
out.bootflags & MISC_SHUTDOWN_FLAG_ORG_VLD ?
|
||||
FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.bootflags) : -1,
|
||||
out.bootflags & MISC_SHUTDOWN_FLAG_ERR_VLD ?
|
||||
FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.bootflags) : -1
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const char *get_imx_type(u32 imxtype)
|
||||
{
|
||||
switch (imxtype) {
|
||||
case MXC_CPU_IMX95:
|
||||
return "95";/* iMX95 FULL */
|
||||
case SCMI_CPU:
|
||||
return IMX_PLAT_STR;
|
||||
default:
|
||||
return "??";
|
||||
}
|
||||
@ -553,6 +744,10 @@ int arch_cpu_init(void)
|
||||
gpio_reset(GPIO3_BASE_ADDR);
|
||||
gpio_reset(GPIO4_BASE_ADDR);
|
||||
gpio_reset(GPIO5_BASE_ADDR);
|
||||
#ifdef CONFIG_IMX94
|
||||
gpio_reset(GPIO6_BASE_ADDR);
|
||||
gpio_reset(GPIO7_BASE_ADDR);
|
||||
#endif
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
@ -218,6 +218,11 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
|
||||
u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
|
||||
MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
|
||||
|
||||
if (bootindex != K3_PRIMARY_BOOTMODE) {
|
||||
pr_alert("Fallback to backup bootmode MMCSD_MODE_FS\n");
|
||||
return MMCSD_MODE_FS;
|
||||
}
|
||||
|
||||
switch (bootmode) {
|
||||
case BOOT_DEVICE_EMMC:
|
||||
if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT))
|
||||
|
||||
@ -264,6 +264,11 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
|
||||
u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
|
||||
MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
|
||||
|
||||
if (bootindex != K3_PRIMARY_BOOTMODE) {
|
||||
pr_alert("Fallback to backup bootmode MMCSD_MODE_FS\n");
|
||||
return MMCSD_MODE_FS;
|
||||
}
|
||||
|
||||
switch (bootmode) {
|
||||
case BOOT_DEVICE_EMMC:
|
||||
if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT))
|
||||
|
||||
@ -294,15 +294,6 @@ void board_init_f(ulong dummy)
|
||||
}
|
||||
spl_enable_cache();
|
||||
|
||||
if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) &&
|
||||
spl_boot_device() == BOOT_DEVICE_ETHERNET) {
|
||||
struct udevice *cpswdev;
|
||||
|
||||
if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss),
|
||||
&cpswdev))
|
||||
printf("Failed to probe am65_cpsw_nuss driver\n");
|
||||
}
|
||||
|
||||
fixup_a53_cpu_freq_by_speed_grade();
|
||||
}
|
||||
|
||||
@ -314,6 +305,11 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
|
||||
u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
|
||||
MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
|
||||
|
||||
if (bootindex != K3_PRIMARY_BOOTMODE) {
|
||||
pr_alert("Fallback to backup bootmode MMCSD_MODE_FS\n");
|
||||
return MMCSD_MODE_FS;
|
||||
}
|
||||
|
||||
switch (bootmode) {
|
||||
case BOOT_DEVICE_EMMC:
|
||||
if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT))
|
||||
|
||||
@ -263,13 +263,6 @@ void board_init_f(ulong dummy)
|
||||
if (ret)
|
||||
panic("DRAM init failed: %d\n", ret);
|
||||
#endif
|
||||
if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) &&
|
||||
spl_boot_device() == BOOT_DEVICE_ETHERNET) {
|
||||
struct udevice *cpswdev;
|
||||
|
||||
if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss), &cpswdev))
|
||||
printf("Failed to probe am65_cpsw_nuss driver\n");
|
||||
}
|
||||
}
|
||||
|
||||
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
|
||||
|
||||
@ -103,3 +103,39 @@ u32 get_boot_device(void)
|
||||
|
||||
return bootmedia;
|
||||
}
|
||||
|
||||
const char *get_reset_reason(void)
|
||||
{
|
||||
u32 reset_reason = readl(CTRLMMR_MCU_RST_SRC);
|
||||
|
||||
/* After reading reset source register, software must clear it */
|
||||
if (reset_reason)
|
||||
writel(reset_reason, CTRLMMR_MCU_RST_SRC);
|
||||
|
||||
if (reset_reason == 0 ||
|
||||
(reset_reason & (RST_SRC_SW_MAIN_POR_FROM_MAIN |
|
||||
RST_SRC_SW_MAIN_POR_FROM_MCU)))
|
||||
return "POR";
|
||||
|
||||
if (reset_reason & (RST_SRC_SAFETY_ERR | RST_SRC_MAIN_ESM_ERR))
|
||||
return "ESM";
|
||||
|
||||
if (reset_reason & (RST_SRC_SW_MAIN_WARM_FROM_MAIN |
|
||||
RST_SRC_SW_MAIN_WARM_FROM_MCU |
|
||||
RST_SRC_SW_MCU_WARM_RST))
|
||||
return "RST";
|
||||
|
||||
if (reset_reason & (RST_SRC_SMS_WARM_RST | RST_SRC_SMS_COLD_RST))
|
||||
return "DMSC";
|
||||
|
||||
if (reset_reason & RST_SRC_DEBUG_RST)
|
||||
return "JTAG";
|
||||
|
||||
if (reset_reason & RST_SRC_THERMAL_RST)
|
||||
return "THERMAL";
|
||||
|
||||
if (reset_reason & (RST_SRC_MAIN_RESET_PIN | RST_SRC_MCU_RESET_PIN))
|
||||
return "PIN";
|
||||
|
||||
return "UNKNOWN";
|
||||
}
|
||||
|
||||
@ -322,17 +322,6 @@ void spl_board_prepare_for_linux(void)
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS)) {
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
||||
DM_DRIVER_GET(am65_cpsw_nuss),
|
||||
&dev);
|
||||
if (ret)
|
||||
printf("Failed to probe am65_cpsw_nuss driver\n");
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_TI_ICSSG_PRUETH)) {
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
@ -140,7 +140,9 @@ int fdt_fixup_reserved(void *blob, const char *name,
|
||||
return -EINVAL;
|
||||
if (!strncmp(node_name, name, strlen(name))) {
|
||||
/* Read out old size first */
|
||||
addr = fdtdec_get_addr_size(blob, subnode, "reg", &size);
|
||||
addr = fdtdec_get_addr_size_auto_parent(
|
||||
blob, nodeoffset, subnode, "reg", 0, &size,
|
||||
false);
|
||||
if (addr == FDT_ADDR_T_NONE)
|
||||
return -EINVAL;
|
||||
new_size = size;
|
||||
|
||||
@ -46,6 +46,24 @@
|
||||
/* Use Last 2K as Scratch pad */
|
||||
#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x7019f800
|
||||
|
||||
/* Reset Reason Detection */
|
||||
#define CTRLMMR_MCU_RST_SRC (MCU_CTRL_MMR0_BASE + 0x18178)
|
||||
|
||||
/* Reset causes by bit mapping */
|
||||
#define RST_SRC_SAFETY_ERR BIT(31)
|
||||
#define RST_SRC_MAIN_ESM_ERR BIT(30)
|
||||
#define RST_SRC_SW_MAIN_POR_FROM_MAIN BIT(25)
|
||||
#define RST_SRC_SW_MAIN_POR_FROM_MCU BIT(24)
|
||||
#define RST_SRC_SW_MAIN_WARM_FROM_MAIN BIT(21)
|
||||
#define RST_SRC_SW_MAIN_WARM_FROM_MCU BIT(20)
|
||||
#define RST_SRC_SW_MCU_WARM_RST BIT(16)
|
||||
#define RST_SRC_SMS_WARM_RST BIT(13)
|
||||
#define RST_SRC_SMS_COLD_RST BIT(12)
|
||||
#define RST_SRC_DEBUG_RST BIT(8)
|
||||
#define RST_SRC_THERMAL_RST BIT(4)
|
||||
#define RST_SRC_MAIN_RESET_PIN BIT(2)
|
||||
#define RST_SRC_MCU_RESET_PIN BIT(0)
|
||||
|
||||
#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__)
|
||||
|
||||
#define AM64X_DEV_RTI8 127
|
||||
|
||||
@ -12,6 +12,7 @@
|
||||
#define BOOT_DEVICE_OSPI 0x01
|
||||
#define BOOT_DEVICE_QSPI 0x02
|
||||
#define BOOT_DEVICE_SPI 0x03
|
||||
#define BOOT_DEVICE_CPGMAC 0x04
|
||||
#define BOOT_DEVICE_ETHERNET 0x04
|
||||
#define BOOT_DEVICE_I2C 0x06
|
||||
#define BOOT_DEVICE_UART 0x07
|
||||
|
||||
@ -44,4 +44,6 @@
|
||||
#define K3_PRIMARY_BOOTMODE 0x0
|
||||
#define K3_BACKUP_BOOTMODE 0x1
|
||||
|
||||
#define BOOT_DEVICE_CPGMAC 0x04
|
||||
|
||||
#endif
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
* This file is auto generated. Please do not hand edit and report any issues
|
||||
* to Bryan Brattlof <bb@ti.com>.
|
||||
*
|
||||
* Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
@ -62,6 +62,17 @@ static const char * const clkout0_ctrl_out0_parents[] = {
|
||||
"hsdiv4_16fft_main_2_hsdivout1_clk10",
|
||||
};
|
||||
|
||||
static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
|
||||
"postdiv4_16ff_main_2_hsdivout5_clk",
|
||||
"postdiv4_16ff_main_0_hsdivout6_clk",
|
||||
"board_0_cp_gemac_cpts0_rft_clk_out",
|
||||
NULL,
|
||||
"board_0_mcu_ext_refclk0_out",
|
||||
"board_0_ext_refclk1_out",
|
||||
NULL,
|
||||
"sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
|
||||
};
|
||||
|
||||
static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
|
||||
"postdiv4_16ff_main_0_hsdivout5_clk",
|
||||
"hsdiv4_16fft_main_2_hsdivout2_clk",
|
||||
@ -99,8 +110,8 @@ static const char * const main_timerclkn_sel_out0_parents[] = {
|
||||
"board_0_cp_gemac_cpts0_rft_clk_out",
|
||||
"hsdiv4_16fft_main_1_hsdivout3_clk",
|
||||
"postdiv4_16ff_main_2_hsdivout6_clk",
|
||||
NULL,
|
||||
NULL,
|
||||
"cpsw_3guss_am67_main_0_cpts_genf0",
|
||||
"cpsw_3guss_am67_main_0_cpts_genf1",
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
@ -148,7 +159,12 @@ static const struct clk_data clk_list[] = {
|
||||
CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_tck_out", 0, 0),
|
||||
CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0),
|
||||
CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0),
|
||||
CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0),
|
||||
CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0),
|
||||
CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
|
||||
CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
|
||||
@ -201,6 +217,7 @@ static const struct clk_data clk_list[] = {
|
||||
CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
|
||||
CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
|
||||
CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
|
||||
CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
|
||||
CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
|
||||
CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
|
||||
CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
|
||||
@ -216,6 +233,24 @@ static const struct clk_data clk_list[] = {
|
||||
};
|
||||
|
||||
static const struct dev_clk soc_dev_clk_data[] = {
|
||||
DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
|
||||
DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
|
||||
DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
|
||||
DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
|
||||
DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
|
||||
DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
|
||||
DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(13, 19, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(13, 20, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(13, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(13, 22, "board_0_rmii1_ref_clk_out"),
|
||||
DEV_CLK(13, 23, "board_0_rmii2_ref_clk_out"),
|
||||
DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
|
||||
DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
|
||||
DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
|
||||
@ -240,6 +275,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
|
||||
DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"),
|
||||
DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"),
|
||||
DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"),
|
||||
DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"),
|
||||
DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"),
|
||||
DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"),
|
||||
DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"),
|
||||
@ -286,6 +323,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
|
||||
DEV_CLK(157, 40, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(157, 54, "mshsi2c_main_0_porscl"),
|
||||
DEV_CLK(157, 91, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
|
||||
DEV_CLK(157, 96, "cpsw_3guss_am67_main_0_mdio_mdclk_o"),
|
||||
DEV_CLK(157, 101, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
|
||||
DEV_CLK(157, 103, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
|
||||
DEV_CLK(157, 143, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
* This file is auto generated. Please do not hand edit and report any issues
|
||||
* to Bryan Brattlof <bb@ti.com>.
|
||||
*
|
||||
* Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include "k3-dev.h"
|
||||
@ -31,11 +31,12 @@ static struct ti_lpsc soc_lpsc_list[] = {
|
||||
[6] = PSC_LPSC(24, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
|
||||
[7] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
|
||||
[8] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
|
||||
[9] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[8]),
|
||||
[10] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[9]),
|
||||
[11] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]),
|
||||
[12] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]),
|
||||
[13] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]),
|
||||
[9] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
|
||||
[10] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[8]),
|
||||
[11] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[10]),
|
||||
[12] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]),
|
||||
[13] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]),
|
||||
[14] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[13]),
|
||||
};
|
||||
|
||||
static struct ti_dev soc_dev_list[] = {
|
||||
@ -52,11 +53,12 @@ static struct ti_dev soc_dev_list[] = {
|
||||
PSC_DEV(36, &soc_lpsc_list[8]),
|
||||
PSC_DEV(102, &soc_lpsc_list[8]),
|
||||
PSC_DEV(146, &soc_lpsc_list[8]),
|
||||
PSC_DEV(166, &soc_lpsc_list[9]),
|
||||
PSC_DEV(135, &soc_lpsc_list[10]),
|
||||
PSC_DEV(170, &soc_lpsc_list[11]),
|
||||
PSC_DEV(177, &soc_lpsc_list[12]),
|
||||
PSC_DEV(55, &soc_lpsc_list[13]),
|
||||
PSC_DEV(13, &soc_lpsc_list[9]),
|
||||
PSC_DEV(166, &soc_lpsc_list[10]),
|
||||
PSC_DEV(135, &soc_lpsc_list[11]),
|
||||
PSC_DEV(170, &soc_lpsc_list[12]),
|
||||
PSC_DEV(177, &soc_lpsc_list[13]),
|
||||
PSC_DEV(55, &soc_lpsc_list[14]),
|
||||
};
|
||||
|
||||
const struct ti_k3_pd_platdata am62px_pd_platdata = {
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
* This file is auto generated. Please do not hand edit and report any issues
|
||||
* to Dave Gerlach <d-gerlach@ti.com>.
|
||||
*
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
@ -55,6 +55,32 @@ static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = {
|
||||
"hsdiv4_16fft_mcu_2_hsdivout4_clk",
|
||||
};
|
||||
|
||||
static const char * const wkup_gpio0_clksel_out0_parents[] = {
|
||||
"k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
|
||||
"k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
|
||||
"j7am_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
|
||||
"j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
|
||||
};
|
||||
|
||||
static const char * const cpsw2g_cpts_rclk_sel_out0_parents[] = {
|
||||
"hsdiv4_16fft_main_3_hsdivout1_clk",
|
||||
"postdiv3_16fft_main_0_hsdivout6_clk",
|
||||
"board_0_mcu_cpts0_rft_clk_out",
|
||||
"board_0_cpts0_rft_clk_out",
|
||||
"board_0_mcu_ext_refclk0_out",
|
||||
"board_0_ext_refclk1_out",
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
"hsdiv4_16fft_mcu_2_hsdivout1_clk",
|
||||
"k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
|
||||
};
|
||||
|
||||
static const char * const mcu_usart_clksel_out0_parents[] = {
|
||||
"hsdiv4_16fft_mcu_1_hsdivout3_clk",
|
||||
"postdiv3_16fft_main_1_hsdivout5_clk",
|
||||
@ -174,7 +200,11 @@ static const struct clk_data clk_list[] = {
|
||||
CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_mcu_rgmii1_rxc_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_mcu_rmii1_ref_clk_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
|
||||
CLK_FIXED_RATE("cpsw_2guss_mcu_0_mdio_mdclk_o", 0, 0),
|
||||
CLK_FIXED_RATE("cpsw_2guss_mcu_0_rgmii1_txc_o", 0, 0),
|
||||
CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
|
||||
CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
|
||||
CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
|
||||
@ -199,6 +229,8 @@ static const struct clk_data clk_list[] = {
|
||||
CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0),
|
||||
CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
|
||||
CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0),
|
||||
CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0),
|
||||
CLK_MUX("cpsw2g_cpts_rclk_sel_out0", cpsw2g_cpts_rclk_sel_out0_parents, 16, 0x40f08050, 8, 4, 0),
|
||||
CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
|
||||
CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0),
|
||||
CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
|
||||
@ -275,6 +307,24 @@ static const struct dev_clk soc_dev_clk_data[] = {
|
||||
DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
|
||||
DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
|
||||
DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(29, 3, "cpsw2g_cpts_rclk_sel_out0"),
|
||||
DEV_CLK(29, 4, "hsdiv4_16fft_main_3_hsdivout1_clk"),
|
||||
DEV_CLK(29, 5, "postdiv3_16fft_main_0_hsdivout6_clk"),
|
||||
DEV_CLK(29, 6, "board_0_mcu_cpts0_rft_clk_out"),
|
||||
DEV_CLK(29, 7, "board_0_cpts0_rft_clk_out"),
|
||||
DEV_CLK(29, 8, "board_0_mcu_ext_refclk0_out"),
|
||||
DEV_CLK(29, 9, "board_0_ext_refclk1_out"),
|
||||
DEV_CLK(29, 18, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
|
||||
DEV_CLK(29, 19, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(29, 20, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
|
||||
DEV_CLK(29, 21, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
|
||||
DEV_CLK(29, 22, "board_0_mcu_rgmii1_rxc_out"),
|
||||
DEV_CLK(29, 26, "board_0_mcu_rmii1_ref_clk_out"),
|
||||
DEV_CLK(29, 28, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(29, 29, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
|
||||
DEV_CLK(29, 30, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
|
||||
DEV_CLK(29, 32, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
|
||||
DEV_CLK(29, 33, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
|
||||
DEV_CLK(43, 0, "postdiv3_16fft_main_0_hsdivout8_clk"),
|
||||
DEV_CLK(43, 1, "hsdiv4_16fft_main_0_hsdivout3_clk"),
|
||||
DEV_CLK(43, 2, "gluelogic_hfosc0_clkout"),
|
||||
@ -367,6 +417,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
|
||||
DEV_CLK(157, 187, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
|
||||
DEV_CLK(157, 194, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
|
||||
DEV_CLK(157, 197, "j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck_n"),
|
||||
DEV_CLK(157, 207, "cpsw_2guss_mcu_0_mdio_mdclk_o"),
|
||||
DEV_CLK(157, 208, "j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck_n"),
|
||||
DEV_CLK(157, 214, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
|
||||
DEV_CLK(157, 221, "mcu_clkout_mux_out0"),
|
||||
@ -374,6 +425,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
|
||||
DEV_CLK(157, 223, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
|
||||
DEV_CLK(157, 225, "emmc8ss_16ffc_main_0_emmcss_io_clk"),
|
||||
DEV_CLK(157, 231, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
|
||||
DEV_CLK(157, 244, "cpsw_2guss_mcu_0_rgmii1_txc_o"),
|
||||
DEV_CLK(157, 352, "dpi0_ext_clksel_out0"),
|
||||
DEV_CLK(180, 0, "gluelogic_hfosc0_clkout"),
|
||||
DEV_CLK(180, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
|
||||
@ -400,7 +452,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
|
||||
|
||||
const struct ti_k3_clk_platdata j721s2_clk_platdata = {
|
||||
.clk_list = clk_list,
|
||||
.clk_list_cnt = 105,
|
||||
.clk_list_cnt = ARRAY_SIZE(clk_list),
|
||||
.soc_dev_clk_data = soc_dev_clk_data,
|
||||
.soc_dev_clk_data_cnt = 124,
|
||||
.soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data),
|
||||
};
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
* This file is auto generated. Please do not hand edit and report any issues
|
||||
* to Dave Gerlach <d-gerlach@ti.com>.
|
||||
*
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include "k3-dev.h"
|
||||
@ -47,6 +47,7 @@ static struct ti_lpsc soc_lpsc_list[] = {
|
||||
};
|
||||
|
||||
static struct ti_dev soc_dev_list[] = {
|
||||
PSC_DEV(29, &soc_lpsc_list[0]),
|
||||
PSC_DEV(35, &soc_lpsc_list[0]),
|
||||
PSC_DEV(108, &soc_lpsc_list[0]),
|
||||
PSC_DEV(109, &soc_lpsc_list[0]),
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
* This file is auto generated. Please do not hand edit and report any issues
|
||||
* to Bryan Brattlof <bb@ti.com>.
|
||||
*
|
||||
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
@ -57,9 +57,15 @@ static const char * const clkout0_ctrl_out0_parents[] = {
|
||||
"hsdiv4_16fft_main_2_hsdivout1_clk",
|
||||
};
|
||||
|
||||
static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
|
||||
"postdiv4_16ff_main_0_hsdivout5_clk",
|
||||
"hsdiv4_16fft_main_2_hsdivout2_clk",
|
||||
static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
|
||||
"postdiv4_16ff_main_2_hsdivout5_clk",
|
||||
"postdiv4_16ff_main_0_hsdivout6_clk",
|
||||
"board_0_cp_gemac_cpts0_rft_clk_out",
|
||||
NULL,
|
||||
"board_0_mcu_ext_refclk0_out",
|
||||
"board_0_ext_refclk1_out",
|
||||
NULL,
|
||||
"sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
|
||||
};
|
||||
|
||||
static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
|
||||
@ -94,8 +100,8 @@ static const char * const main_timerclkn_sel_out0_parents[] = {
|
||||
"board_0_cp_gemac_cpts0_rft_clk_out",
|
||||
"hsdiv4_16fft_main_1_hsdivout3_clk",
|
||||
"postdiv4_16ff_main_2_hsdivout6_clk",
|
||||
NULL,
|
||||
NULL,
|
||||
"cpsw_3guss_am67_main_0_cpts_genf0",
|
||||
"cpsw_3guss_am67_main_0_cpts_genf1",
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
@ -143,7 +149,12 @@ static const struct clk_data clk_list[] = {
|
||||
CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_tck_out", 0, 0),
|
||||
CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0),
|
||||
CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0),
|
||||
CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0),
|
||||
CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0),
|
||||
CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
|
||||
CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
|
||||
@ -194,7 +205,7 @@ static const struct clk_data clk_list[] = {
|
||||
CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
|
||||
CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
|
||||
CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
|
||||
CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
|
||||
CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
|
||||
CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
|
||||
CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
|
||||
CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0),
|
||||
@ -209,6 +220,24 @@ static const struct clk_data clk_list[] = {
|
||||
};
|
||||
|
||||
static const struct dev_clk soc_dev_clk_data[] = {
|
||||
DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
|
||||
DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
|
||||
DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
|
||||
DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
|
||||
DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
|
||||
DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
|
||||
DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(13, 19, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(13, 20, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(13, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(13, 22, "board_0_rmii1_ref_clk_out"),
|
||||
DEV_CLK(13, 23, "board_0_rmii2_ref_clk_out"),
|
||||
DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
|
||||
DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
|
||||
DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
|
||||
@ -233,10 +262,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
|
||||
DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"),
|
||||
DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"),
|
||||
DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"),
|
||||
DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"),
|
||||
DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"),
|
||||
DEV_CLK(57, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
|
||||
DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"),
|
||||
DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"),
|
||||
DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"),
|
||||
DEV_CLK(58, 1, "board_0_mmc1_clklb_out"),
|
||||
DEV_CLK(58, 2, "board_0_mmc1_clk_out"),
|
||||
@ -279,6 +306,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
|
||||
DEV_CLK(157, 62, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(157, 74, "mshsi2c_main_0_porscl"),
|
||||
DEV_CLK(157, 135, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
|
||||
DEV_CLK(157, 140, "cpsw_3guss_am67_main_0_mdio_mdclk_o"),
|
||||
DEV_CLK(157, 143, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
|
||||
DEV_CLK(157, 145, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
|
||||
DEV_CLK(157, 157, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
* This file is auto generated. Please do not hand edit and report any issues
|
||||
* to Bryan Brattlof <bb@ti.com>.
|
||||
*
|
||||
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include "k3-dev.h"
|
||||
@ -23,16 +23,16 @@ static struct ti_pd soc_pd_list[] = {
|
||||
|
||||
static struct ti_lpsc soc_lpsc_list[] = {
|
||||
[0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL),
|
||||
[1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]),
|
||||
[2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]),
|
||||
[3] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
|
||||
[4] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
|
||||
[5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
|
||||
[6] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
|
||||
[7] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
|
||||
[8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[7]),
|
||||
[1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]),
|
||||
[2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]),
|
||||
[3] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
|
||||
[4] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
|
||||
[5] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
|
||||
[6] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
|
||||
[7] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
|
||||
[8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[6]),
|
||||
[9] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]),
|
||||
[10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[7]),
|
||||
[10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[6]),
|
||||
[11] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[10]),
|
||||
[12] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]),
|
||||
};
|
||||
@ -43,13 +43,13 @@ static struct ti_dev soc_dev_list[] = {
|
||||
PSC_DEV(61, &soc_lpsc_list[0]),
|
||||
PSC_DEV(178, &soc_lpsc_list[1]),
|
||||
PSC_DEV(179, &soc_lpsc_list[2]),
|
||||
PSC_DEV(57, &soc_lpsc_list[3]),
|
||||
PSC_DEV(58, &soc_lpsc_list[4]),
|
||||
PSC_DEV(161, &soc_lpsc_list[5]),
|
||||
PSC_DEV(75, &soc_lpsc_list[6]),
|
||||
PSC_DEV(36, &soc_lpsc_list[7]),
|
||||
PSC_DEV(102, &soc_lpsc_list[7]),
|
||||
PSC_DEV(146, &soc_lpsc_list[7]),
|
||||
PSC_DEV(58, &soc_lpsc_list[3]),
|
||||
PSC_DEV(161, &soc_lpsc_list[4]),
|
||||
PSC_DEV(75, &soc_lpsc_list[5]),
|
||||
PSC_DEV(36, &soc_lpsc_list[6]),
|
||||
PSC_DEV(102, &soc_lpsc_list[6]),
|
||||
PSC_DEV(146, &soc_lpsc_list[6]),
|
||||
PSC_DEV(13, &soc_lpsc_list[7]),
|
||||
PSC_DEV(166, &soc_lpsc_list[8]),
|
||||
PSC_DEV(135, &soc_lpsc_list[9]),
|
||||
PSC_DEV(170, &soc_lpsc_list[10]),
|
||||
|
||||
@ -57,6 +57,25 @@ static const char * const wkup_gpio0_clksel_out0_parents[] = {
|
||||
"j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
|
||||
};
|
||||
|
||||
static const char * const cpsw2g_cpts_rclk_sel_out0_parents[] = {
|
||||
"hsdiv4_16fft_main_3_hsdivout1_clk",
|
||||
"postdiv3_16fft_main_0_hsdivout6_clk",
|
||||
"board_0_mcu_cpts0_rft_clk_out",
|
||||
"board_0_cpts0_rft_clk_out",
|
||||
"board_0_mcu_ext_refclk0_out",
|
||||
"board_0_ext_refclk1_out",
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
"hsdiv4_16fft_mcu_2_hsdivout1_clk",
|
||||
"k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
|
||||
};
|
||||
|
||||
static const char * const mcu_usart_clksel_out0_parents[] = {
|
||||
"hsdiv4_16fft_mcu_1_hsdivout3_clk",
|
||||
"postdiv3_16fft_main_1_hsdivout5_clk",
|
||||
@ -132,6 +151,11 @@ static const char * const main_pll_hfosc_sel_out8_parents[] = {
|
||||
"board_0_hfosc1_clk_out",
|
||||
};
|
||||
|
||||
static const char * const mcu_clkout_mux_out0_parents[] = {
|
||||
"hsdiv4_16fft_mcu_2_hsdivout0_clk",
|
||||
"hsdiv4_16fft_mcu_2_hsdivout1_clk",
|
||||
};
|
||||
|
||||
static const char * const usb0_refclk_sel_out0_parents[] = {
|
||||
"gluelogic_hfosc0_clkout",
|
||||
"board_0_hfosc1_clk_out",
|
||||
@ -142,11 +166,6 @@ static const char * const emmcsd1_lb_clksel_out0_parents[] = {
|
||||
"board_0_mmc1_clk_out",
|
||||
};
|
||||
|
||||
static const char * const mcu_clkout_mux_out0_parents[] = {
|
||||
"hsdiv4_16fft_mcu_2_hsdivout0_clk",
|
||||
"hsdiv4_16fft_mcu_2_hsdivout1_clk",
|
||||
};
|
||||
|
||||
static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
|
||||
"main_pll_hfosc_sel_out0",
|
||||
"hsdiv4_16fft_main_0_hsdivout0_clk",
|
||||
@ -201,7 +220,11 @@ static const struct clk_data clk_list[] = {
|
||||
CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_mcu_rgmii1_rxc_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_mcu_rmii1_ref_clk_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
|
||||
CLK_FIXED_RATE("cpsw_2guss_mcu_0_mdio_mdclk_o", 0, 0),
|
||||
CLK_FIXED_RATE("cpsw_2guss_mcu_0_rgmii1_txc_o", 0, 0),
|
||||
CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
|
||||
CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
|
||||
CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
|
||||
@ -224,6 +247,7 @@ static const struct clk_data clk_list[] = {
|
||||
CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
|
||||
CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0),
|
||||
CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0),
|
||||
CLK_MUX("cpsw2g_cpts_rclk_sel_out0", cpsw2g_cpts_rclk_sel_out0_parents, 16, 0x40f08050, 8, 4, 0),
|
||||
CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
|
||||
CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0),
|
||||
CLK_MUX("wkup_usart_clksel_out0", wkup_usart_clksel_out0_parents, 2, 0x43008064, 0, 1, 0),
|
||||
@ -317,6 +341,24 @@ static const struct dev_clk soc_dev_clk_data[] = {
|
||||
DEV_CLK(61, 15, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
|
||||
DEV_CLK(61, 16, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(63, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(63, 3, "cpsw2g_cpts_rclk_sel_out0"),
|
||||
DEV_CLK(63, 4, "hsdiv4_16fft_main_3_hsdivout1_clk"),
|
||||
DEV_CLK(63, 5, "postdiv3_16fft_main_0_hsdivout6_clk"),
|
||||
DEV_CLK(63, 6, "board_0_mcu_cpts0_rft_clk_out"),
|
||||
DEV_CLK(63, 7, "board_0_cpts0_rft_clk_out"),
|
||||
DEV_CLK(63, 8, "board_0_mcu_ext_refclk0_out"),
|
||||
DEV_CLK(63, 9, "board_0_ext_refclk1_out"),
|
||||
DEV_CLK(63, 18, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
|
||||
DEV_CLK(63, 19, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(63, 20, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
|
||||
DEV_CLK(63, 21, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
|
||||
DEV_CLK(63, 22, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
|
||||
DEV_CLK(63, 24, "board_0_mcu_rgmii1_rxc_out"),
|
||||
DEV_CLK(63, 27, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
|
||||
DEV_CLK(63, 28, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
|
||||
DEV_CLK(63, 29, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
|
||||
DEV_CLK(63, 30, "board_0_mcu_rmii1_ref_clk_out"),
|
||||
DEV_CLK(78, 0, "postdiv3_16fft_main_0_hsdivout8_clk"),
|
||||
DEV_CLK(78, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
|
||||
DEV_CLK(78, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
|
||||
@ -353,10 +395,12 @@ static const struct dev_clk soc_dev_clk_data[] = {
|
||||
DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
|
||||
DEV_CLK(157, 179, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
|
||||
DEV_CLK(157, 180, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
|
||||
DEV_CLK(157, 190, "cpsw_2guss_mcu_0_mdio_mdclk_o"),
|
||||
DEV_CLK(157, 224, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
|
||||
DEV_CLK(157, 226, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
|
||||
DEV_CLK(157, 228, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
|
||||
DEV_CLK(157, 230, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
|
||||
DEV_CLK(157, 233, "cpsw_2guss_mcu_0_rgmii1_txc_o"),
|
||||
DEV_CLK(157, 239, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(157, 243, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
|
||||
DEV_CLK(157, 245, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
|
||||
|
||||
@ -54,6 +54,7 @@ static struct ti_lpsc soc_lpsc_list[] = {
|
||||
};
|
||||
|
||||
static struct ti_dev soc_dev_list[] = {
|
||||
PSC_DEV(63, &soc_lpsc_list[0]),
|
||||
PSC_DEV(35, &soc_lpsc_list[0]),
|
||||
PSC_DEV(160, &soc_lpsc_list[0]),
|
||||
PSC_DEV(161, &soc_lpsc_list[0]),
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue
Block a user