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clk: at91: remove default values for PMC_PLL_ACR

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Remove default values for PMC PLL Analog Control Register(ACR) as the
values are specific for each SoC and PLL, so load them from PLL
characteristics structure

Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
This commit is contained in:
Manikandan Muralidharan 2025-09-23 15:28:18 +05:30 committed by Eugen Hristev
parent 57d88e78a8
commit 7885969610
2 changed files with 2 additions and 7 deletions
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7
drivers/clk/at91/clk-sam9x60-pll.c
View File

@ -183,11 +183,8 @@ static int sam9x60_frac_pll_enable(struct clk *clk)
AT91_PMC_PLL_UPDT_ID_MSK,
AT91_PMC_PLL_UPDT_STUPTIM(0x3f) | pll->id);
/* Recommended value for AT91_PMC_PLL_ACR */
if (pll->characteristics->upll)
val = AT91_PMC_PLL_ACR_DEFAULT_UPLL;
else
val = AT91_PMC_PLL_ACR_DEFAULT_PLLA;
/* Load recommended value for PMC_PLL_ACR */
val = pll->characteristics->acr;
pmc_write(base, AT91_PMC_PLL_ACR, val);
if (pll->characteristics->upll) {

2
include/linux/clk/at91_pmc.h
View File

@ -45,8 +45,6 @@
#define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */
#define AT91_PMC_PLL_ACR 0x18 /* PLL Analog Control Register [for SAM9X60] */
#define AT91_PMC_PLL_ACR_DEFAULT_UPLL 0x12020010UL /* Default PLL ACR value for UPLL */
#define AT91_PMC_PLL_ACR_DEFAULT_PLLA 0x00020010UL /* Default PLL ACR value for PLLA */
#define AT91_PMC_PLL_ACR_UTMIVR (1 << 12) /* UPLL Voltage regulator Control */
#define AT91_PMC_PLL_ACR_UTMIBG (1 << 13) /* UPLL Bandgap Control */