26872 Commits

Author SHA1 Message Date
Andrew Goodbody
ebf8aaf7af mtd: rawnand: cortina_nand: Fix -ENOMEM detection
In init_nand_dma there was code to detect failure to allocate memory but
it had two problems. Firstly the 2nd clause when info->tx_desc was NULL
attempted to free info->tx_desc when it should be freeing info->rx_desc.
Secondly there was no detection of both allocations failing, arguably
the more likely scenario. Refactor the code to simplify it and just fail
as soon as either allocation fails.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-08-03 10:22:04 +02:00
Andrew Goodbody
56372f834c mtd: nand: sunxi: Free allocated memory on errors
Add kfree calls on error paths for memory that was allocated. This will
prevent memory leaks.

This issue found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-By: Michael Trimarchi <michael@amarulasolutions.com>
2025-08-03 10:20:16 +02:00
Andrew Goodbody
4003ed1c1e mtd: rawnand: stm32_fmc2: Ensure to return error code
In stm32_fmc2_nfc_probe there are 3 error returns that do not set the
error code before returning which could lead to the error being silently
ignored. Just return -EINVAL in each case.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-08-03 10:20:16 +02:00
Andrew Goodbody
42ef9a0b7f mtd: nand: pxa3xx: Free memory on error
In pxa3xx_nand_probe_dt if the function detects an error after
allocating memory that memory is not freed before exit. Add the
appropriate free.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: MIchael Trimarchi <michael@amarulasolutions.com>
2025-08-03 10:20:16 +02:00
Siddharth Vadapalli
5a4bfe3877 net: phy: Support overriding Auto Negotiation timeout with env variable
The Auto Negotiation procedure between two Ethernet PHYs consists of
determining the best commonly supported parameters among Speed,
Duplex Mode and Flow Control.

The time taken for this procedure is not only dependent on the local
PHY used, but also on the link-partner PHY.

While a timeout can be specified in the form of a "CONFIG" on the basis
of the local PHY present on the device, since the timeout also depends
on the link-partner PHY, it might be necessary to modify the timeout.

To avoid rebuilding the bootloader for a given device, just because it
may be connected to various link-partner PHYs, each with a different
timeout, introduce an environment variable named "phy_aneg_timeout" and
override "CONFIG_PHY_ANEG_TIMEOUT" with "phy_aneg_timeout".

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
[jf: add missing #include <env.h>]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-08-01 10:42:22 +02:00
Christian Speich
d1b4bfc984 virtio: net: Add missing virtqueue_kick in free_pkt
Every virtqueue_add must eventually be followed by virtqueue_kick for to
properly notify the peer that new buffers have been put into the queue.

This is currently missing for virtio-net and may result in non-working
network when the host has depleted the rx buffers and waits for new
buffers. Depending on the host it may busy poll on the virtio queue or
wait for the kick. Qemu does the latter and may break.

Signed-off-by: Christian Speich <c.speich@avm.de>
2025-08-01 09:30:47 +02:00
Tom Rini
3c1ac44caa arm: bcm281xx: Remove ethernet driver
As no platforms enable the ethernet driver, remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-01 09:30:47 +02:00
Tom Rini
982aac5754 net: Tighten some network driver dependencies
A large number of network drivers cannot build without access to some
platform specific header files. Express those requirements in Kconfig as
well. This covers the QUICC engine drivers as that is networking
driver infrastructure.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-01 09:30:47 +02:00
Tom Rini
5564a4be25 net: Add <cpu_func.h> to some platforms
The common portable header for CPU related functions such as cache
flushing and invalidation is <cpu_func.h> so add that to these drivers.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-01 09:30:47 +02:00
Tom Rini
3a5da11ffe drivers/net/ftgmac100.c: Fix a debug print
In the debug print in ftgmac100_send we want to say where the packet is
in memory and what the length is, so use %p to print that.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-01 09:30:47 +02:00
Tom Rini
f5e968a28e Add support for STM32 TIMERS and STM32 PWM on STM32MP25
Add STM32MP13xx SPL and OpTee-OS start support
 Fix header misuse in stm32 reset drivers
 Fix STMicroelectronics spelling
 Fix clk-stm32h7 wrong macros used in register read
 Fix PRE_CON_BUF_ADDR on STM32MP13
 Fix clock identifier passed to struct scmi_clk_parent_set_in
 Fix stm32 reset for STM32F4/F7 and H7
 Enable OF_UPSTREAM_BUILD_VENDOR for stm32mp13_defconfig
 Add STM32MP23 SoC and stm32mp235f-dk board support
 -----BEGIN PGP SIGNATURE-----
 
 iQJQBAABCgA6FiEEXyrViUccKBz9c35Jysd4L3sz/6YFAmiLMDMcHHBhdHJpY2Uu
 Y2hvdGFyZEBmb3NzLnN0LmNvbQAKCRDKx3gvezP/piEgD/4iJisKm8VxHkbD8rHQ
 XBcew6H8fgjRxm+Df9SJd1FfiGcJDr84E91VLhfmZm+MmDLdI+Zwt21teDkEiAsk
 CLQcuJnCTPl0rQ4bteZQGrPAyUr7iMz+txwFCWor9hA3Om8nKZ/qvtXTzudJWZg9
 J1tneYMBOIknC4UUXJjbwWTLDyMJus32FxBm97ylPlDzWT9vci+BdiIFRt2W/Izh
 ETow6eKQf7UFhYSYc+sAoFr1BeUZCW/O+Omo+rj5ZcbG4jTfvNFeaAB3RUCeIigX
 44O3he6AQxFscjRYmvJhtITVCJFNlLLbVBo2CR3F2rvYNdtXEFMsksTiCwSkc3Yk
 tO+hMqO3NCsDXB4kIYvIsaK2tjuhFghmbKeg17cQyrXgnSaJM4hKumf1Tf8oGZWI
 76MwETlyPmjfYGvVGTghtrqAWAFcWhPB/GnGFmboe0xhM+CfNhKGK+Rt8YzT3zbS
 HYCuSsrfbbs2lAkUc1HOovNDWpDUlCbDadhH2TgQ3TODQWwce1EL+n3Cz0hOS3vR
 qD27G2YH7Ng//vkwQjK6wbVaS08cTWQeYgxpqRxG0pV64q6fY3qXcp1E8bECf0Br
 WbfUO6DEklnnOxX/u5annOVelRVDlnxVTEXFdFwDgkgWDm5SPWETcbszhqExAXIj
 kXNZmKIvStR4vlbbsdBkVYjJdw==
 =LafX
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-stm32-20250731' of https://source.denx.de/u-boot/custodians/u-boot-stm

CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/27236

- Add support for STM32 TIMERS and STM32 PWM on STM32MP25
- Add STM32MP13xx SPL and OpTee-OS start support
- Fix header misuse in stm32 reset drivers
- Fix STMicroelectronics spelling
- Fix clk-stm32h7 wrong macros used in register read
- Fix PRE_CON_BUF_ADDR on STM32MP13
- Fix clock identifier passed to struct scmi_clk_parent_set_in
- Fix stm32 reset for STM32F4/F7 and H7
- Enable OF_UPSTREAM_BUILD_VENDOR for stm32mp13_defconfig
- Add STM32MP23 SoC and stm32mp235f-dk board support
2025-07-31 10:04:32 -06:00
Tom Rini
eef444c389 Merge tag 'u-boot-socfpga-next-20250731' of https://source.denx.de/u-boot/custodians/u-boot-socfpga
This pull request includes updates for the SoCFPGA platform intended for the 2025.10 release
cycle. The highlights focus on enabling the Power Manager for Agilex5, NAND boot support
enhancements, and various bug fixes and cleanups across SoCFPGA components.

CI:

  * https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27221

Summary of changes:

Agilex5 Power Manager:

  *   Initial driver support and DT bindings are added for the Agilex5 Power Manager, enabling
better power domain control.

NAND Boot Support for Agilex5:

  *   SPL support for NAND boot is enabled.
  *   UBI/UBIFS support is configured in defconfigs.
  *   Memory layout updates (malloc and BSS relocation) ensure proper boot behavior.

Code Quality Improvements:

  *   Coverity and runtime bug fixes (e.g., jtag_usercode check, sub-device conditionals).
  *   Several cleanup patches addressing formatting, logic, and initialization issues.

General Maintenance:

  *   SPDX license tags and header include fixes.
  *   Device tree updates to limit SPI clock frequency and other minor adjustments.

These contributions come from Alif Zakuan Yuslaimi, Andrew Goodbody, Dinesh Maniyam, Naresh
Kumar Ravulapalli, and Tingting Meng.

This patch set has been tested on Agilex 5 devkit.
2025-07-31 08:42:06 -06:00
Tom Rini
6549dbfd26 Merge patch series "Extend usb_onboard_hub driver to support Cypress HX3 hub family"
Lukasz Czechowski <lukasz.czechowski@thaumatec.com> says:

This patch series extends the usb_onboard_hub driver to allow for
support of more types of onboard hub devices, and adds the Cypress HX3
hub family.

First patch in the series updates the bind function, so that it no
longer uses hardcoded compatible strings.
Next patch simplifies the code, by removing unnecessary dm_gpio function
call.
Third patch updates the remove function, which allows the prevent issues
with usb devices reenumeration, in case of calling "usb reset". Although
the issue could still occur in case of invalid initial state of reset
gpio, it is minimized with no impact on main usb_hub driver.
Fourth patch extends the driver with support for multiple power
supplies, the same way it is done in kernel driver.  Finally, last patch
provides hub data and of_match table entries for Cypress HX3

Link: https://lore.kernel.org/r/20250722-usb_onboard_hub_cypress_hx3-v4-0-91c3ee958c0e@thaumatec.com
2025-07-30 08:20:35 -06:00
Lukasz Czechowski
480753ca92 usb: onboard-hub: Use devm API do automatically free the reset GPIO
The reset GPIO is obtained during driver probing by the function
devm_gpiod_get_optional, which means the GPIO will be automatically
freed when the device is removed. Because of this, explicit call
to free the reset GPIO in hub remove function is not needed.
To support the Managed device resources, the DEVRES config must
be enabled, otherwise the devres functions fall back to non-managed
variants. Set the necessary dependency to DEVRES in Kconfig.

Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com>
2025-07-30 07:57:17 -06:00
Patrice Chotard
e064db5fe7 reset: stm32: Fix set_clr field
STM32F4/F7 and H7 series doesn't have a clear reset register, so
set_clr field must be set to false.

Fixes: 0994a627c278 ("reset: stm32mp25: add stm32mp25 reset driver")

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-07-30 14:55:17 +02:00
Alif Zakuan Yuslaimi
9f68908686 arch: arm: agilex5: Enable power manager for Agilex5
Agilex5 FSBL is required to disable the power of unused peripheral SRAM
blocks to reduce power consumption.

Introducing a new power manager driver for Agilex5 which will be called
as part of Agilex5 SPL initialization process.

This driver will read the peripheral handoff data obtained from the
bitstream and will power off the specified peripheral's SRAM from the
handoff data values.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-07-30 17:45:31 +08:00
Andrew Goodbody
6e1cc5d861 socfpga_dtreg: Ensure reg is initialised before use
In socfpga_dtreg_probe it is possible that if mask is 0 then reg will
not be assigned to before first use. Refactor the code slightly to
ensure that reg is always assigned to and remove a piece of duplicated
code.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-30 17:45:30 +08:00
Andrew Goodbody
5a13fa7c66 ddr: altera: n5x: size_t cannot be less than 0
The function socfpga_get_handoff_size returns an int so make the struct
fields used to accept the return value also an int so that testing for
less than 0 is then valid.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-30 17:45:29 +08:00
Andrew Goodbody
dff25bb4ab clk: n5x: Fix misplaced paren
Smatch reported an issue about the precedence of shift being higher than
mask in clk_get_emac_clk_hz. This turned out to be a misplaced paren in
one of the calculations. Fix this by placing the paren in the same place
as in the other similar calculations in the same function.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-30 17:45:29 +08:00
Andrew Goodbody
f4aa24af69 arm: socfpga: Remove unnecessary for loop
The for loop in fpgamgr_program_poll_cd will always terminate after a
single pass and so is not necessary. Remove it and all related code and
leave only the code that is effective.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-30 17:45:28 +08:00
Patrice Chotard
7e1e22c70d watchdog: don't autostart watchdog on STM32MP architecture
On STM32MP reference boards, the watchdog is started by a previous
boot stage (e.g. bootrom or secure OS), so the config flag
WATCHDOG_AUTOSTART is not required.
It's preferable to rely on the DT properties "u-boot,autostart" or
"u-boot,noautostart", if needed.

For backward compatibility on defconfigs that are based on SPL,
thus cannot rely on a previous boot stage for starting the
watchdog, enable WATCHDOG_AUTOSTART in their respective defconfig.
The change in stm32mp15_dhsom.config is propagated to:
- configs/stm32mp15_dhcom_basic.config
- configs/stm32mp15_dhcor_basic.config
and then to:
- stm32mp15_dhcom_basic_defconfig
- stm32mp15_dhcom_drc02_basic_defconfig
- stm32mp15_dhcom_pdk2_basic_defconfig
- stm32mp15_dhcom_picoitx_basic_defconfig
- stm32mp15_dhcor_avenger96_basic_defconfig
- stm32mp15_dhcor_basic_defconfig
- stm32mp15_dhcor_drc_compact_basic_defconfig
- stm32mp15_dhcor_testbench_basic_defconfig

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-07-30 08:01:11 +02:00
Clément Le Goffic
4bef031d69 watchdog: stm32mp: check the watchdog status
Add a mean to check the IWDG status based on the peripheral version.
This is done by either checking the status bit ONF either by updating
the reload register with the same value and check if the reload succeed.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-07-30 08:01:11 +02:00
Antonio Borneo
6319fabe32 watchdog: arm_smc_wdt: get wdt status through SMCWD_GET_TIMELEFT
The optional SMCWD_GET_TIMELEFT command can be used to detect if
the watchdog has already been started.
See the implementation in OP-TEE secure OS [1].

At probe time, check if the watchdog is already started and then
call wdt_set_force_autostart(). This will keep U-Boot pinging the
watchdog even when the property 'u-boot,noautostart' is present.

Link: https://github.com/OP-TEE/optee_os/commit/a7f2d4bd8632 [1]

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-07-30 08:01:11 +02:00
Antonio Borneo
091303c788 watchdog: wdt-uclass.c: add wdt_set_force_autostart() helper
The watchdog could have been already started by a previous boot
stage (e.g. bootrom or secure OS). U-Boot has to start and kick
the watchdog even when CONFIG_WATCHDOG_AUTOSTART is not enabled
or when the DT property u-boot,noautostart is present.

Add the helper wdt_set_force_autostart() that can be called by the
driver's probe() when it detects that the watchdog has already
been started and is running.

Co-developed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-07-30 08:01:11 +02:00
Tom Rini
a8f20bb665 Merge patch series "bios_emulator: Fix two issues found by Smatch"
Andrew Goodbody <andrew.goodbody@linaro.org> says:

Smatch found two issues in bios_emulator, a buffer overflow and missing
parens for a macro. Fix them both.

Link: https://lore.kernel.org/r/20250723-bios_emulator-v1-0-78b9ef7b9b4a@linaro.org
2025-07-29 13:14:52 -06:00
Andrew Goodbody
0fdcca86d8 bios_emulator: Add parens to xorl macro
The xorl macro lacked surrounding parens which meant that it could have
unexpected results when used in expressions. Fix this by adding the
surrounding parens to make its use predictable.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-29 13:14:47 -06:00
Andrew Goodbody
4b8aba93bd bios_emulator: Fix buffer overflow
Using strcpy to copy a 4 character string into a 4 byte field in a
structure will overflow that field as it writes the terminating \0 into
the following field. Correct this by using memcpy instead.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-29 13:14:46 -06:00
Tom Rini
808d4bc2bd Merge tag 'u-boot-marvell-20250729' of https://source.denx.de/u-boot/custodians/u-boot-marvell
CI: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=394&view=results

- cmd: tlv_eeprom: Minor improvements (Hugo)
- kirkwood: Enable bootstd and other modernization for ib62x0 board
  (Tony)
- spi: mvebu: Correct dependencies on MVEBU_A3700_SPI (Tom)
- ddr: marvell: a38x: Fix unsigned issues detected by smatch (Andrew)
2025-07-29 09:36:59 -06:00
Patrice Chotard
fdd30ee308 ARM: stm32mp: Add STM32MP23 support
Add STM32MP23 support which is a cost optimized of STM32MP25.
More details available at:
https://www.st.com/en/microcontrollers-microprocessors/stm32mp2-series.html

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-07-29 17:02:31 +02:00
Andrew Goodbody
8693fe92ac clk: stm32: Wrong macros used in register read
Smatch reported a warning about a shift macro being used as a mask. Make
the obvious changes to make this register read calculation work the same
as the previous ones.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-07-29 17:02:31 +02:00
Alice Guo
52b7ad7bec clk: scmi: Fix clock identifier passed to struct scmi_clk_parent_set_in
Commit aa7bdc1af505 ("clk: scmi: manage properly the clk identifier with
CFF") enables CONFIG_CLK_AUTO_ID, so need to use clk_get_id() to get the
real SCMI CLK ID, otherwise wrong ID is used when set clk parent.

Fixes: aa7bdc1af505 ("clk: scmi: manage properly the clk identifier with
CCF")

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-07-29 17:02:31 +02:00
Marek Vasut
f91bb6d1df reset: stm32: Fix header misuse
The stm32-reset-core.h is located in drivers/reset/stm32/ , it has to
be included using "stm32-reset-core.h" and not <stm32-reset-core.h> ,
otherwise the build fails. Fix it.

Fixes: 0994a627c278 ("reset: stm32mp25: add stm32mp25 reset driver")
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-07-29 17:02:31 +02:00
Cheick Traore
3f14dc91ab pwm: stm32: add support for stm32mp25
Add support for STM32MP25 SoC.
IPIDR register is used to check the hardware configuration register
when available to gather the number of complementary outputs.

Signed-off-by: Cheick Traore <cheick.traore@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-07-29 16:44:58 +02:00
Tom Rini
0662dae4df Second set of u-boot-at91 features for the 2025.10 cycle
-----BEGIN PGP SIGNATURE-----
 
 iQFNBAABCgA3FiEEqxhEmNJ6d7ZdeFLIHrMeAg6sL8gFAmiDRqMZHGV1Z2VuLmhy
 aXN0ZXZAbGluYXJvLm9yZwAKCRAesx4CDqwvyDCNB/45njdX2R6wvdoOFxLYShDX
 /9p2v7S5O3CAI9LDV9cmL2Je6vQbuDpvGbNx6563WWra79YpzuSJrBV/u9U1Ye/A
 N3OM32IdTj1qosOQUH7RV53ljUmy46a9iZDzt9LzpJzEB/aUiC/Ntm1E05wz1SxF
 xq3oL8KB6a2JlCMD26g1do3rCQYcDZ+bCO26rX/PBylNrCImLfl/LBe2wbqTmI3I
 78cuRT06KlPtF0XKUFndykTvxuKZ3TADbsO/EinftxKgL9DfaKyjsnCNfaOn6yYX
 vh1Pz2iPRjjo2M/3vWrQzZBni5obpQB3JZ+H+EUy2wwYSxaYvQxG8lTgVArQECH5
 =uuIk
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-at91-2025.10-b' of https://source.denx.de/u-boot/custodians/u-boot-at91

Second set of u-boot-at91 features for the 2025.10 cycle:

This feature set includes the addition of new sama7d65 SoC and a new
board named sama7d65-curiosity.
2025-07-29 07:55:49 -06:00
Andrew Goodbody
b35ddfc57a ddr: marvell: a38x: Fix unsigned issues
Cannot test an unsigned variable to be less than 0, it will always fail.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Stefan Roese <stefan.roese@mailbox.org>
2025-07-29 08:44:18 +02:00
Tom Rini
c8114a01ad spi: mvebu: Correct dependencies on MVEBU_A3700_SPI
A dependency exposed by "make allyesconfig" is that the logic around
this symbol was not quite correct. It needs to depend on ARCH_MVEBU and
ARM64 and then select CLK_MVEBU.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2025-07-29 08:44:18 +02:00
Andre Przywara
1063678a70 power: regulator: add AXP323 support
The X-Powers AXP323 is very close sibling to the AXP313A, only that it
adds support for dual-phasing the first two DC/DC converters.

We do not really care about this particular feature, so just add the new
compatible string and tie it to the existing AXP313A support code.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-07-27 22:57:35 +01:00
Andre Przywara
869d396191 sunxi: mmc: add support for Allwinner A523 MMC mod clock
The Allwinner A523 SoC has a slightly changed mod clock, where the P
factor, formerly a shift value, is now a second divider value.
Also the input clock is not PLL_PERIPH0 (600MHz) anymore, but
PLL_PERIPH0_400M (for MMC0/1), so adjust the input rate calculation
accordingly. MMC2 has a different set of parents, so the input clock
is 800 MHz there.
Adjust for all of this.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-07-27 22:57:35 +01:00
Andre Przywara
14c66b9e35 pinctrl: sunxi: add Allwinner A523 pinctrl description
The new DT pinctrl binding would allow us to read the pinmux values from
the DT, but it is actually easier to just continue with hardcoding the
mux values in the driver, and matching them against the "function" name.

Add the values for the primary and secondary pin controller on the A523.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-07-27 22:57:35 +01:00
Andre Przywara
d508d995d1 clk: sunxi: Add support for the A523 -R CCU
Add a clock driver for the PRCM clock controller on the Allwinner A523
family of SoCs, often also used with an "r" prefix or suffix.
This just describes the clock gates and reset lines for the few devices
that we would need, most prominently the R_I2C device for the PMIC.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-07-27 22:57:35 +01:00
Andre Przywara
1d0b1d46cc clk: sunxi: Add support for the A523 CCU
Add a clock driver for the main clock controller on the Allwinner A523
family of SoCs.
As usual, this just describes the clock gates and reset lines for the
few device that U-Boot cares about: USB, Ethernet, MMC, I2C, SPI.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-07-27 22:57:35 +01:00
Simon Glass
0029f2447b efi: Rename CONFIG_EFI to CONFIG_EFI_CLIENT
The generic name 'EFI' would be more useful for common EFI features. At
present it just refers to the EFI app and stub, which is confusing.

Rename it to EFI_CLIENT

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-07-26 07:34:28 +02:00
Tom Rini
088d24eb96 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-samsung
- Enhanced e850-96 support
2025-07-25 07:50:44 -06:00
Ryan Wanner
8dff5dd290 clk: at91: sama7d65: add clock support
Add clock support for SAMA7D65

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
[romain.sioen@microchip.com: add Fractional PLL core
output range]
Signed-off-by: Romain Sioen <romain.sioen@microchip.com>
[varshini.rajendran@microchip.com: adapt driver to upstream]
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
2025-07-25 11:54:43 +03:00
Ryan Wanner
eff0e49d1c clk: at91: Update MAX PLL and master clk ID
Update the MAX PLL and master CLK ID to support sama7d65
SoC family.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
2025-07-25 11:54:43 +03:00
Sam Protsenko
ba713dd7d4 usb: dwc3-generic: Add Exynos850 support
The only thing needed from DWC3 glue layer for Exynos850 is to enable
USB clocks. The generic glue layer driver already does that. Add
Exynos850 dwc3 compatible string to enable support for this chip.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-07-25 10:17:21 +09:00
Sam Protsenko
80c1606d13 phy: samsung: Add Exynos USB DRD PHY driver
Add DM driver for Exynos USB PHY controllers. For now it only supports
Exynos850 SoC. Only UTMI+ (USB 2.0) PHY interface is implemented, as
Exynos850 doesn't support USB 3.0. Only two clocks are used for this
controller:
  - phy: bus clock, used for PHY registers access
  - ref: PHY reference clock (OSCCLK)

Ported from Linux kernel: drivers/phy/samsung/phy-exynos5-usbdrd.c

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-07-25 10:17:21 +09:00
Tom Rini
021783860f Merge tag 'u-boot-imx-master-20250724' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27149

- Add support for the NXP imx93 frdm board.
- imx93_evk and phycore-imx93 cleanups.
- Convert imx6dl-sielaff to OF_UPSTREAM and fix serial download mode boot.
- Fix crash in imx power-domain.
- Migrate Phytec imx8mm boards to standard boot.
- Fix smatch warnings.
2025-07-24 15:31:17 -06:00
Tom Rini
896f570d56 Merge patch series "Add support for K3 BIST"
Neha Malcom Francis <n-francis@ti.com> says:

This series implements a driver for the BIST (Built-In Self Test) module
for K3 devices. The BIST driver must ideally support triggering of BIST
tests, both PBIST (Memory BIST) and LBIST (Logic BIST) on a core. Both
tests are destructive in nature. Please see links [1] and [2] for
further information regarding the two.

At boot up, BIST is executed by hardware for the MCU domain
automatically as part of HW POST. So BIST has been checked only for the
MCU domain when U-Boot comes up in the usual U-Boot to Linux boot flow.
To facilitate the use-case where some safe firmware is intended to be
run on a safe core, it is best to have triggered the BIST tests on that
core. As an example, we take triggering the BIST tests on the MAIN R52_x
cores. The triggering patch is kept as DONOTMERGE.

The general procedure for triggering BIST on a core is:
	1. Power on the core under test following a sequence
	2. Trigger the BIST test
	3. Reset the core under test following a sequence

BIST tests are triggered from A72 SPL where the DM (Device Manager
firmware that handles power management) is already up and can perform
these power sequences for us.

Boot logs (with LOG_DEBUG and CONFIG_K3_BIST enabled) and DT node kept (already
merged to ti-k3-dts-next [3]):
https://gist.github.com/nehamalcom/3fed504d038b54e3e05ba3874d73d603

[1] https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/pbist.html#introduction
[2] https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/lbist.html#introduction
[3] https://lore.kernel.org/all/175205725858.918402.3771835070085533874.b4-ty@ti.com/

Link: https://lore.kernel.org/r/20250716062156.2564297-1-n-francis@ti.com
2025-07-24 13:30:20 -06:00
Andrew Goodbody
5c0827eede sandbox: eth-raw: Prevent possible buffer overflow
Instead of strcpy which is unbounded use strlcpy to ensure that the
receiving buffer cannot be overflowed.

This issue found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-24 13:30:20 -06:00