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clk: stm32: Wrong macros used in register read

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Smatch reported a warning about a shift macro being used as a mask. Make
the obvious changes to make this register read calculation work the same
as the previous ones.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
This commit is contained in:
Andrew Goodbody 2025-07-24 12:37:38 +01:00 committed by Patrice Chotard
parent 52b7ad7bec
commit 8693fe92ac
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/stm32/clk-stm32h7.c
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@ -549,8 +549,8 @@ static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs,
divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK;
divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1;
fracn1 = readl(&regs->pll1fracr) & RCC_PLL1DIVR_DIVR1_MASK;
fracn1 = fracn1 & RCC_PLL1DIVR_DIVR1_SHIFT;
fracn1 = readl(&regs->pll1fracr) & RCC_PLL1FRACR_FRACN1_MASK;
fracn1 = (fracn1 >> RCC_PLL1FRACR_FRACN1_SHIFT) + 1;
vco = (pllsrc / divm1) * divn1;
rate = (pllsrc * fracn1) / (divm1 * 8192);