mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2025-08-06 07:17:01 +02:00
Add support for STM32 TIMERS and STM32 PWM on STM32MP25
Add STM32MP13xx SPL and OpTee-OS start support Fix header misuse in stm32 reset drivers Fix STMicroelectronics spelling Fix clk-stm32h7 wrong macros used in register read Fix PRE_CON_BUF_ADDR on STM32MP13 Fix clock identifier passed to struct scmi_clk_parent_set_in Fix stm32 reset for STM32F4/F7 and H7 Enable OF_UPSTREAM_BUILD_VENDOR for stm32mp13_defconfig Add STM32MP23 SoC and stm32mp235f-dk board support -----BEGIN PGP SIGNATURE----- iQJQBAABCgA6FiEEXyrViUccKBz9c35Jysd4L3sz/6YFAmiLMDMcHHBhdHJpY2Uu Y2hvdGFyZEBmb3NzLnN0LmNvbQAKCRDKx3gvezP/piEgD/4iJisKm8VxHkbD8rHQ XBcew6H8fgjRxm+Df9SJd1FfiGcJDr84E91VLhfmZm+MmDLdI+Zwt21teDkEiAsk CLQcuJnCTPl0rQ4bteZQGrPAyUr7iMz+txwFCWor9hA3Om8nKZ/qvtXTzudJWZg9 J1tneYMBOIknC4UUXJjbwWTLDyMJus32FxBm97ylPlDzWT9vci+BdiIFRt2W/Izh ETow6eKQf7UFhYSYc+sAoFr1BeUZCW/O+Omo+rj5ZcbG4jTfvNFeaAB3RUCeIigX 44O3he6AQxFscjRYmvJhtITVCJFNlLLbVBo2CR3F2rvYNdtXEFMsksTiCwSkc3Yk tO+hMqO3NCsDXB4kIYvIsaK2tjuhFghmbKeg17cQyrXgnSaJM4hKumf1Tf8oGZWI 76MwETlyPmjfYGvVGTghtrqAWAFcWhPB/GnGFmboe0xhM+CfNhKGK+Rt8YzT3zbS HYCuSsrfbbs2lAkUc1HOovNDWpDUlCbDadhH2TgQ3TODQWwce1EL+n3Cz0hOS3vR qD27G2YH7Ng//vkwQjK6wbVaS08cTWQeYgxpqRxG0pV64q6fY3qXcp1E8bECf0Br WbfUO6DEklnnOxX/u5annOVelRVDlnxVTEXFdFwDgkgWDm5SPWETcbszhqExAXIj kXNZmKIvStR4vlbbsdBkVYjJdw== =LafX -----END PGP SIGNATURE----- Merge tag 'u-boot-stm32-20250731' of https://source.denx.de/u-boot/custodians/u-boot-stm CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/27236 - Add support for STM32 TIMERS and STM32 PWM on STM32MP25 - Add STM32MP13xx SPL and OpTee-OS start support - Fix header misuse in stm32 reset drivers - Fix STMicroelectronics spelling - Fix clk-stm32h7 wrong macros used in register read - Fix PRE_CON_BUF_ADDR on STM32MP13 - Fix clock identifier passed to struct scmi_clk_parent_set_in - Fix stm32 reset for STM32F4/F7 and H7 - Enable OF_UPSTREAM_BUILD_VENDOR for stm32mp13_defconfig - Add STM32MP23 SoC and stm32mp235f-dk board support
This commit is contained in:
Tom Rini
commit
f5e968a28e
@ -732,7 +732,6 @@ F: include/dt-bindings/clock/stm32fx-clock.h
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F: include/dt-bindings/clock/stm32mp*
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F: include/dt-bindings/pinctrl/stm32-pinfunc.h
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F: include/dt-bindings/reset/stm32mp*
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F: include/stm32-reset-core.h
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F: include/stm32_rcc.h
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F: tools/logos/st.bmp
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F: tools/stm32image.c
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187
arch/arm/dts/stm32mp1-ddr.dtsi
Normal file
187
arch/arm/dts/stm32mp1-ddr.dtsi
Normal file
@ -0,0 +1,187 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
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/*
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* Copyright : STMicroelectronics 2018-2025
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*/
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#include <linux/stringify.h>
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#ifdef CONFIG_SPL
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&ddr {
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config-DDR_MEM_COMPATIBLE {
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bootph-all;
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compatible = __stringify(st,DDR_MEM_COMPATIBLE);
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st,mem-name = DDR_MEM_NAME;
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st,mem-speed = <DDR_MEM_SPEED>;
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st,mem-size = <DDR_MEM_SIZE>;
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st,ctl-reg = <
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DDR_MSTR
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DDR_MRCTRL0
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DDR_MRCTRL1
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DDR_DERATEEN
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DDR_DERATEINT
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DDR_PWRCTL
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DDR_PWRTMG
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DDR_HWLPCTL
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DDR_RFSHCTL0
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DDR_RFSHCTL3
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DDR_CRCPARCTL0
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DDR_ZQCTL0
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DDR_DFITMG0
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DDR_DFITMG1
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DDR_DFILPCFG0
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DDR_DFIUPD0
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DDR_DFIUPD1
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DDR_DFIUPD2
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DDR_DFIPHYMSTR
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DDR_ODTMAP
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DDR_DBG0
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DDR_DBG1
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DDR_DBGCMD
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DDR_POISONCFG
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DDR_PCCFG
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>;
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st,ctl-timing = <
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DDR_RFSHTMG
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DDR_DRAMTMG0
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DDR_DRAMTMG1
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DDR_DRAMTMG2
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DDR_DRAMTMG3
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DDR_DRAMTMG4
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DDR_DRAMTMG5
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DDR_DRAMTMG6
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DDR_DRAMTMG7
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DDR_DRAMTMG8
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DDR_DRAMTMG14
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DDR_ODTCFG
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>;
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st,ctl-map = <
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DDR_ADDRMAP1
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DDR_ADDRMAP2
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DDR_ADDRMAP3
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DDR_ADDRMAP4
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DDR_ADDRMAP5
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DDR_ADDRMAP6
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DDR_ADDRMAP9
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DDR_ADDRMAP10
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DDR_ADDRMAP11
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>;
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/*
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* Both st,ctl-perf and st,phy-reg differ
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* between STM32MP13xx and STM32MP15xx due
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* to 16bit and 32bit DRAM bus respectively
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* on these SoCs.
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*/
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st,phy-timing = <
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DDR_PTR0
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DDR_PTR1
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DDR_PTR2
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DDR_DTPR0
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DDR_DTPR1
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DDR_DTPR2
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DDR_MR0
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DDR_MR1
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DDR_MR2
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DDR_MR3
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>;
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status = "okay";
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};
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};
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#endif
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#undef DDR_MEM_COMPATIBLE
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#undef DDR_MEM_NAME
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#undef DDR_MEM_SPEED
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#undef DDR_MEM_SIZE
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#undef DDR_MSTR
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#undef DDR_MRCTRL0
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#undef DDR_MRCTRL1
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#undef DDR_DERATEEN
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#undef DDR_DERATEINT
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#undef DDR_PWRCTL
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#undef DDR_PWRTMG
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#undef DDR_HWLPCTL
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#undef DDR_RFSHCTL0
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#undef DDR_RFSHCTL3
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#undef DDR_RFSHTMG
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#undef DDR_CRCPARCTL0
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#undef DDR_DRAMTMG0
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#undef DDR_DRAMTMG1
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#undef DDR_DRAMTMG2
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#undef DDR_DRAMTMG3
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#undef DDR_DRAMTMG4
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#undef DDR_DRAMTMG5
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#undef DDR_DRAMTMG6
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#undef DDR_DRAMTMG7
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#undef DDR_DRAMTMG8
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#undef DDR_DRAMTMG14
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#undef DDR_ZQCTL0
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#undef DDR_DFITMG0
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#undef DDR_DFITMG1
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#undef DDR_DFILPCFG0
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#undef DDR_DFIUPD0
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#undef DDR_DFIUPD1
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#undef DDR_DFIUPD2
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#undef DDR_DFIPHYMSTR
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#undef DDR_ADDRMAP1
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#undef DDR_ADDRMAP2
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#undef DDR_ADDRMAP3
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#undef DDR_ADDRMAP4
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#undef DDR_ADDRMAP5
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#undef DDR_ADDRMAP6
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#undef DDR_ADDRMAP9
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#undef DDR_ADDRMAP10
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#undef DDR_ADDRMAP11
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#undef DDR_ODTCFG
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#undef DDR_ODTMAP
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#undef DDR_SCHED
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#undef DDR_SCHED1
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#undef DDR_PERFHPR1
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#undef DDR_PERFLPR1
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#undef DDR_PERFWR1
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#undef DDR_DBG0
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#undef DDR_DBG1
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#undef DDR_DBGCMD
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#undef DDR_POISONCFG
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#undef DDR_PCCFG
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#undef DDR_PCFGR_0
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#undef DDR_PCFGW_0
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#undef DDR_PCFGQOS0_0
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#undef DDR_PCFGQOS1_0
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#undef DDR_PCFGWQOS0_0
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#undef DDR_PCFGWQOS1_0
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#undef DDR_PCFGR_1
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#undef DDR_PCFGW_1
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#undef DDR_PCFGQOS0_1
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#undef DDR_PCFGQOS1_1
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#undef DDR_PCFGWQOS0_1
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#undef DDR_PCFGWQOS1_1
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#undef DDR_PGCR
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#undef DDR_PTR0
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#undef DDR_PTR1
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#undef DDR_PTR2
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#undef DDR_ACIOCR
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#undef DDR_DXCCR
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#undef DDR_DSGCR
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#undef DDR_DCR
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#undef DDR_DTPR0
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#undef DDR_DTPR1
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#undef DDR_DTPR2
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#undef DDR_MR0
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#undef DDR_MR1
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#undef DDR_MR2
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#undef DDR_MR3
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#undef DDR_ODTCR
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#undef DDR_ZQ0CR1
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#undef DDR_DX0GCR
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#undef DDR_DX1GCR
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#undef DDR_DX2GCR
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#undef DDR_DX3GCR
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49
arch/arm/dts/stm32mp13-ddr.dtsi
Normal file
49
arch/arm/dts/stm32mp13-ddr.dtsi
Normal file
@ -0,0 +1,49 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
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/*
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* Copyright : STMicroelectronics 2018-2025
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*/
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#ifdef CONFIG_SPL
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&ddr {
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clocks = <&rcc AXIDCG>,
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<&rcc DDRC1>,
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<&rcc DDRPHYC>,
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<&rcc DDRCAPB>,
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<&rcc DDRPHYCAPB>;
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clock-names = "axidcg",
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"ddrc1",
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"ddrphyc",
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"ddrcapb",
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"ddrphycapb";
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config-DDR_MEM_COMPATIBLE {
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st,ctl-perf = <
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DDR_SCHED
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DDR_SCHED1
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DDR_PERFHPR1
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DDR_PERFLPR1
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DDR_PERFWR1
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DDR_PCFGR_0
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DDR_PCFGW_0
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DDR_PCFGQOS0_0
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DDR_PCFGQOS1_0
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DDR_PCFGWQOS0_0
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DDR_PCFGWQOS1_0
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>;
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st,phy-reg = <
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DDR_PGCR
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DDR_ACIOCR
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DDR_DXCCR
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DDR_DSGCR
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DDR_DCR
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DDR_ODTCR
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DDR_ZQ0CR1
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DDR_DX0GCR
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DDR_DX1GCR
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>;
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};
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};
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#endif
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#include "stm32mp1-ddr.dtsi"
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100
arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi
Normal file
100
arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi
Normal file
@ -0,0 +1,100 @@
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2025, DH electronics - All Rights Reserved
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*
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* STM32MP13xx DHSOM configuration
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* 1x DDR3L 1Gb, 16-bit, 533MHz, Single Die Package in flyby topology.
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* Reference used W631GU6MB15I from Winbond
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*
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* DDR type / Platform DDR3/3L
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* freq 533MHz
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* width 16
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* datasheet 0 = W631GU6MB15I / DDR3-1333
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* DDR density 2
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* timing mode optimized
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* address mapping : RBC
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* Tc > + 85C : J
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*/
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#define DDR_MEM_COMPATIBLE ddr3l-dhsom-1066-888-bin-g-1x2gb-533mhz
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#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz"
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#define DDR_MEM_SPEED 533000
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#define DDR_MEM_SIZE 0x20000000
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#define DDR_MSTR 0x00040401
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#define DDR_MRCTRL0 0x00000010
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#define DDR_MRCTRL1 0x00000000
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#define DDR_DERATEEN 0x00000000
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#define DDR_DERATEINT 0x00800000
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#define DDR_PWRCTL 0x00000000
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#define DDR_PWRTMG 0x00400010
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#define DDR_HWLPCTL 0x00000000
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#define DDR_RFSHCTL0 0x00210000
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#define DDR_RFSHCTL3 0x00000000
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#define DDR_RFSHTMG 0x0081008B
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#define DDR_CRCPARCTL0 0x00000000
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#define DDR_DRAMTMG0 0x121B2414
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#define DDR_DRAMTMG1 0x000A041B
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#define DDR_DRAMTMG2 0x0607080F
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#define DDR_DRAMTMG3 0x0050400C
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#define DDR_DRAMTMG4 0x07040607
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#define DDR_DRAMTMG5 0x06060403
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#define DDR_DRAMTMG6 0x02020002
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#define DDR_DRAMTMG7 0x00000202
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#define DDR_DRAMTMG8 0x00001005
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#define DDR_DRAMTMG14 0x000000A0
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#define DDR_ZQCTL0 0xC2000040
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#define DDR_DFITMG0 0x02050105
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#define DDR_DFITMG1 0x00000202
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#define DDR_DFILPCFG0 0x07000000
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#define DDR_DFIUPD0 0xC0400003
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#define DDR_DFIUPD1 0x00000000
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#define DDR_DFIUPD2 0x00000000
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#define DDR_DFIPHYMSTR 0x00000000
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#define DDR_ADDRMAP1 0x00080808
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#define DDR_ADDRMAP2 0x00000000
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#define DDR_ADDRMAP3 0x00000000
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#define DDR_ADDRMAP4 0x00001F1F
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#define DDR_ADDRMAP5 0x07070707
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#define DDR_ADDRMAP6 0x0F070707
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#define DDR_ADDRMAP9 0x00000000
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#define DDR_ADDRMAP10 0x00000000
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#define DDR_ADDRMAP11 0x00000000
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#define DDR_ODTCFG 0x06000600
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#define DDR_ODTMAP 0x00000001
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#define DDR_SCHED 0x00000F01
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#define DDR_SCHED1 0x00000000
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#define DDR_PERFHPR1 0x00000001
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#define DDR_PERFLPR1 0x04000200
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#define DDR_PERFWR1 0x08000400
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#define DDR_DBG0 0x00000000
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#define DDR_DBG1 0x00000000
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#define DDR_DBGCMD 0x00000000
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#define DDR_POISONCFG 0x00000000
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#define DDR_PCCFG 0x00000010
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#define DDR_PCFGR_0 0x00000000
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#define DDR_PCFGW_0 0x00000000
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#define DDR_PCFGQOS0_0 0x00100009
|
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#define DDR_PCFGQOS1_0 0x00000020
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#define DDR_PCFGWQOS0_0 0x01100B03
|
||||
#define DDR_PCFGWQOS1_0 0x01000200
|
||||
#define DDR_PGCR 0x01442E02
|
||||
#define DDR_PTR0 0x0022AA5B
|
||||
#define DDR_PTR1 0x04841104
|
||||
#define DDR_PTR2 0x042DA068
|
||||
#define DDR_ACIOCR 0x10400812
|
||||
#define DDR_DXCCR 0x00000C40
|
||||
#define DDR_DSGCR 0xF200011F
|
||||
#define DDR_DCR 0x0000000B
|
||||
#define DDR_DTPR0 0x36D477D0
|
||||
#define DDR_DTPR1 0x098B00D8
|
||||
#define DDR_DTPR2 0x10023600
|
||||
#define DDR_MR0 0x00000830
|
||||
#define DDR_MR1 0x00000000
|
||||
#define DDR_MR2 0x00000208
|
||||
#define DDR_MR3 0x00000000
|
||||
#define DDR_ODTCR 0x00010000
|
||||
#define DDR_ZQ0CR1 0x00000038
|
||||
#define DDR_DX0GCR 0x0000CE81
|
||||
#define DDR_DX1GCR 0x0000CE81
|
||||
|
||||
#include "stm32mp13-ddr.dtsi"
|
||||
@ -17,6 +17,7 @@
|
||||
pinctrl0 = &pinctrl;
|
||||
};
|
||||
|
||||
#if defined(CONFIG_TFABOOT)
|
||||
firmware {
|
||||
optee {
|
||||
bootph-all;
|
||||
@ -27,6 +28,86 @@
|
||||
psci {
|
||||
bootph-some-ram;
|
||||
};
|
||||
#else
|
||||
binman: binman {
|
||||
multiple-images;
|
||||
|
||||
spl-stm32 {
|
||||
filename = "u-boot-spl.stm32";
|
||||
mkimage {
|
||||
args = "-T stm32imagev2 -a 0x2ffe0000 -e 0x2ffe0000";
|
||||
u-boot-spl {
|
||||
no-write-symbols;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
bootph-all;
|
||||
|
||||
clk_hse: ck_hse {
|
||||
bootph-all;
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
clk_hsi: ck_hsi {
|
||||
bootph-all;
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <64000000>;
|
||||
};
|
||||
|
||||
clk_lse: ck_lse {
|
||||
bootph-all;
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
clk_lsi: ck_lsi {
|
||||
bootph-all;
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32000>;
|
||||
};
|
||||
|
||||
clk_csi: ck_csi {
|
||||
bootph-all;
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <4000000>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu0_opp_table: cpu0-opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
bootph-pre-ram;
|
||||
opp-650000000 {
|
||||
bootph-pre-ram;
|
||||
opp-hz = /bits/ 64 <650000000>;
|
||||
opp-microvolt = <1200000>;
|
||||
opp-supported-hw = <0x1>;
|
||||
};
|
||||
opp-1000000000 {
|
||||
bootph-pre-ram;
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-microvolt = <1350000>;
|
||||
opp-supported-hw = <0x2>;
|
||||
};
|
||||
};
|
||||
|
||||
reboot {
|
||||
bootph-all;
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&rcc>;
|
||||
offset = <0x114>;
|
||||
mask = <0x1>;
|
||||
};
|
||||
#endif
|
||||
|
||||
soc {
|
||||
bootph-all;
|
||||
@ -52,6 +133,14 @@
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
#if !defined(CONFIG_TFABOOT)
|
||||
&cpu0 {
|
||||
nvmem-cells = <&part_number_otp>;
|
||||
nvmem-cell-names = "part_number";
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
};
|
||||
#endif
|
||||
|
||||
&gpioa {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
@ -3,7 +3,9 @@
|
||||
* Copyright (C) 2024 Marek Vasut <marex@denx.de>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/stm32mp13-clksrc.h>
|
||||
#include "stm32mp13-u-boot.dtsi"
|
||||
#include "stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
@ -18,8 +20,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
&etzpc {
|
||||
compatible = "simple-bus";
|
||||
};
|
||||
|
||||
&flash0 {
|
||||
bootph-pre-ram;
|
||||
bootph-all;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
@ -48,6 +54,138 @@
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3_pins_a>;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&qspi_clk_pins_a {
|
||||
bootph-all;
|
||||
pins {
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
&qspi_bk1_pins_a {
|
||||
bootph-all;
|
||||
pins {
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
&qspi_cs1_pins_a {
|
||||
bootph-all;
|
||||
pins {
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
bootph-all;
|
||||
i2c3_pins_a: i2c3-0 {
|
||||
bootph-all;
|
||||
pins {
|
||||
bootph-all;
|
||||
pinmux = <STM32_PINMUX('B', 8, AF5)>, /* I2C3_SCL */
|
||||
<STM32_PINMUX('H', 14, AF4)>; /* I2C3_SDA */
|
||||
bias-disable;
|
||||
drive-open-drain;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#if !defined(CONFIG_TFABOOT)
|
||||
&rcc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, <&clk_lse>, <&clk_lsi>;
|
||||
|
||||
st,clksrc = <
|
||||
CLK_MPU_PLL1P
|
||||
CLK_AXI_PLL2P
|
||||
CLK_MLAHBS_PLL3
|
||||
CLK_PLL12_HSE
|
||||
CLK_PLL3_HSE
|
||||
CLK_PLL4_HSE
|
||||
CLK_CKPER_HSE
|
||||
CLK_RTC_LSE
|
||||
CLK_MCO1_LSI
|
||||
CLK_MCO2_HSI
|
||||
>;
|
||||
|
||||
st,clkdiv = <
|
||||
0 /*AXI*/
|
||||
0 /*MLHAB*/
|
||||
1 /*APB1*/
|
||||
1 /*APB2*/
|
||||
1 /*APB3*/
|
||||
1 /*APB4*/
|
||||
2 /*APB5*/
|
||||
1 /*APB6*/
|
||||
0 /*RTC*/
|
||||
>;
|
||||
|
||||
st,pkcs = <
|
||||
CLK_I2C12_HSI
|
||||
CLK_I2C3_HSI
|
||||
CLK_QSPI_PLL3R
|
||||
CLK_SAES_AXI
|
||||
CLK_SDMMC1_PLL3R
|
||||
CLK_SDMMC2_PLL3R
|
||||
CLK_STGEN_HSE
|
||||
CLK_UART2_HSI
|
||||
CLK_UART4_HSI
|
||||
CLK_USBO_USBPHY
|
||||
CLK_USBPHY_HSE
|
||||
>;
|
||||
|
||||
/*
|
||||
* cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >;
|
||||
* frac = < f >;
|
||||
*
|
||||
* PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled
|
||||
* DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN
|
||||
* m ... for PLL1,2: m=2 ; for PLL3,4: m=1
|
||||
* XTAL = 24 MHz
|
||||
*
|
||||
* VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) )
|
||||
* P = VCO / (P + 1)
|
||||
* Q = VCO / (Q + 1)
|
||||
* R = VCO / (R + 1)
|
||||
*/
|
||||
|
||||
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */
|
||||
pll2: st,pll@1 {
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <1>;
|
||||
cfg = < 2 65 1 1 0 PQR(1,1,1) >;
|
||||
frac = < 0x1400 >;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
/* VCO = 600 MHz => P = 200, Q = 150, R = 200 */
|
||||
pll3: st,pll@2 {
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <2>;
|
||||
cfg = < 2 74 2 3 2 PQR(1,1,1) >;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
/* VCO = 750.0 MHz => P = 125, Q = 83, R = 75 */
|
||||
pll4: st,pll@3 {
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <3>;
|
||||
cfg = < 3 124 5 8 9 PQR(1,1,1) >;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
&sdmmc1 {
|
||||
status = "disabled";
|
||||
};
|
||||
@ -55,3 +193,23 @@
|
||||
&usbotg_hs {
|
||||
u-boot,force-b-session-valid;
|
||||
};
|
||||
|
||||
&vddcpu {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&vdd_ddr {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&vdd {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&vddcore {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&vref_ddr {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
@ -2,8 +2,6 @@
|
||||
/*
|
||||
* Copyright : STMicroelectronics 2018
|
||||
*/
|
||||
#include <linux/stringify.h>
|
||||
|
||||
#ifdef CONFIG_SPL
|
||||
&ddr {
|
||||
clocks = <&rcc AXIDCG>,
|
||||
@ -21,69 +19,6 @@
|
||||
"ddrphycapb";
|
||||
|
||||
config-DDR_MEM_COMPATIBLE {
|
||||
bootph-all;
|
||||
|
||||
compatible = __stringify(st,DDR_MEM_COMPATIBLE);
|
||||
|
||||
st,mem-name = DDR_MEM_NAME;
|
||||
st,mem-speed = <DDR_MEM_SPEED>;
|
||||
st,mem-size = <DDR_MEM_SIZE>;
|
||||
|
||||
st,ctl-reg = <
|
||||
DDR_MSTR
|
||||
DDR_MRCTRL0
|
||||
DDR_MRCTRL1
|
||||
DDR_DERATEEN
|
||||
DDR_DERATEINT
|
||||
DDR_PWRCTL
|
||||
DDR_PWRTMG
|
||||
DDR_HWLPCTL
|
||||
DDR_RFSHCTL0
|
||||
DDR_RFSHCTL3
|
||||
DDR_CRCPARCTL0
|
||||
DDR_ZQCTL0
|
||||
DDR_DFITMG0
|
||||
DDR_DFITMG1
|
||||
DDR_DFILPCFG0
|
||||
DDR_DFIUPD0
|
||||
DDR_DFIUPD1
|
||||
DDR_DFIUPD2
|
||||
DDR_DFIPHYMSTR
|
||||
DDR_ODTMAP
|
||||
DDR_DBG0
|
||||
DDR_DBG1
|
||||
DDR_DBGCMD
|
||||
DDR_POISONCFG
|
||||
DDR_PCCFG
|
||||
>;
|
||||
|
||||
st,ctl-timing = <
|
||||
DDR_RFSHTMG
|
||||
DDR_DRAMTMG0
|
||||
DDR_DRAMTMG1
|
||||
DDR_DRAMTMG2
|
||||
DDR_DRAMTMG3
|
||||
DDR_DRAMTMG4
|
||||
DDR_DRAMTMG5
|
||||
DDR_DRAMTMG6
|
||||
DDR_DRAMTMG7
|
||||
DDR_DRAMTMG8
|
||||
DDR_DRAMTMG14
|
||||
DDR_ODTCFG
|
||||
>;
|
||||
|
||||
st,ctl-map = <
|
||||
DDR_ADDRMAP1
|
||||
DDR_ADDRMAP2
|
||||
DDR_ADDRMAP3
|
||||
DDR_ADDRMAP4
|
||||
DDR_ADDRMAP5
|
||||
DDR_ADDRMAP6
|
||||
DDR_ADDRMAP9
|
||||
DDR_ADDRMAP10
|
||||
DDR_ADDRMAP11
|
||||
>;
|
||||
|
||||
st,ctl-perf = <
|
||||
DDR_SCHED
|
||||
DDR_SCHED1
|
||||
@ -117,111 +52,8 @@
|
||||
DDR_DX2GCR
|
||||
DDR_DX3GCR
|
||||
>;
|
||||
|
||||
st,phy-timing = <
|
||||
DDR_PTR0
|
||||
DDR_PTR1
|
||||
DDR_PTR2
|
||||
DDR_DTPR0
|
||||
DDR_DTPR1
|
||||
DDR_DTPR2
|
||||
DDR_MR0
|
||||
DDR_MR1
|
||||
DDR_MR2
|
||||
DDR_MR3
|
||||
>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
#undef DDR_MEM_COMPATIBLE
|
||||
#undef DDR_MEM_NAME
|
||||
#undef DDR_MEM_SPEED
|
||||
#undef DDR_MEM_SIZE
|
||||
|
||||
#undef DDR_MSTR
|
||||
#undef DDR_MRCTRL0
|
||||
#undef DDR_MRCTRL1
|
||||
#undef DDR_DERATEEN
|
||||
#undef DDR_DERATEINT
|
||||
#undef DDR_PWRCTL
|
||||
#undef DDR_PWRTMG
|
||||
#undef DDR_HWLPCTL
|
||||
#undef DDR_RFSHCTL0
|
||||
#undef DDR_RFSHCTL3
|
||||
#undef DDR_RFSHTMG
|
||||
#undef DDR_CRCPARCTL0
|
||||
#undef DDR_DRAMTMG0
|
||||
#undef DDR_DRAMTMG1
|
||||
#undef DDR_DRAMTMG2
|
||||
#undef DDR_DRAMTMG3
|
||||
#undef DDR_DRAMTMG4
|
||||
#undef DDR_DRAMTMG5
|
||||
#undef DDR_DRAMTMG6
|
||||
#undef DDR_DRAMTMG7
|
||||
#undef DDR_DRAMTMG8
|
||||
#undef DDR_DRAMTMG14
|
||||
#undef DDR_ZQCTL0
|
||||
#undef DDR_DFITMG0
|
||||
#undef DDR_DFITMG1
|
||||
#undef DDR_DFILPCFG0
|
||||
#undef DDR_DFIUPD0
|
||||
#undef DDR_DFIUPD1
|
||||
#undef DDR_DFIUPD2
|
||||
#undef DDR_DFIPHYMSTR
|
||||
#undef DDR_ADDRMAP1
|
||||
#undef DDR_ADDRMAP2
|
||||
#undef DDR_ADDRMAP3
|
||||
#undef DDR_ADDRMAP4
|
||||
#undef DDR_ADDRMAP5
|
||||
#undef DDR_ADDRMAP6
|
||||
#undef DDR_ADDRMAP9
|
||||
#undef DDR_ADDRMAP10
|
||||
#undef DDR_ADDRMAP11
|
||||
#undef DDR_ODTCFG
|
||||
#undef DDR_ODTMAP
|
||||
#undef DDR_SCHED
|
||||
#undef DDR_SCHED1
|
||||
#undef DDR_PERFHPR1
|
||||
#undef DDR_PERFLPR1
|
||||
#undef DDR_PERFWR1
|
||||
#undef DDR_DBG0
|
||||
#undef DDR_DBG1
|
||||
#undef DDR_DBGCMD
|
||||
#undef DDR_POISONCFG
|
||||
#undef DDR_PCCFG
|
||||
#undef DDR_PCFGR_0
|
||||
#undef DDR_PCFGW_0
|
||||
#undef DDR_PCFGQOS0_0
|
||||
#undef DDR_PCFGQOS1_0
|
||||
#undef DDR_PCFGWQOS0_0
|
||||
#undef DDR_PCFGWQOS1_0
|
||||
#undef DDR_PCFGR_1
|
||||
#undef DDR_PCFGW_1
|
||||
#undef DDR_PCFGQOS0_1
|
||||
#undef DDR_PCFGQOS1_1
|
||||
#undef DDR_PCFGWQOS0_1
|
||||
#undef DDR_PCFGWQOS1_1
|
||||
#undef DDR_PGCR
|
||||
#undef DDR_PTR0
|
||||
#undef DDR_PTR1
|
||||
#undef DDR_PTR2
|
||||
#undef DDR_ACIOCR
|
||||
#undef DDR_DXCCR
|
||||
#undef DDR_DSGCR
|
||||
#undef DDR_DCR
|
||||
#undef DDR_DTPR0
|
||||
#undef DDR_DTPR1
|
||||
#undef DDR_DTPR2
|
||||
#undef DDR_MR0
|
||||
#undef DDR_MR1
|
||||
#undef DDR_MR2
|
||||
#undef DDR_MR3
|
||||
#undef DDR_ODTCR
|
||||
#undef DDR_ZQ0CR1
|
||||
#undef DDR_DX0GCR
|
||||
#undef DDR_DX1GCR
|
||||
#undef DDR_DX2GCR
|
||||
#undef DDR_DX3GCR
|
||||
#include "stm32mp1-ddr.dtsi"
|
||||
|
||||
104
arch/arm/dts/stm32mp23-u-boot.dtsi
Normal file
104
arch/arm/dts/stm32mp23-u-boot.dtsi
Normal file
@ -0,0 +1,104 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
|
||||
/*
|
||||
* Copyright : STMicroelectronics 2024
|
||||
*/
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
gpio0 = &gpioa;
|
||||
gpio1 = &gpiob;
|
||||
gpio2 = &gpioc;
|
||||
gpio3 = &gpiod;
|
||||
gpio4 = &gpioe;
|
||||
gpio5 = &gpiof;
|
||||
gpio6 = &gpiog;
|
||||
gpio7 = &gpioh;
|
||||
gpio8 = &gpioi;
|
||||
gpio25 = &gpioz;
|
||||
pinctrl0 = &pinctrl;
|
||||
pinctrl1 = &pinctrl_z;
|
||||
};
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
scmi {
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
/* need PSCI for sysreset during board_f */
|
||||
psci {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
soc@0 {
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
&bsec {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&gpioa {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&gpiob {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&gpioc {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&gpiod {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&gpioe {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&gpiof {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&gpiog {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&gpioh {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&gpioi {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&gpioz {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&rcc {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&rifsc {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&scmi_clk {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&syscfg {
|
||||
bootph-all;
|
||||
};
|
||||
27
arch/arm/dts/stm32mp235f-dk-u-boot.dtsi
Normal file
27
arch/arm/dts/stm32mp235f-dk-u-boot.dtsi
Normal file
@ -0,0 +1,27 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2024 - All Rights Reserved
|
||||
*/
|
||||
|
||||
#include "stm32mp23-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
config {
|
||||
u-boot,boot-led = "led-blue";
|
||||
u-boot,mmc-env-partition = "u-boot-env";
|
||||
};
|
||||
};
|
||||
|
||||
&usart2 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&usart2_pins_a {
|
||||
bootph-all;
|
||||
pins1 {
|
||||
bootph-all;
|
||||
};
|
||||
pins2 {
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
@ -29,7 +29,7 @@
|
||||
*
|
||||
* Currently valid part Names are (PART):
|
||||
* M_NAND - Micron NAND
|
||||
* STNOR - STMicrolelctronics M29W128GL
|
||||
* STNOR - STMicroelectronics M29W128GL
|
||||
*/
|
||||
#define GPMC_SIZE_256M 0x0
|
||||
#define GPMC_SIZE_128M 0x8
|
||||
|
||||
@ -29,7 +29,7 @@
|
||||
*
|
||||
* Currently valid part Names are (PART):
|
||||
* M_NAND - Micron NAND
|
||||
* STNOR - STMicrolelctronics M29W128GL
|
||||
* STNOR - STMicroelectronics M29W128GL
|
||||
*/
|
||||
#define GPMC_SIZE_256M 0x0
|
||||
#define GPMC_SIZE_128M 0x8
|
||||
|
||||
@ -40,16 +40,19 @@ choice
|
||||
config STM32MP13X
|
||||
bool "Support STMicroelectronics STM32MP13x Soc"
|
||||
select ARCH_EARLY_INIT_R
|
||||
select ARM_SMCCC
|
||||
select ARM_SMCCC if TFABOOT
|
||||
select ARCH_SUPPORT_PSCI if !TFABOOT
|
||||
select BINMAN if !TFABOOT
|
||||
select CPU_V7A
|
||||
select CPU_V7_HAS_NONSEC
|
||||
select CPU_V7_HAS_VIRT
|
||||
select OF_BOARD
|
||||
select OF_BOARD if TFABOOT
|
||||
select OF_BOARD_SETUP
|
||||
select PINCTRL_STM32
|
||||
select STM32_RCC
|
||||
select STM32_RESET
|
||||
select STM32_SERIAL
|
||||
select SUPPORT_SPL if !TFABOOT
|
||||
select SYS_ARCH_TIMER
|
||||
imply CMD_NVEDIT_INFO
|
||||
imply OF_UPSTREAM
|
||||
@ -81,6 +84,32 @@ config STM32MP15X
|
||||
STMicroelectronics MPU with core ARMv7
|
||||
dual core A7 for STM32MP157/3, monocore for STM32MP151
|
||||
|
||||
config STM32MP23X
|
||||
bool "Support STMicroelectronics STM32MP23x Soc"
|
||||
select ARM64
|
||||
select CLK_STM32MP25
|
||||
select OF_BOARD
|
||||
select PINCTRL_STM32
|
||||
select STM32_RCC
|
||||
select STM32_RESET
|
||||
select STM32_SERIAL
|
||||
select STM32MP_TAMP_NVMEM
|
||||
select SYS_ARCH_TIMER
|
||||
select TFABOOT
|
||||
imply CLK_SCMI
|
||||
imply CMD_NVEDIT_INFO
|
||||
imply DM_REGULATOR
|
||||
imply DM_REGULATOR_SCMI
|
||||
imply OF_UPSTREAM
|
||||
imply OPTEE
|
||||
imply RESET_SCMI
|
||||
imply SYSRESET_PSCI
|
||||
imply TEE
|
||||
imply VERSION_VARIABLE
|
||||
help
|
||||
Support of STMicroelectronics SOC STM32MP23x family
|
||||
STMicroelectronics MPU with 2 * A53 core and 1 M33 core
|
||||
|
||||
config STM32MP25X
|
||||
bool "Support STMicroelectronics STM32MP25x Soc"
|
||||
select ARM64
|
||||
@ -165,6 +194,7 @@ config MFD_STM32_TIMERS
|
||||
|
||||
source "arch/arm/mach-stm32mp/Kconfig.13x"
|
||||
source "arch/arm/mach-stm32mp/Kconfig.15x"
|
||||
source "arch/arm/mach-stm32mp/Kconfig.23x"
|
||||
source "arch/arm/mach-stm32mp/Kconfig.25x"
|
||||
source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
|
||||
|
||||
|
||||
@ -20,10 +20,11 @@ config TARGET_ST_STM32MP13X
|
||||
endchoice
|
||||
|
||||
config TEXT_BASE
|
||||
default 0xC0000000
|
||||
default 0xC0000000 if TFABOOT
|
||||
default 0xC0100000 if !TFABOOT
|
||||
|
||||
config PRE_CON_BUF_ADDR
|
||||
default 0xC0800000
|
||||
default 0xC2FFF000
|
||||
|
||||
config PRE_CON_BUF_SZ
|
||||
default 4096
|
||||
|
||||
37
arch/arm/mach-stm32mp/Kconfig.23x
Normal file
37
arch/arm/mach-stm32mp/Kconfig.23x
Normal file
@ -0,0 +1,37 @@
|
||||
if STM32MP23X
|
||||
|
||||
choice
|
||||
prompt "STM32MP23x board select"
|
||||
optional
|
||||
|
||||
config TARGET_ST_STM32MP23X
|
||||
bool "STMicroelectronics STM32MP23x boards"
|
||||
imply BOOTSTAGE
|
||||
imply CMD_BOOTSTAGE
|
||||
help
|
||||
target the STMicroelectronics board with SOC STM32MP23x
|
||||
managed by board/st/stm32mp2
|
||||
The difference between board are managed with devicetree
|
||||
|
||||
endchoice
|
||||
|
||||
config TEXT_BASE
|
||||
default 0x84000000
|
||||
|
||||
config PRE_CON_BUF_ADDR
|
||||
default 0x84800000
|
||||
|
||||
config PRE_CON_BUF_SZ
|
||||
default 4096
|
||||
|
||||
if DEBUG_UART
|
||||
|
||||
# debug on USART2 by default
|
||||
config DEBUG_UART_BASE
|
||||
default 0x400e0000
|
||||
|
||||
endif
|
||||
|
||||
source "board/st/stm32mp2/Kconfig"
|
||||
|
||||
endif
|
||||
@ -10,6 +10,7 @@ obj-y += soc.o
|
||||
|
||||
obj-$(CONFIG_STM32MP15X) += stm32mp1/
|
||||
obj-$(CONFIG_STM32MP13X) += stm32mp1/
|
||||
obj-$(CONFIG_STM32MP23X) += stm32mp2/
|
||||
obj-$(CONFIG_STM32MP25X) += stm32mp2/
|
||||
|
||||
obj-$(CONFIG_MFD_STM32_TIMERS) += timers.o
|
||||
|
||||
@ -171,7 +171,7 @@ static u8 get_key_nb(void)
|
||||
if (IS_ENABLED(CONFIG_STM32MP15X))
|
||||
return ARRAY_SIZE(stm32mp15_list);
|
||||
|
||||
if (IS_ENABLED(CONFIG_STM32MP25X))
|
||||
if (IS_ENABLED(CONFIG_STM32MP23X) || IS_ENABLED(CONFIG_STM32MP25X))
|
||||
return ARRAY_SIZE(stm32mp25_list);
|
||||
}
|
||||
|
||||
@ -183,7 +183,7 @@ static const struct stm32key *get_key(u8 index)
|
||||
if (IS_ENABLED(CONFIG_STM32MP15X))
|
||||
return &stm32mp15_list[index];
|
||||
|
||||
if (IS_ENABLED(CONFIG_STM32MP25X))
|
||||
if (IS_ENABLED(CONFIG_STM32MP23X) || IS_ENABLED(CONFIG_STM32MP25X))
|
||||
return &stm32mp25_list[index];
|
||||
}
|
||||
|
||||
@ -195,7 +195,7 @@ static u8 get_otp_close_state_nb(void)
|
||||
if (IS_ENABLED(CONFIG_STM32MP15X))
|
||||
return ARRAY_SIZE(stm32mp15_close_state_otp);
|
||||
|
||||
if (IS_ENABLED(CONFIG_STM32MP25X))
|
||||
if (IS_ENABLED(CONFIG_STM32MP23X) || IS_ENABLED(CONFIG_STM32MP25X))
|
||||
return ARRAY_SIZE(stm32mp25_close_state_otp);
|
||||
}
|
||||
|
||||
@ -207,7 +207,7 @@ static const struct otp_close *get_otp_close_state(u8 index)
|
||||
if (IS_ENABLED(CONFIG_STM32MP15X))
|
||||
return &stm32mp15_close_state_otp[index];
|
||||
|
||||
if (IS_ENABLED(CONFIG_STM32MP25X))
|
||||
if (IS_ENABLED(CONFIG_STM32MP23X) || IS_ENABLED(CONFIG_STM32MP25X))
|
||||
return &stm32mp25_close_state_otp[index];
|
||||
}
|
||||
|
||||
|
||||
@ -156,6 +156,8 @@ enum forced_boot_mode {
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32MP13X
|
||||
#define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4)
|
||||
#define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5)
|
||||
#define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(31)
|
||||
#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30)
|
||||
#endif
|
||||
@ -163,7 +165,7 @@ enum forced_boot_mode {
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* CONFIG_STM32MP15X || CONFIG_STM32MP13X */
|
||||
|
||||
#ifdef CONFIG_STM32MP25X
|
||||
#if defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X)
|
||||
#define STM32_USART2_BASE 0x400E0000
|
||||
#define STM32_USART3_BASE 0x400F0000
|
||||
#define STM32_UART4_BASE 0x40100000
|
||||
@ -188,7 +190,7 @@ enum forced_boot_mode {
|
||||
|
||||
/* TAMP registers zone 3 RIF 1 (RW) at 96*/
|
||||
#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(96)
|
||||
#endif /* STM32MP25X */
|
||||
#endif /* defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X) */
|
||||
|
||||
/* offset used for BSEC driver: misc_read and misc_write */
|
||||
#define STM32_BSEC_SHADOW_OFFSET 0x0
|
||||
@ -212,14 +214,14 @@ enum forced_boot_mode {
|
||||
#define BSEC_OTP_MAC 57
|
||||
#define BSEC_OTP_BOARD 60
|
||||
#endif
|
||||
#ifdef CONFIG_STM32MP25X
|
||||
#if defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X)
|
||||
#define BSEC_OTP_SERIAL 5
|
||||
#define BSEC_OTP_RPN 9
|
||||
#define BSEC_OTP_REVID 102
|
||||
#define BSEC_OTP_PKG 122
|
||||
#define BSEC_OTP_BOARD 246
|
||||
#define BSEC_OTP_MAC 247
|
||||
#endif
|
||||
#endif /* defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X) */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <asm/types.h>
|
||||
|
||||
@ -30,29 +30,44 @@
|
||||
#define CPU_STM32MP131Fxx 0x05010EC8
|
||||
#define CPU_STM32MP131Dxx 0x05010EC9
|
||||
|
||||
/* ID for STM32MP23x = Device Part Number (RPN) (bit31:0) */
|
||||
#define CPU_STM32MP235Cxx 0x00082182
|
||||
#define CPU_STM32MP233Cxx 0x000B318E
|
||||
#define CPU_STM32MP231Cxx 0x000B31EF
|
||||
#define CPU_STM32MP235Axx 0x40082F82
|
||||
#define CPU_STM32MP233Axx 0x400B3F8E
|
||||
#define CPU_STM32MP231Axx 0x400B3FEF
|
||||
#define CPU_STM32MP235Fxx 0x80082182
|
||||
#define CPU_STM32MP233Fxx 0x800B318E
|
||||
#define CPU_STM32MP231Fxx 0x800B31EF
|
||||
#define CPU_STM32MP235Dxx 0xC0082F82
|
||||
#define CPU_STM32MP233Dxx 0xC00B3F8E
|
||||
#define CPU_STM32MP231Dxx 0xC00B3FEF
|
||||
|
||||
/* ID for STM32MP25x = Device Part Number (RPN) (bit31:0) */
|
||||
#define CPU_STM32MP257Cxx 0x00002000
|
||||
#define CPU_STM32MP255Cxx 0x00082000
|
||||
#define CPU_STM32MP253Cxx 0x000B2004
|
||||
#define CPU_STM32MP251Cxx 0x000B3065
|
||||
#define CPU_STM32MP257Axx 0x40002E00
|
||||
#define CPU_STM32MP255Axx 0x40082E00
|
||||
#define CPU_STM32MP253Axx 0x400B2E04
|
||||
#define CPU_STM32MP251Axx 0x400B3E65
|
||||
#define CPU_STM32MP257Fxx 0x80002000
|
||||
#define CPU_STM32MP255Fxx 0x80082000
|
||||
#define CPU_STM32MP253Fxx 0x800B2004
|
||||
#define CPU_STM32MP251Fxx 0x800B3065
|
||||
#define CPU_STM32MP257Dxx 0xC0002E00
|
||||
#define CPU_STM32MP255Dxx 0xC0082E00
|
||||
#define CPU_STM32MP253Dxx 0xC00B2E04
|
||||
#define CPU_STM32MP251Dxx 0xC00B3E65
|
||||
#define CPU_STM32MP257Cxx 0x00002000
|
||||
#define CPU_STM32MP255Cxx 0x00082000
|
||||
#define CPU_STM32MP253Cxx 0x000B2004
|
||||
#define CPU_STM32MP251Cxx 0x000B3065
|
||||
#define CPU_STM32MP257Axx 0x40002E00
|
||||
#define CPU_STM32MP255Axx 0x40082E00
|
||||
#define CPU_STM32MP253Axx 0x400B2E04
|
||||
#define CPU_STM32MP251Axx 0x400B3E65
|
||||
#define CPU_STM32MP257Fxx 0x80002000
|
||||
#define CPU_STM32MP255Fxx 0x80082000
|
||||
#define CPU_STM32MP253Fxx 0x800B2004
|
||||
#define CPU_STM32MP251Fxx 0x800B3065
|
||||
#define CPU_STM32MP257Dxx 0xC0002E00
|
||||
#define CPU_STM32MP255Dxx 0xC0082E00
|
||||
#define CPU_STM32MP253Dxx 0xC00B2E04
|
||||
#define CPU_STM32MP251Dxx 0xC00B3E65
|
||||
|
||||
/* return CPU_STMP32MP...Xxx constants */
|
||||
u32 get_cpu_type(void);
|
||||
|
||||
#define CPU_DEV_STM32MP15 0x500
|
||||
#define CPU_DEV_STM32MP13 0x501
|
||||
#define CPU_DEV_STM32MP23 0x505
|
||||
#define CPU_DEV_STM32MP25 0x505
|
||||
|
||||
/* return CPU_DEV constants */
|
||||
@ -87,6 +102,12 @@ u32 get_cpu_package(void);
|
||||
#define STM32MP15_PKG_AD_TFBGA257 1
|
||||
#define STM32MP15_PKG_UNKNOWN 0
|
||||
|
||||
/* package used for STM32MP23x */
|
||||
#define STM32MP23_PKG_CUSTOM 0
|
||||
#define STM32MP23_PKG_AL_VFBGA361 1
|
||||
#define STM32MP23_PKG_AK_VFBGA424 3
|
||||
#define STM32MP23_PKG_AJ_TFBGA361 7
|
||||
|
||||
/* package used for STM32MP25x */
|
||||
#define STM32MP25_PKG_CUSTOM 0
|
||||
#define STM32MP25_PKG_AL_VFBGA361 1
|
||||
|
||||
@ -29,6 +29,10 @@
|
||||
#define TIM_DMAR 0x4C /* DMA register for transfer */
|
||||
#define TIM_TISEL 0x68 /* Input Selection */
|
||||
|
||||
#define TIM_HWCFGR2 0x3EC /* hardware configuration 2 Reg (MP25) */
|
||||
#define TIM_HWCFGR1 0x3F0 /* hardware configuration 1 Reg (MP25) */
|
||||
#define TIM_IPIDR 0x3F8 /* IP identification Reg (MP25) */
|
||||
|
||||
#define TIM_CR1_CEN BIT(0) /* Counter Enable */
|
||||
#define TIM_CR1_ARPE BIT(7)
|
||||
#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12))
|
||||
@ -40,11 +44,16 @@
|
||||
#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */
|
||||
#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */
|
||||
#define TIM_EGR_UG BIT(0) /* Update Generation */
|
||||
#define TIM_HWCFGR2_CNT_WIDTH GENMASK(15, 8) /* Counter width */
|
||||
#define TIM_HWCFGR1_NB_OF_DT GENMASK(7, 4) /* Complementary outputs & dead-time generators */
|
||||
|
||||
#define MAX_TIM_PSC 0xFFFF
|
||||
|
||||
#define STM32MP25_TIM_IPIDR 0x00120002
|
||||
|
||||
struct stm32_timers_plat {
|
||||
void __iomem *base;
|
||||
u32 ipidr;
|
||||
};
|
||||
|
||||
struct stm32_timers_priv {
|
||||
|
||||
@ -28,7 +28,9 @@
|
||||
* early TLB into the .data section so that it not get cleared
|
||||
* with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
|
||||
*/
|
||||
#if (!IS_ENABLED(CONFIG_XPL_BUILD) || !IS_ENABLED(CONFIG_STM32MP13X))
|
||||
u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
|
||||
#endif
|
||||
|
||||
u32 get_bootmode(void)
|
||||
{
|
||||
@ -95,18 +97,19 @@ void dram_bank_mmu_setup(int bank)
|
||||
*/
|
||||
static void early_enable_caches(void)
|
||||
{
|
||||
#if (!IS_ENABLED(CONFIG_XPL_BUILD) || !IS_ENABLED(CONFIG_STM32MP13X))
|
||||
/* I-cache is already enabled in start.S: cpu_init_cp15 */
|
||||
|
||||
if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
|
||||
return;
|
||||
|
||||
#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
|
||||
gd->arch.tlb_size = PGTABLE_SIZE;
|
||||
gd->arch.tlb_addr = (unsigned long)&early_tlb;
|
||||
gd->arch.tlb_size = PGTABLE_SIZE;
|
||||
gd->arch.tlb_addr = (unsigned long)&early_tlb;
|
||||
#endif
|
||||
|
||||
/* enable MMU (default configuration) */
|
||||
dcache_enable();
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@ -220,10 +220,11 @@ void board_init_f(ulong dummy)
|
||||
* activate cache on DDR only when DDR is fully initialized
|
||||
* to avoid speculative access and issue in get_ram_size()
|
||||
*/
|
||||
if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
|
||||
if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !IS_ENABLED(CONFIG_STM32MP13X)) {
|
||||
mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
|
||||
CONFIG_DDR_CACHEABLE_SIZE,
|
||||
DCACHE_DEFAULT_OPTION);
|
||||
}
|
||||
}
|
||||
|
||||
void spl_board_prepare_for_boot(void)
|
||||
|
||||
@ -6,11 +6,59 @@
|
||||
#define LOG_CATEGORY LOGC_ARCH
|
||||
|
||||
#include <config.h>
|
||||
#include <cpu_func.h>
|
||||
#include <log.h>
|
||||
#include <syscon.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/arch/bsec.h>
|
||||
#include <asm/arch/stm32.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <dm/device.h>
|
||||
#include <dm/uclass.h>
|
||||
#include <linux/bitfield.h>
|
||||
#include <malloc.h>
|
||||
|
||||
/* RCC register */
|
||||
#define RCC_TZCR (STM32_RCC_BASE + 0x00)
|
||||
#define RCC_BDCR (STM32_RCC_BASE + 0x400)
|
||||
#define RCC_DBGCFGR (STM32_RCC_BASE + 0x468)
|
||||
#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x740)
|
||||
#define RCC_MP_AHB6ENSETR (STM32_RCC_BASE + 0x780)
|
||||
|
||||
#define RCC_BDCR_VSWRST BIT(31)
|
||||
#define RCC_BDCR_RTCSRC GENMASK(17, 16)
|
||||
|
||||
#define RCC_DBGCFGR_DBGCKEN BIT(8)
|
||||
|
||||
/* DBGMCU register */
|
||||
#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2c)
|
||||
#define DBGMCU_APB4FZ1_IWDG2 BIT(2)
|
||||
|
||||
/* Security register */
|
||||
#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
|
||||
#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
|
||||
|
||||
#define TZC_ACTION (STM32_TZC_BASE + 0x004)
|
||||
#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
|
||||
#define TZC_REGION_BASE(n) (STM32_TZC_BASE + 0x100 + (0x20 * (n)))
|
||||
#define TZC_REGION_TOP(n) (STM32_TZC_BASE + 0x108 + (0x20 * (n)))
|
||||
#define TZC_REGION_ATTRIBUTE(n) (STM32_TZC_BASE + 0x110 + (0x20 * (n)))
|
||||
#define TZC_REGION_ID_ACCESS(n) (STM32_TZC_BASE + 0x114 + (0x20 * (n)))
|
||||
|
||||
#define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
|
||||
|
||||
#define PWR_CR1 (STM32_PWR_BASE + 0x00)
|
||||
#define PWR_CR1_DBP BIT(8)
|
||||
|
||||
/* boot interface from Bootrom
|
||||
* - boot instance = bit 31:16
|
||||
* - boot device = bit 15:0
|
||||
*/
|
||||
#define BOOTROM_MODE_MASK GENMASK(15, 0)
|
||||
#define BOOTROM_MODE_SHIFT 0
|
||||
#define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
|
||||
#define BOOTROM_INSTANCE_SHIFT 16
|
||||
|
||||
/* SYSCFG register */
|
||||
#define SYSCFG_IDC_OFFSET 0x380
|
||||
@ -23,6 +71,162 @@
|
||||
#define RPN_SHIFT 0
|
||||
#define RPN_MASK GENMASK(11, 0)
|
||||
|
||||
static void security_init(void)
|
||||
{
|
||||
/* Disable the backup domain write protection */
|
||||
/* the protection is enable at each reset by hardware */
|
||||
/* And must be disable by software */
|
||||
setbits_le32(PWR_CR1, PWR_CR1_DBP);
|
||||
|
||||
while (!(readl(PWR_CR1) & PWR_CR1_DBP))
|
||||
;
|
||||
|
||||
/* If RTC clock isn't enable so this is a cold boot then we need
|
||||
* to reset the backup domain
|
||||
*/
|
||||
if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
|
||||
setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
|
||||
while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
|
||||
;
|
||||
clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
|
||||
}
|
||||
|
||||
/* allow non secure access in Write/Read for all peripheral */
|
||||
writel(0, ETZPC_DECPROT0);
|
||||
|
||||
/* Open SYSRAM for no secure access */
|
||||
writel(0x0, ETZPC_TZMA1_SIZE);
|
||||
|
||||
/* enable MCE clock */
|
||||
writel(BIT(1), RCC_MP_AHB6ENSETR);
|
||||
|
||||
/* enable TZC clock */
|
||||
writel(BIT(11), RCC_MP_APB5ENSETR);
|
||||
|
||||
/* Disable Filter 0 */
|
||||
writel(0, TZC_GATE_KEEPER);
|
||||
|
||||
/* Region 0 set to no access by default */
|
||||
/* bit 0 / 16 => nsaid0 read/write Enable
|
||||
* bit 1 / 17 => nsaid1 read/write Enable
|
||||
* ...
|
||||
* bit 15 / 31 => nsaid15 read/write Enable
|
||||
*/
|
||||
writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS(0));
|
||||
|
||||
/* bit 30 / 31 => Secure Global Enable : write/read */
|
||||
writel(BIT(0) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE(0));
|
||||
|
||||
writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS(1));
|
||||
writel(0xC0000000, TZC_REGION_BASE(1));
|
||||
writel(0xDDFFFFFF, TZC_REGION_TOP(1));
|
||||
writel(BIT(0) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE(1));
|
||||
|
||||
writel(0x00000000, TZC_REGION_ID_ACCESS(2));
|
||||
writel(0xDE000000, TZC_REGION_BASE(2));
|
||||
writel(0xDFFFFFFF, TZC_REGION_TOP(2));
|
||||
writel(BIT(0) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE(2));
|
||||
|
||||
writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS(3));
|
||||
writel(0x00000000, TZC_REGION_BASE(3));
|
||||
writel(0xBFFFFFFF, TZC_REGION_TOP(3));
|
||||
writel(BIT(0) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE(3));
|
||||
|
||||
/* Set Action */
|
||||
writel(BIT(0), TZC_ACTION);
|
||||
|
||||
/* Enable Filter 0 */
|
||||
writel(BIT(0), TZC_GATE_KEEPER);
|
||||
|
||||
/* RCC trust zone deactivated */
|
||||
writel(0x0, RCC_TZCR);
|
||||
|
||||
/* TAMP: deactivate the internal tamper
|
||||
* Bit 23 ITAMP8E: monotonic counter overflow
|
||||
* Bit 20 ITAMP5E: RTC calendar overflow
|
||||
* Bit 19 ITAMP4E: HSE monitoring
|
||||
* Bit 18 ITAMP3E: LSE monitoring
|
||||
* Bit 16 ITAMP1E: RTC power domain supply monitoring
|
||||
*/
|
||||
writel(0x0, TAMP_CR1);
|
||||
}
|
||||
|
||||
/*
|
||||
* Debug init
|
||||
*/
|
||||
void dbgmcu_init(void)
|
||||
{
|
||||
/*
|
||||
* Freeze IWDG2 if Cortex-A7 is in debug mode
|
||||
* done in TF-A for TRUSTED boot and
|
||||
* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE
|
||||
*/
|
||||
if (bsec_dbgswenable()) {
|
||||
setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
|
||||
setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
|
||||
}
|
||||
}
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
u8 *tlb;
|
||||
int ret;
|
||||
|
||||
dbgmcu_init();
|
||||
|
||||
/* force probe of BSEC driver to shadow the upper OTP */
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), &dev);
|
||||
if (ret)
|
||||
log_warning("BSEC probe failed: %d\n", ret);
|
||||
|
||||
/* Enable Dcache here, now that DRAM is available */
|
||||
if (IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_STM32MP13X)) {
|
||||
tlb = memalign(0x4000, PGTABLE_SIZE);
|
||||
if (!tlb)
|
||||
return;
|
||||
|
||||
gd->arch.tlb_size = PGTABLE_SIZE;
|
||||
gd->arch.tlb_addr = (unsigned long)tlb;
|
||||
dcache_enable();
|
||||
}
|
||||
}
|
||||
|
||||
/* get bootmode from ROM code boot context: saved in TAMP register */
|
||||
static void update_bootmode(void)
|
||||
{
|
||||
u32 boot_mode;
|
||||
u32 bootrom_itf = readl(get_stm32mp_rom_api_table());
|
||||
u32 bootrom_device, bootrom_instance;
|
||||
|
||||
/* enable TAMP clock = RTCAPBEN */
|
||||
writel(BIT(8), RCC_MP_APB5ENSETR);
|
||||
|
||||
/* read bootrom context */
|
||||
bootrom_device =
|
||||
(bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
|
||||
bootrom_instance =
|
||||
(bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
|
||||
boot_mode =
|
||||
((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
|
||||
((bootrom_instance << BOOT_INSTANCE_SHIFT) &
|
||||
BOOT_INSTANCE_MASK);
|
||||
|
||||
/* save the boot mode in TAMP backup register */
|
||||
clrsetbits_le32(TAMP_BOOT_CONTEXT,
|
||||
TAMP_BOOT_MODE_MASK,
|
||||
boot_mode << TAMP_BOOT_MODE_SHIFT);
|
||||
}
|
||||
|
||||
/* weak function: STM32MP15x mach init for boot without TFA */
|
||||
void stm32mp_cpu_init(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_XPL_BUILD)) {
|
||||
security_init();
|
||||
update_bootmode();
|
||||
}
|
||||
}
|
||||
|
||||
static u32 read_idc(void)
|
||||
{
|
||||
void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
|
||||
|
||||
@ -7,4 +7,5 @@ obj-y += cpu.o
|
||||
obj-y += arm64-mmu.o
|
||||
obj-y += rifsc.o
|
||||
obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
|
||||
obj-$(CONFIG_STM32MP23X) += stm32mp23x.o
|
||||
obj-$(CONFIG_STM32MP25X) += stm32mp25x.o
|
||||
|
||||
191
arch/arm/mach-stm32mp/stm32mp2/stm32mp23x.c
Normal file
191
arch/arm/mach-stm32mp/stm32mp2/stm32mp23x.c
Normal file
@ -0,0 +1,191 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
|
||||
/*
|
||||
* Copyright (C) 2025, STMicroelectronics - All Rights Reserved
|
||||
*/
|
||||
|
||||
#define LOG_CATEGORY LOGC_ARCH
|
||||
|
||||
#include <log.h>
|
||||
#include <syscon.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/stm32.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
||||
/* SYSCFG register */
|
||||
#define SYSCFG_DEVICEID_OFFSET 0x6400
|
||||
#define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0)
|
||||
#define SYSCFG_DEVICEID_DEV_ID_SHIFT 0
|
||||
|
||||
/* Revision ID = OTP102[5:0] 6 bits : 3 for Major / 3 for Minor*/
|
||||
#define REVID_SHIFT 0
|
||||
#define REVID_MASK GENMASK(5, 0)
|
||||
|
||||
/* Device Part Number (RPN) = OTP9 */
|
||||
#define RPN_SHIFT 0
|
||||
#define RPN_MASK GENMASK(31, 0)
|
||||
|
||||
/* Package = bit 0:2 of OTP122 => STM32MP23_PKG defines
|
||||
* - 000: Custom package
|
||||
* - 011: TFBGA361 => AL = 10x10, 361 balls pith 0.5mm
|
||||
* - 100: TFBGA424 => AK = 14x14, 424 balls pith 0.5mm
|
||||
* - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm
|
||||
* - others: Reserved
|
||||
*/
|
||||
#define PKG_SHIFT 0
|
||||
#define PKG_MASK GENMASK(2, 0)
|
||||
|
||||
static u32 read_deviceid(void)
|
||||
{
|
||||
void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
|
||||
|
||||
return readl(syscfg + SYSCFG_DEVICEID_OFFSET);
|
||||
}
|
||||
|
||||
u32 get_cpu_dev(void)
|
||||
{
|
||||
return (read_deviceid() & SYSCFG_DEVICEID_DEV_ID_MASK) >> SYSCFG_DEVICEID_DEV_ID_SHIFT;
|
||||
}
|
||||
|
||||
u32 get_cpu_rev(void)
|
||||
{
|
||||
return get_otp(BSEC_OTP_REVID, REVID_SHIFT, REVID_MASK);
|
||||
}
|
||||
|
||||
/* Get Device Part Number (RPN) from OTP */
|
||||
u32 get_cpu_type(void)
|
||||
{
|
||||
return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
|
||||
}
|
||||
|
||||
/* Get Package options from OTP */
|
||||
u32 get_cpu_package(void)
|
||||
{
|
||||
return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
|
||||
}
|
||||
|
||||
int get_eth_nb(void)
|
||||
{
|
||||
int nb_eth;
|
||||
|
||||
switch (get_cpu_type()) {
|
||||
case CPU_STM32MP235Fxx:
|
||||
fallthrough;
|
||||
case CPU_STM32MP235Dxx:
|
||||
fallthrough;
|
||||
case CPU_STM32MP235Cxx:
|
||||
fallthrough;
|
||||
case CPU_STM32MP235Axx:
|
||||
fallthrough;
|
||||
case CPU_STM32MP233Fxx:
|
||||
fallthrough;
|
||||
case CPU_STM32MP233Dxx:
|
||||
fallthrough;
|
||||
case CPU_STM32MP233Cxx:
|
||||
fallthrough;
|
||||
case CPU_STM32MP233Axx:
|
||||
nb_eth = 2; /* dual ETH */
|
||||
break;
|
||||
case CPU_STM32MP231Fxx:
|
||||
fallthrough;
|
||||
case CPU_STM32MP231Dxx:
|
||||
fallthrough;
|
||||
case CPU_STM32MP231Cxx:
|
||||
fallthrough;
|
||||
case CPU_STM32MP231Axx:
|
||||
nb_eth = 1; /* single ETH */
|
||||
break;
|
||||
default:
|
||||
nb_eth = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
return nb_eth;
|
||||
}
|
||||
|
||||
void get_soc_name(char name[SOC_NAME_SIZE])
|
||||
{
|
||||
char *cpu_s, *cpu_r, *package;
|
||||
|
||||
cpu_s = "????";
|
||||
cpu_r = "?";
|
||||
package = "??";
|
||||
if (get_cpu_dev() == CPU_DEV_STM32MP23) {
|
||||
switch (get_cpu_type()) {
|
||||
case CPU_STM32MP235Fxx:
|
||||
cpu_s = "235F";
|
||||
break;
|
||||
case CPU_STM32MP235Dxx:
|
||||
cpu_s = "235D";
|
||||
break;
|
||||
case CPU_STM32MP235Cxx:
|
||||
cpu_s = "235C";
|
||||
break;
|
||||
case CPU_STM32MP235Axx:
|
||||
cpu_s = "235A";
|
||||
break;
|
||||
case CPU_STM32MP233Fxx:
|
||||
cpu_s = "233F";
|
||||
break;
|
||||
case CPU_STM32MP233Dxx:
|
||||
cpu_s = "233D";
|
||||
break;
|
||||
case CPU_STM32MP233Cxx:
|
||||
cpu_s = "233C";
|
||||
break;
|
||||
case CPU_STM32MP233Axx:
|
||||
cpu_s = "233A";
|
||||
break;
|
||||
case CPU_STM32MP231Fxx:
|
||||
cpu_s = "231F";
|
||||
break;
|
||||
case CPU_STM32MP231Dxx:
|
||||
cpu_s = "231D";
|
||||
break;
|
||||
case CPU_STM32MP231Cxx:
|
||||
cpu_s = "231C";
|
||||
break;
|
||||
case CPU_STM32MP231Axx:
|
||||
cpu_s = "231A";
|
||||
break;
|
||||
default:
|
||||
cpu_s = "23??";
|
||||
break;
|
||||
}
|
||||
/* REVISION */
|
||||
switch (get_cpu_rev()) {
|
||||
case OTP_REVID_1:
|
||||
cpu_r = "A";
|
||||
break;
|
||||
case OTP_REVID_2:
|
||||
cpu_r = "B";
|
||||
break;
|
||||
case OTP_REVID_2_1:
|
||||
cpu_r = "Y";
|
||||
break;
|
||||
case OTP_REVID_2_2:
|
||||
cpu_r = "X";
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
/* PACKAGE */
|
||||
switch (get_cpu_package()) {
|
||||
case STM32MP23_PKG_CUSTOM:
|
||||
package = "XX";
|
||||
break;
|
||||
case STM32MP23_PKG_AL_VFBGA361:
|
||||
package = "AL";
|
||||
break;
|
||||
case STM32MP23_PKG_AK_VFBGA424:
|
||||
package = "AK";
|
||||
break;
|
||||
case STM32MP23_PKG_AJ_TFBGA361:
|
||||
package = "AJ";
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, package, cpu_r);
|
||||
}
|
||||
@ -10,6 +10,7 @@
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/timers.h>
|
||||
#include <dm/device_compat.h>
|
||||
#include <linux/bitfield.h>
|
||||
|
||||
static void stm32_timers_get_arr_size(struct udevice *dev)
|
||||
{
|
||||
@ -29,6 +30,33 @@ static void stm32_timers_get_arr_size(struct udevice *dev)
|
||||
writel(arr, plat->base + TIM_ARR);
|
||||
}
|
||||
|
||||
static int stm32_timers_probe_hwcfgr(struct udevice *dev)
|
||||
{
|
||||
struct stm32_timers_plat *plat = dev_get_plat(dev);
|
||||
struct stm32_timers_priv *priv = dev_get_priv(dev);
|
||||
u32 val;
|
||||
|
||||
if (!plat->ipidr) {
|
||||
/* fallback to legacy method for probing counter width */
|
||||
stm32_timers_get_arr_size(dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
val = readl(plat->base + TIM_IPIDR);
|
||||
/* Sanity check on IP identification register */
|
||||
if (val != plat->ipidr) {
|
||||
dev_err(dev, "Unexpected identification: %u\n", val);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
val = readl(plat->base + TIM_HWCFGR2);
|
||||
/* Counter width in bits, max reload value is BIT(width) - 1 */
|
||||
priv->max_arr = BIT(FIELD_GET(TIM_HWCFGR2_CNT_WIDTH, val)) - 1;
|
||||
dev_dbg(dev, "TIM width: %ld\n", FIELD_GET(TIM_HWCFGR2_CNT_WIDTH, val));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_timers_of_to_plat(struct udevice *dev)
|
||||
{
|
||||
struct stm32_timers_plat *plat = dev_get_plat(dev);
|
||||
@ -38,6 +66,7 @@ static int stm32_timers_of_to_plat(struct udevice *dev)
|
||||
dev_err(dev, "can't get address\n");
|
||||
return -ENOENT;
|
||||
}
|
||||
plat->ipidr = (u32)dev_get_driver_data(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -60,13 +89,16 @@ static int stm32_timers_probe(struct udevice *dev)
|
||||
|
||||
priv->rate = clk_get_rate(&clk);
|
||||
|
||||
stm32_timers_get_arr_size(dev);
|
||||
ret = stm32_timers_probe_hwcfgr(dev);
|
||||
if (ret)
|
||||
clk_disable(&clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct udevice_id stm32_timers_ids[] = {
|
||||
{ .compatible = "st,stm32-timers" },
|
||||
{ .compatible = "st,stm32mp25-timers", .data = STM32MP25_TIM_IPIDR },
|
||||
{}
|
||||
};
|
||||
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
config CMD_STBOARD
|
||||
bool "stboard - command for OTP board information"
|
||||
depends on ARCH_STM32MP
|
||||
default y if TARGET_ST_STM32MP25X || TARGET_ST_STM32MP15X || TARGET_ST_STM32MP13X
|
||||
default y if TARGET_ST_STM32MP13X || TARGET_ST_STM32MP15X || TARGET_ST_STM32MP23X || TARGET_ST_STM32MP25X
|
||||
help
|
||||
This compile the stboard command to
|
||||
read and write the board in the OTP.
|
||||
|
||||
@ -14,8 +14,19 @@
|
||||
#include <power/pmic.h>
|
||||
#include <power/stpmic1.h>
|
||||
|
||||
static bool is_stm32mp13xx(void)
|
||||
{
|
||||
if (!IS_ENABLED(CONFIG_STM32MP13X))
|
||||
return false;
|
||||
|
||||
return of_machine_is_compatible("st,stm32mp131") ||
|
||||
of_machine_is_compatible("st,stm32mp133") ||
|
||||
of_machine_is_compatible("st,stm32mp135");
|
||||
}
|
||||
|
||||
int board_ddr_power_init(enum ddr_type ddr_type)
|
||||
{
|
||||
bool is_mp13 = is_stm32mp13xx();
|
||||
struct udevice *dev;
|
||||
bool buck3_at_1800000v = false;
|
||||
int ret;
|
||||
@ -30,18 +41,21 @@ int board_ddr_power_init(enum ddr_type ddr_type)
|
||||
switch (ddr_type) {
|
||||
case STM32MP_DDR3:
|
||||
/* VTT = Set LDO3 to sync mode */
|
||||
ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
if (!is_mp13) {
|
||||
/* Enable VTT only on STM32MP15xx */
|
||||
ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret &= ~STPMIC1_LDO3_MODE;
|
||||
ret &= ~STPMIC1_LDO12356_VOUT_MASK;
|
||||
ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
|
||||
ret &= ~STPMIC1_LDO3_MODE;
|
||||
ret &= ~STPMIC1_LDO12356_VOUT_MASK;
|
||||
ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
|
||||
|
||||
ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
|
||||
ret);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
|
||||
ret);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* VDD_DDR = Set BUCK2 to 1.35V */
|
||||
ret = pmic_clrsetbits(dev,
|
||||
@ -69,11 +83,14 @@ int board_ddr_power_init(enum ddr_type ddr_type)
|
||||
mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
|
||||
|
||||
/* Enable VTT = LDO3 */
|
||||
ret = pmic_clrsetbits(dev,
|
||||
STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
|
||||
STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
if (!is_mp13) {
|
||||
/* Enable VTT only on STM32MP15xx */
|
||||
ret = pmic_clrsetbits(dev,
|
||||
STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
|
||||
STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
|
||||
|
||||
|
||||
@ -9,17 +9,32 @@
|
||||
#include <asm/arch/stm32.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#if IS_ENABLED(CONFIG_STM32MP13X)
|
||||
#define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0700)
|
||||
#define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0768)
|
||||
#elif IS_ENABLED(CONFIG_STM32MP15X)
|
||||
#define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00)
|
||||
#define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28)
|
||||
#endif
|
||||
|
||||
#define GPIOA_BASE 0x50002000
|
||||
#define GPIOG_BASE 0x50008000
|
||||
|
||||
void board_debug_uart_init(void)
|
||||
{
|
||||
if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE) {
|
||||
/* UART4 clock enable */
|
||||
setbits_le32(RCC_MP_APB1ENSETR, BIT(16));
|
||||
if (CONFIG_DEBUG_UART_BASE != STM32_UART4_BASE)
|
||||
return;
|
||||
|
||||
/* UART4 clock enable */
|
||||
setbits_le32(RCC_MP_APB1ENSETR, BIT(16));
|
||||
|
||||
if (IS_ENABLED(CONFIG_STM32MP13X)) {
|
||||
/* GPIOA clock enable */
|
||||
writel(BIT(0), RCC_MP_AHB4ENSETR);
|
||||
/* GPIO configuration for DH boards: Uart4 TX = A9 */
|
||||
writel(0xfffbffff, GPIOA_BASE + 0x00);
|
||||
writel(0x00000080, GPIOA_BASE + 0x24);
|
||||
} else if (IS_ENABLED(CONFIG_STM32MP15X)) {
|
||||
/* GPIOG clock enable */
|
||||
writel(BIT(6), RCC_MP_AHB4ENSETR);
|
||||
/* GPIO configuration for ST boards: Uart4 TX = G11 */
|
||||
|
||||
@ -1,3 +1,17 @@
|
||||
if TARGET_ST_STM32MP23X
|
||||
|
||||
config SYS_BOARD
|
||||
default "stm32mp2"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "st"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "stm32mp23_st_common"
|
||||
|
||||
source "board/st/common/Kconfig"
|
||||
endif
|
||||
|
||||
if TARGET_ST_STM32MP25X
|
||||
|
||||
config SYS_BOARD
|
||||
|
||||
@ -48,6 +48,8 @@ CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_LOG=y
|
||||
CONFIG_CMD_UBI=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_UPSTREAM_BUILD_VENDOR=y
|
||||
CONFIG_OF_UPSTREAM_VENDOR="st"
|
||||
CONFIG_ENV_IS_NOWHERE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_REDUNDANT=y
|
||||
|
||||
@ -2,7 +2,6 @@
|
||||
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_STM32MP=y
|
||||
CONFIG_TFABOOT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x1c0000
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0400000
|
||||
CONFIG_ENV_OFFSET=0x3E0000
|
||||
@ -12,11 +11,16 @@ CONFIG_DDR_CACHEABLE_SIZE=0x8000000
|
||||
CONFIG_TARGET_ST_STM32MP13X=y
|
||||
CONFIG_ENV_OFFSET_REDUND=0x3F0000
|
||||
CONFIG_STM32MP15_PWR=y
|
||||
# CONFIG_ARMV7_NONSEC is not set
|
||||
CONFIG_ARMV7_NONSEC=y
|
||||
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
|
||||
CONFIG_ARMV7_PSCI_NR_CPUS=2
|
||||
# CONFIG_ARMV7_LPAE is not set
|
||||
CONFIG_SYS_MEMTEST_START=0xc0000000
|
||||
CONFIG_SYS_MEMTEST_END=0xc4000000
|
||||
CONFIG_SYS_MEM_TOP_HIDE=0x2000000
|
||||
CONFIG_BOOTSTAGE_RECORD_COUNT=100
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_BOOTM_OPTEE=y
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_ERASEENV=y
|
||||
@ -31,20 +35,28 @@ CONFIG_ENV_IS_NOWHERE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_MMC_USE_DT=y
|
||||
CONFIG_ENV_SPI_MAX_HZ=50000000
|
||||
CONFIG_CLK_SCMI=y
|
||||
CONFIG_SET_DFU_ALT_INFO=y
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
|
||||
CONFIG_ENV_MMC_DEVICE_INDEX=0
|
||||
CONFIG_ENV_MMC_EMMC_HW_PARTITION=1
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DM_REGULATOR_SCMI=y
|
||||
CONFIG_RESET_SCMI=y
|
||||
CONFIG_DM_RNG=y
|
||||
CONFIG_RNG_STM32=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_TEE=y
|
||||
CONFIG_OPTEE=y
|
||||
# CONFIG_OPTEE_TA_AVB is not set
|
||||
CONFIG_USB_ONBOARD_HUB=y
|
||||
CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2000
|
||||
CONFIG_ERRNO_STR=y
|
||||
CONFIG_OPTEE_LIB=y
|
||||
CONFIG_OPTEE_IMAGE=y
|
||||
CONFIG_OPTEE_TZDRAM_SIZE=0x02000000
|
||||
CONFIG_SPL_TEXT_BASE=0x2FFE0000
|
||||
CONFIG_SPL_CLK_CCF=y
|
||||
CONFIG_SPL_CLK_COMPOSITE_CCF=y
|
||||
# CONFIG_SPL_SHA1 is not set
|
||||
# CONFIG_SPL_SHA256 is not set
|
||||
CONFIG_SPL_HAVE_INIT_STACK=y
|
||||
CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL_GENERIC=y
|
||||
CONFIG_SPL_PINMUX=y
|
||||
CONFIG_SPL_PINCONF=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
|
||||
|
||||
@ -2,10 +2,6 @@
|
||||
|
||||
# CONFIG_ARMV7_VIRT is not set
|
||||
# CONFIG_BINMAN_FDT is not set
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
# CONFIG_SPL_PARTITION_UUIDS is not set
|
||||
# CONFIG_SPL_PINCTRL_FULL is not set
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_BOARD_SIZE_LIMIT=1441792
|
||||
CONFIG_BOOTCOUNT_BOOTLIMIT=3
|
||||
@ -20,9 +16,7 @@ CONFIG_CMD_STM32PROG_OTP=y
|
||||
CONFIG_CONSOLE_MUX=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
|
||||
CONFIG_DM_HWSPINLOCK=y
|
||||
CONFIG_DM_REGULATOR_STM32_VREFBUF=y
|
||||
CONFIG_HAS_BOARD_SIZE_LIMIT=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_HWSPINLOCK_STM32=y
|
||||
CONFIG_KS8851_MLL=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks access-controllers"
|
||||
@ -31,42 +25,7 @@ CONFIG_PINCTRL_STMFX=y
|
||||
CONFIG_REMOTEPROC_STM32_COPRO=y
|
||||
CONFIG_SERVERIP="192.168.1.1"
|
||||
CONFIG_SF_DEFAULT_SPEED=50000000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_BLOCK_CACHE=y
|
||||
CONFIG_SPL_BOOTCOUNT_LIMIT=y
|
||||
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
|
||||
CONFIG_SPL_DFU=y
|
||||
CONFIG_SPL_DM_REGULATOR=y
|
||||
CONFIG_SPL_DM_REGULATOR_STPMIC1=y
|
||||
CONFIG_SPL_DM_SPI=y
|
||||
CONFIG_SPL_DM_SPI_FLASH=y
|
||||
CONFIG_SPL_DM_USB_GADGET=y
|
||||
CONFIG_SPL_ENV_IS_NOWHERE=y
|
||||
CONFIG_SPL_ENV_SUPPORT=y
|
||||
CONFIG_SPL_FOOTPRINT_LIMIT=y
|
||||
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000
|
||||
CONFIG_SPL_MAX_FOOTPRINT=0x3db00
|
||||
CONFIG_SPL_MMC=y
|
||||
CONFIG_SPL_MTD=y
|
||||
CONFIG_SPL_PHY=y
|
||||
CONFIG_SPL_POWER=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_SPI=y
|
||||
CONFIG_SPL_SPI_FLASH_MTD=y
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_HAVE_INIT_STACK=y
|
||||
CONFIG_SPL_STACK=0x30000000
|
||||
CONFIG_SPL_SYS_MALLOC=y
|
||||
CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000
|
||||
CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
|
||||
CONFIG_SPL_TEXT_BASE=0x2FFC2500
|
||||
CONFIG_SPL_USB_GADGET=y
|
||||
CONFIG_STM32_ADC=y
|
||||
CONFIG_SYSRESET_SYSCON=y
|
||||
CONFIG_SYS_BOOTCOUNT_ADDR=0x5C00A14C
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
|
||||
@ -77,3 +36,10 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
|
||||
CONFIG_TARGET_DH_STM32MP1_PDK2=y
|
||||
CONFIG_USE_SERVERIP=y
|
||||
CONFIG_WATCHDOG_AUTOSTART=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
|
||||
CONFIG_SPL_TEXT_BASE=0x2FFC2500
|
||||
CONFIG_SPL_BLOCK_CACHE=y
|
||||
CONFIG_SPL_MMC=y
|
||||
|
||||
82
configs/stm32mp23_defconfig
Normal file
82
configs/stm32mp23_defconfig
Normal file
@ -0,0 +1,82 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_STM32MP=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x600000
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x90000000
|
||||
CONFIG_ENV_OFFSET=0x900000
|
||||
CONFIG_ENV_SECT_SIZE=0x40000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp235f-dk"
|
||||
CONFIG_SYS_BOOTM_LEN=0x2000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x84000000
|
||||
CONFIG_STM32MP23X=y
|
||||
CONFIG_DDR_CACHEABLE_SIZE=0x10000000
|
||||
CONFIG_CMD_STM32KEY=y
|
||||
CONFIG_ENV_OFFSET_REDUND=0x940000
|
||||
CONFIG_TARGET_ST_STM32MP23X=y
|
||||
CONFIG_SYS_MEMTEST_START=0x84000000
|
||||
CONFIG_SYS_MEMTEST_END=0x88000000
|
||||
CONFIG_API=y
|
||||
CONFIG_SYS_MMC_MAX_DEVICE=3
|
||||
CONFIG_FIT=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_BOOTDELAY=1
|
||||
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
|
||||
CONFIG_SYS_PROMPT="STM32MP> "
|
||||
# CONFIG_CMD_BDI is not set
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_ADTIMG=y
|
||||
# CONFIG_CMD_ELF is not set
|
||||
CONFIG_CMD_MEMINFO=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_FUSE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_RNG=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_LOG=y
|
||||
CONFIG_CMD_UBI=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_UPSTREAM_BUILD_VENDOR=y
|
||||
CONFIG_OF_UPSTREAM_VENDOR="st"
|
||||
CONFIG_ENV_IS_NOWHERE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_ENV_IS_IN_UBI=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_ENV_UBI_PART="UBI"
|
||||
CONFIG_ENV_UBI_VOLUME="uboot_config"
|
||||
CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r"
|
||||
CONFIG_SYS_MMC_ENV_DEV=-1
|
||||
CONFIG_NO_NET=y
|
||||
CONFIG_SYS_64BIT_LBA=y
|
||||
CONFIG_BUTTON=y
|
||||
CONFIG_BUTTON_GPIO=y
|
||||
CONFIG_GPIO_HOG=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_STM32F7=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_STM32_SDMMC2=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_USE_SYS_MAX_FLASH_BANKS=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_PINCONF=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_RAM=y
|
||||
# CONFIG_STM32MP1_DDR is not set
|
||||
CONFIG_DM_RNG=y
|
||||
CONFIG_SERIAL_RX_BUFFER=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
# CONFIG_OPTEE_TA_AVB is not set
|
||||
CONFIG_WDT=y
|
||||
CONFIG_WDT_STM32MP=y
|
||||
CONFIG_WDT_ARM_SMC=y
|
||||
# CONFIG_UBIFS_SILENCE_DEBUG_DUMP is not set
|
||||
CONFIG_ERRNO_STR=y
|
||||
@ -9,6 +9,7 @@ CONFIG_SYS_BOOTM_LEN=0x2000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x84000000
|
||||
CONFIG_STM32MP25X=y
|
||||
CONFIG_DDR_CACHEABLE_SIZE=0x10000000
|
||||
CONFIG_MFD_STM32_TIMERS=y
|
||||
CONFIG_ENV_OFFSET_REDUND=0x940000
|
||||
CONFIG_TARGET_ST_STM32MP25X=y
|
||||
CONFIG_SYS_MEMTEST_START=0x84000000
|
||||
@ -29,6 +30,7 @@ CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_FUSE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_PWM=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
@ -65,6 +67,8 @@ CONFIG_SPI_FLASH=y
|
||||
CONFIG_PINCONF=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_DM_PWM=y
|
||||
CONFIG_PWM_STM32=y
|
||||
CONFIG_RAM=y
|
||||
# CONFIG_STM32MP1_DDR is not set
|
||||
CONFIG_DM_RNG=y
|
||||
|
||||
@ -2,6 +2,10 @@
|
||||
# CONFIG_CMD_EXPORTENV is not set
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
# CONFIG_SPL_PARTITION_UUIDS is not set
|
||||
# CONFIG_SPL_PINCTRL_FULL is not set
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
|
||||
CONFIG_BOOTCOUNT_LIMIT=y
|
||||
CONFIG_CMD_BOOTCOUNT=y
|
||||
@ -38,6 +42,7 @@ CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_DM_REGULATOR_STPMIC1=y
|
||||
CONFIG_DM_REGULATOR_STM32_VREFBUF=y
|
||||
CONFIG_DM_RTC=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
@ -49,6 +54,7 @@ CONFIG_ENV_SIZE=0x4000
|
||||
CONFIG_FAT_WRITE=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_GPIO_HOG=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_IPV6=y
|
||||
CONFIG_IP_DEFRAG=y
|
||||
@ -58,6 +64,7 @@ CONFIG_MTD=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_UPSTREAM=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
|
||||
CONFIG_PHY=y
|
||||
CONFIG_PHY_STM32_USBPHYC=y
|
||||
CONFIG_PINCONF=y
|
||||
@ -66,17 +73,39 @@ CONFIG_PROT_TCP_SACK=y
|
||||
CONFIG_RTC_STM32=y
|
||||
CONFIG_SERIAL_RX_BUFFER=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_BOOTCOUNT_LIMIT=y
|
||||
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
|
||||
CONFIG_SPL_DFU=y
|
||||
CONFIG_SPL_DM_SPI=y
|
||||
CONFIG_SPL_DM_SPI_FLASH=y
|
||||
CONFIG_SPL_ENV_IS_NOWHERE=y
|
||||
CONFIG_SPL_ENV_SUPPORT=y
|
||||
CONFIG_SPL_FOOTPRINT_LIMIT=y
|
||||
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000
|
||||
CONFIG_SPL_MAX_FOOTPRINT=0x3db00
|
||||
CONFIG_SPL_MTD=y
|
||||
CONFIG_SPL_PHY=y
|
||||
CONFIG_SPL_POWER=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_SPI=y
|
||||
CONFIG_SPL_SPI_FLASH_MTD=y
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_STACK=0x30000000
|
||||
CONFIG_SPL_SYS_MALLOC=y
|
||||
CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000
|
||||
CONFIG_STM32_FMC2_EBI=y
|
||||
CONFIG_STM32_QSPI=y
|
||||
CONFIG_STM32_SDMMC2=y
|
||||
CONFIG_STM32_SPI=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_SYSRESET_SYSCON=y
|
||||
CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
|
||||
CONFIG_SYS_BOOTM_LEN=0x2000000
|
||||
CONFIG_SYS_DISABLE_AUTOLOAD=y
|
||||
|
||||
@ -336,8 +336,8 @@ static int scmi_clk_probe(struct udevice *dev)
|
||||
static int __scmi_clk_set_parent(struct clk *clk, struct clk *parent)
|
||||
{
|
||||
struct scmi_clk_parent_set_in in = {
|
||||
.clock_id = clk->id,
|
||||
.parent_clk = parent->id,
|
||||
.clock_id = clk_get_id(clk),
|
||||
.parent_clk = clk_get_id(parent),
|
||||
};
|
||||
struct scmi_clk_parent_set_out out;
|
||||
struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK,
|
||||
|
||||
@ -549,8 +549,8 @@ static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs,
|
||||
divr1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK;
|
||||
divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1;
|
||||
|
||||
fracn1 = readl(®s->pll1fracr) & RCC_PLL1DIVR_DIVR1_MASK;
|
||||
fracn1 = fracn1 & RCC_PLL1DIVR_DIVR1_SHIFT;
|
||||
fracn1 = readl(®s->pll1fracr) & RCC_PLL1FRACR_FRACN1_MASK;
|
||||
fracn1 = (fracn1 >> RCC_PLL1FRACR_FRACN1_SHIFT) + 1;
|
||||
|
||||
vco = (pllsrc / divm1) * divn1;
|
||||
rate = (pllsrc * fracn1) / (divm1 * 8192);
|
||||
|
||||
@ -12,6 +12,7 @@
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/timers.h>
|
||||
#include <dm/device_compat.h>
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/time.h>
|
||||
|
||||
#define CCMR_CHANNEL_SHIFT 8
|
||||
@ -157,7 +158,14 @@ static void stm32_pwm_detect_complementary(struct udevice *dev)
|
||||
{
|
||||
struct stm32_timers_plat *plat = dev_get_plat(dev_get_parent(dev));
|
||||
struct stm32_pwm_priv *priv = dev_get_priv(dev);
|
||||
u32 ccer;
|
||||
u32 ccer, val;
|
||||
|
||||
if (plat->ipidr) {
|
||||
/* Simply read from HWCFGR the number of complementary outputs (MP25). */
|
||||
val = readl(plat->base + TIM_HWCFGR1);
|
||||
priv->have_complementary_output = !!FIELD_GET(TIM_HWCFGR1_NB_OF_DT, val);
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* If complementary bit doesn't exist writing 1 will have no
|
||||
@ -192,6 +200,7 @@ static const struct pwm_ops stm32_pwm_ops = {
|
||||
|
||||
static const struct udevice_id stm32_pwm_ids[] = {
|
||||
{ .compatible = "st,stm32-pwm" },
|
||||
{ .compatible = "st,stm32mp25-pwm" },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
||||
@ -16,7 +16,7 @@ config RESET_STM32MP1
|
||||
|
||||
config RESET_STM32MP25
|
||||
bool "Enable the STM32MP25 reset"
|
||||
depends on STM32MP25X
|
||||
depends on STM32MP23X || STM32MP25X
|
||||
default y
|
||||
help
|
||||
Support for reset controllers on STMicroelectronics STM32MP2 family SoCs.
|
||||
|
||||
@ -6,7 +6,7 @@
|
||||
|
||||
#include <dm.h>
|
||||
#include <reset-uclass.h>
|
||||
#include <stm32-reset-core.h>
|
||||
#include "stm32-reset-core.h"
|
||||
#include <stm32_rcc.h>
|
||||
#include <dm/device_compat.h>
|
||||
#include <linux/iopoll.h>
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
*/
|
||||
|
||||
#include <dm.h>
|
||||
#include <stm32-reset-core.h>
|
||||
#include "stm32-reset-core.h"
|
||||
|
||||
/* Reset clear offset for STM32MP RCC */
|
||||
#define RCC_CLR_OFFSET 0x4
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
*/
|
||||
|
||||
#include <dm.h>
|
||||
#include <stm32-reset-core.h>
|
||||
#include "stm32-reset-core.h"
|
||||
#include <stm32mp25_rcc.h>
|
||||
#include <dt-bindings/reset/st,stm32mp25-rcc.h>
|
||||
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
*/
|
||||
|
||||
#include <dm.h>
|
||||
#include <stm32-reset-core.h>
|
||||
#include "stm32-reset-core.h"
|
||||
|
||||
/* Timeout for deassert */
|
||||
#define STM32_DEASSERT_TIMEOUT_US 10000
|
||||
@ -19,7 +19,7 @@ static const struct stm32_reset_cfg *stm32_get_reset_line(struct reset_ctl *rese
|
||||
|
||||
ptr_line->offset = bank;
|
||||
ptr_line->bit_idx = offset;
|
||||
ptr_line->set_clr = true;
|
||||
ptr_line->set_clr = false;
|
||||
|
||||
return ptr_line;
|
||||
}
|
||||
|
||||
130
include/configs/stm32mp23_common.h
Normal file
130
include/configs/stm32mp23_common.h
Normal file
@ -0,0 +1,130 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (C) 2025, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* Configuration settings for the STM32MP23x CPU
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_STM32MP23_COMMMON_H
|
||||
#define __CONFIG_STM32MP23_COMMMON_H
|
||||
#include <linux/sizes.h>
|
||||
#include <asm/arch/stm32.h>
|
||||
|
||||
/*
|
||||
* Configuration of the external SRAM memory used by U-Boot
|
||||
*/
|
||||
#define CFG_SYS_SDRAM_BASE STM32_DDR_BASE
|
||||
|
||||
/*
|
||||
* For booting Linux, use the first 256 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_SYS_BOOTMAPSZ SZ_256M
|
||||
|
||||
#define STM32MP_FIP_IMAGE_GUID \
|
||||
EFI_GUID(0x19d5df83, 0x11b0, 0x457b, 0xbe, 0x2c, \
|
||||
0x75, 0x59, 0xc1, 0x31, 0x42, 0xa5)
|
||||
|
||||
/*****************************************************************************/
|
||||
#ifdef CONFIG_DISTRO_DEFAULTS
|
||||
/*****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_NET
|
||||
#define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
|
||||
#else
|
||||
#define BOOT_TARGET_PXE(func)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_MMC
|
||||
#define BOOT_TARGET_MMC0(func) func(MMC, mmc, 0)
|
||||
#define BOOT_TARGET_MMC1(func) func(MMC, mmc, 1)
|
||||
#define BOOT_TARGET_MMC2(func) func(MMC, mmc, 2)
|
||||
#else
|
||||
#define BOOT_TARGET_MMC0(func)
|
||||
#define BOOT_TARGET_MMC1(func)
|
||||
#define BOOT_TARGET_MMC2(func)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_UBIFS
|
||||
#define BOOT_TARGET_UBIFS(func) func(UBIFS, ubifs, 0, UBI, boot)
|
||||
#else
|
||||
#define BOOT_TARGET_UBIFS(func)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define BOOT_TARGET_USB(func) func(USB, usb, 0)
|
||||
#else
|
||||
#define BOOT_TARGET_USB(func)
|
||||
#endif
|
||||
|
||||
#define BOOT_TARGET_DEVICES(func) \
|
||||
BOOT_TARGET_MMC1(func) \
|
||||
BOOT_TARGET_UBIFS(func) \
|
||||
BOOT_TARGET_MMC0(func) \
|
||||
BOOT_TARGET_MMC2(func) \
|
||||
BOOT_TARGET_USB(func) \
|
||||
BOOT_TARGET_PXE(func)
|
||||
|
||||
/*
|
||||
* default bootcmd for stm32mp23:
|
||||
* for serial/usb: execute the stm32prog command
|
||||
* for mmc boot (eMMC, SD card), distro boot on the same mmc device
|
||||
* for NAND or SPI-NAND boot, distro boot with UBIFS on UBI partition
|
||||
* for other boot, use the default distro order in ${boot_targets}
|
||||
*/
|
||||
#define STM32MP_BOOTCMD "bootcmd_stm32mp=" \
|
||||
"echo \"Boot over ${boot_device}${boot_instance}!\";" \
|
||||
"if test ${boot_device} = serial || test ${boot_device} = usb;" \
|
||||
"then stm32prog ${boot_device} ${boot_instance}; " \
|
||||
"else " \
|
||||
"run env_check;" \
|
||||
"if test ${boot_device} = mmc;" \
|
||||
"then env set boot_targets \"mmc${boot_instance}\"; fi;" \
|
||||
"if test ${boot_device} = nand ||" \
|
||||
" test ${boot_device} = spi-nand ;" \
|
||||
"then env set boot_targets ubifs0; fi;" \
|
||||
"run distro_bootcmd;" \
|
||||
"fi;\0"
|
||||
|
||||
#ifndef STM32MP_BOARD_EXTRA_ENV
|
||||
#define STM32MP_BOARD_EXTRA_ENV
|
||||
#endif
|
||||
|
||||
#define STM32MP_EXTRA \
|
||||
"env_check=if env info -p -d -q; then env save; fi\0" \
|
||||
"boot_net_usb_start=true\0"
|
||||
/*
|
||||
* memory layout for 96MB uncompressed/compressed kernel,
|
||||
* 1M fdt, 1M script, 1M pxe and 1M for overlay
|
||||
* and the ramdisk at the end.
|
||||
*/
|
||||
#define __KERNEL_COMP_ADDR_R __stringify(0x84000000)
|
||||
#define __KERNEL_COMP_SIZE_R __stringify(0x04000000)
|
||||
#define __KERNEL_ADDR_R __stringify(0x8a000000)
|
||||
#define __FDT_ADDR_R __stringify(0x90000000)
|
||||
#define __SCRIPT_ADDR_R __stringify(0x90100000)
|
||||
#define __PXEFILE_ADDR_R __stringify(0x90200000)
|
||||
#define __FDTOVERLAY_ADDR_R __stringify(0x90300000)
|
||||
#define __RAMDISK_ADDR_R __stringify(0x90400000)
|
||||
|
||||
#define STM32MP_MEM_LAYOUT \
|
||||
"kernel_addr_r=" __KERNEL_ADDR_R "\0" \
|
||||
"fdt_addr_r=" __FDT_ADDR_R "\0" \
|
||||
"scriptaddr=" __SCRIPT_ADDR_R "\0" \
|
||||
"pxefile_addr_r=" __PXEFILE_ADDR_R "\0" \
|
||||
"fdtoverlay_addr_r=" __FDTOVERLAY_ADDR_R "\0" \
|
||||
"ramdisk_addr_r=" __RAMDISK_ADDR_R "\0" \
|
||||
"kernel_comp_addr_r=" __KERNEL_COMP_ADDR_R "\0" \
|
||||
"kernel_comp_size=" __KERNEL_COMP_SIZE_R "\0"
|
||||
|
||||
#include <config_distro_bootcmd.h>
|
||||
#define CFG_EXTRA_ENV_SETTINGS \
|
||||
STM32MP_MEM_LAYOUT \
|
||||
STM32MP_BOOTCMD \
|
||||
BOOTENV \
|
||||
STM32MP_EXTRA \
|
||||
STM32MP_BOARD_EXTRA_ENV
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_STM32MP23_COMMMON_H */
|
||||
51
include/configs/stm32mp23_st_common.h
Normal file
51
include/configs/stm32mp23_st_common.h
Normal file
@ -0,0 +1,51 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (C) 2025, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* Configuration settings for the STMicroelectonics STM32MP23x boards
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_STM32MP23_ST_COMMON_H__
|
||||
#define __CONFIG_STM32MP23_ST_COMMON_H__
|
||||
|
||||
#define STM32MP_BOARD_EXTRA_ENV \
|
||||
"usb_pgood_delay=2000\0" \
|
||||
"console=ttySTM0\0"
|
||||
|
||||
#include <configs/stm32mp23_common.h>
|
||||
|
||||
#ifdef CFG_EXTRA_ENV_SETTINGS
|
||||
/*
|
||||
* default bootcmd for stm32mp23 STMicroelectronics boards:
|
||||
* for serial/usb: execute the stm32prog command
|
||||
* for mmc boot (eMMC, SD card), distro boot on the same mmc device
|
||||
* for nand or spi-nand boot, distro boot with ubifs on UBI partition or
|
||||
* sdcard
|
||||
* for nor boot, distro boot on SD card = mmc0 ONLY !
|
||||
*/
|
||||
#define ST_STM32MP23_BOOTCMD "bootcmd_stm32mp=" \
|
||||
"echo \"Boot over ${boot_device}${boot_instance}!\";" \
|
||||
"if test ${boot_device} = serial || test ${boot_device} = usb;" \
|
||||
"then stm32prog ${boot_device} ${boot_instance}; " \
|
||||
"else " \
|
||||
"run env_check;" \
|
||||
"if test ${boot_device} = mmc;" \
|
||||
"then env set boot_targets \"mmc${boot_instance}\"; fi;" \
|
||||
"if test ${boot_device} = nand ||" \
|
||||
" test ${boot_device} = spi-nand ;" \
|
||||
"then env set boot_targets ubifs0 mmc0; fi;" \
|
||||
"if test ${boot_device} = nor;" \
|
||||
"then env set boot_targets mmc0; fi;" \
|
||||
"run distro_bootcmd;" \
|
||||
"fi;\0"
|
||||
|
||||
#undef CFG_EXTRA_ENV_SETTINGS
|
||||
#define CFG_EXTRA_ENV_SETTINGS \
|
||||
STM32MP_MEM_LAYOUT \
|
||||
ST_STM32MP23_BOOTCMD \
|
||||
BOOTENV \
|
||||
STM32MP_EXTRA \
|
||||
STM32MP_BOARD_EXTRA_ENV
|
||||
|
||||
#endif
|
||||
#endif
|
||||
@ -2,7 +2,7 @@
|
||||
/*
|
||||
* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* Configuration settings for the STMicroelectonics STM32MP25x boards
|
||||
* Configuration settings for the STMicroelectronics STM32MP25x boards
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_STM32MP25_ST_COMMON_H__
|
||||
|
||||
Loading…
Reference in New Issue
Block a user