Enable support for environment in eMMC on STM32MP13xx DHCOR SoM,
in addition to existing support for environment in SPI NOR. The
environment size is the same, except in case the environment is
placed in eMMC, it is stored at the end of eMMC BOOT partitions
in the last 32 sectors of each eMMC HW BOOT partition.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
It is pointless to use the custom compatible "st,led1" when
stm32746g-eval.dts and stm32f769-disco.dts already contain the
"gpio-leds" compatible, which is specifically used for GPIO LEDs
management.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
It is pointless to use the custom compatible "st,button1" when
stm32746g-eval.dts and stm32f769-disco.dts already contain the
"gpio-keys" compatible, which is specifically used for button
management.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
LDO2 is expansion connector supply on STM32MP13xx DHCOR DHSBC rev.200.
LDO5 is carrier board supply on STM32MP13xx DHCOR DHSBC rev.200. Keep
both regulators always enabled to make sure both the carrier board and
the expansion connector is always powered on and supplied with correct
voltage.
Describe ST33TPHF2XSPI TPM 2.0 chip reset lines.
This is a port of Linux kernel patch posted at:
https://patchwork.kernel.org/project/linux-arm-kernel/patch/20250302152605.54792-1-marex@denx.de/
This change shall be removed when the Linux kernel DT change lands
and Linux kernel DTs get synchronized with U-Boot DTs.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
On STM32MP15xx with 1 GiB of DRAM, the gd->ram_top becomes 0,
because DRAM base 0xc0000000 + DRAM size 0x40000000 leads to
gd->ram_top overflow which resets it to 0. Handle this special
case simply by checking for gd->ram_top being zero, and if it
is, assume there is no addr >= gd->ram_top .
This fixes boot hang on STM32MP15xx with 1 GiB of DRAM.
Fixes: 25fb58e88aba ("ARM: stm32mp: Fix dram_bank_mmu_setup() for LMB located above ram_top")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
The lone user of the legacy USB device framework have been removed for
some time. Remove the final parts of the code that were missed.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20250227205101.4127604-1-trini@konsulko.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Instead of using the implementation specific struct jmp_buf_data use the
standard compliant type jmp_buf when switching exception levels.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Separate setjmp.h into an architecture independent part and an architecture
specific part. This simplifies moving from using struct jmp_buf_data
directly to using type jmp_buf in our code which is the C compliant way.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Don't assume that u32 and u64 are already defined.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
ulong is defined in linux/types.h use unsigned long instead.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
The existing memory layout places the bloblist at 0xb000 and the fdt at
0x100, resulting in a 0xaf00 size constraint for the fdt. This constraint
has been reached. Lets modify the layout by moving the bloblist to 0x100,
device tree to 0x1000 and placing early memory allocation after pre-console
buffer at 0xf4000. This should guarantee sufficient memory allocation for
future expansion.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Zynq:
- Guard code around SPL_FS_LOAD_PAYLOAD_NAME
Versal*:
- Remove tftp block size 4096
Versal:
- Use clocks per DT binding
- Store driver data in data section
Versal Gen 2:
- Fix major/minor version decoding
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Merge tag 'xilinx-for-v2025.04-rc4' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx changes for v2025.04-rc4
Zynq:
- Guard code around SPL_FS_LOAD_PAYLOAD_NAME
Versal*:
- Remove tftp block size 4096
Versal:
- Use clocks per DT binding
- Store driver data in data section
Versal Gen 2:
- Fix major/minor version decoding
With a recent Binman change, the skip-at-start property is now honoured,
meaning that all image-pos values in the affected section start from
the skip-at-start value.
The x86 code works around the old behaviour at present, so update it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Initialize MCU & MAIN Domain ESMs as a prerequisite to enable
watchdog reset functionality. The ESM aka error signalling module
is primarily responsible for sensing the watchdog reset event.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Baocheng Su <baocheng.su@siemens.com> says:
This introduces a sysinfo driver which also permits SMBIOS support.
The first 10 patches of v2 have already been applied. The remaining is
solely the sysinfo driver. To maintain consistency and ease of searching
through the history, the series title remains unchanged.
Link: https://lore.kernel.org/r/20250218023614.52574-1-baocheng.su@siemens.com
Drop the info structure parsing of the board in favor of our new sysinfo
driver to avoid code duplication.
Signed-off-by: Baocheng Su <baocheng.su@siemens.com>
Signed-off-by: Li Hua Qian <huaqian.li@siemens.com>
[Jan: rebasing, split-up, cleanup]
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
This brings a sysinfo driver and DT entry for the IOT2050 board series.
It translates the board information passed from SE-Boot to SPL into
values that can be retrieved via the sysinfo API. Will is already used
to fill the SMBIOS table when booting via EFI.
Signed-off-by: Baocheng Su <baocheng.su@siemens.com>
Signed-off-by: Li Hua Qian <huaqian.li@siemens.com>
[Jan: split-off as separate patch, cleanup]
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
The patch enables the second USB3.0 Type-A USB port on the NanoPi R4S
board, which prevents a crash when initializing the usb system in U-Boot
and allows both Type-A USB ports to be used for booting.
=> usb start
starting USB...
Bus usb@fe380000: USB EHCI 1.00
Bus usb@fe3c0000: "Synchronous Abort" handler, esr 0x96000010, far 0x0
Signed-off-by: Justin Klaassen <justin@tidylabs.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
BootROM leave GPIO4_D6 configured as SDMMC_PWREN function and DW MMC
driver set PWREN high in dwmci_init().
However, HW revision prior to v1.2 must pull GPIO4_D6 low to access
sdmmc. For HW revision v1.2 the state of GPIO4_D6 has no impact.
Upstream Linux commit 26c100232b09 "arm64: dts: rockchip: Fix sdmmc
access on rk3308-rock-s0 v1.1 boards" fixed this issue by adding a
vcc_sd regulator.
Include the new vcc_sd regulator in SPL and enable required Kconfig
options to set GPIO4_D6 low to fix reading sdmmc on v1.1 hw revision.
Fixes: 25438c40a007 ("board: rockchip: Add Radxa ROCK S0")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
There are some device-tree overlays with missing entries for the
keyfile. Add them to sign all images in the U-Boot FIT image.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
There are some device-tree overlays with missing entries for the
keyfile. Add them to sign all images in the U-Boot FIT image.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
The imx6q-lxr devicetree has landed in kernel 6.13.
Switch to OF_UPSTREAM to make use of the upstream devicetree.
Signed-off-by: Fabio Estevam <festevam@denx.de>
The device tree for imxrt1050 is now
available in the /dts/upstream directory.
Migrate board to use OF_UPSTREAM.
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
This function allows updating bootloader from u-boot
on production devices without need in host PC.
Be aware! It works only with re-crypt BCT and AES
encrypted devices.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Tegra 124 is fully compatible with existing Tegra pincontrol
driver, but it needs a specific MIPI PAD control pinconfig.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Since pinmux driver now is available for Tegra 2, these parts may
be removed from here and defined either in device tree or in
the device board files.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/24816
Please pull the SoCFPGA changes for next from u-boot-socfpga, containing
boot support for the Altera SoCFPGA Agilex 5 platform in U-Boot. The
changes include:
1. Board-specific configurations and setup required to enable Agilex 5
operation in U-Boot.
2. Integration of cache coherency unit (CCU) initialization routine,
including CCU conguration in DT.
3. Clock, firewall (configured in DT), SMMU, low level initialization
specific to Agilex 5.
4. Integration of memory initialization routine, including DDR setup.
This patch set has been tested on Agilex 5 devkit with QSPI boot
(UBI/UBIFS) and RAM boot (TFTP & ARM DS debugger).
Add board_boot_order() to retrieve the list of boot devices from
spl-boot-order property in device tree. This board_boot_order()
would be used for all Intel SOC64 devices.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Introduce a new symbol in the beginning of .data section in
the common ARMv8 linker script and use that as a reference
for data save and restore.
Previously, the code would rely on calculating the start of
the .data section address via data size, however, we observed
that the data size does not really reflect the SPL mapped
addresses.
In our case, the binman_sym section size was not included in
the data size, which will result in a wrong address for the
.data start section, which prevents us from properly saving
and restoring SPL data.
This approach skips the calculation for the starting address
of the .data section, and instead just defines the beginning
address of the .data section and calling the symbol as needed,
in which we think as a simpler and much more robust method.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
As cache is enabled in U-Boot and disabled in ATF(BL31). We need to
perform cache flush of buffers that are shared between U-Boot and
ATF using secure monitor calls.
Signed-off-by: Mahesh Rao <mahesh.rao@altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Board ID is exported as environment variable for use to boot Linux with FIT
configuration.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Update the print info per Agilex5
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Allow non-secure accesses only with SMMU peripherals. This would protect
the content in DDR secure region from accidentally modified by SMMU
peripherals.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
set/way instructions "dc cisw" which is used by the "dcache flush" command
only flushing CPU data caches from L1 -> L2 -> L3 to system memory cache in
cache coherency unit, hence this patch enables data flush from system
memory cache of CCU into DDR memory.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
These firewall configure settings are needed to disable firewall on
respective hardware component so both secure and non-secure transactions
are allowed.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
These configuration settings are required to enable cache maintenance and
access between initiators and targets.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Agilex5 supports both HPS handoff data and DDR handoff data.
Existing HPS handoff functions are restructured to support both existing
devices and Agilex5 device.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Status polling is used instead of using interrupt controller for Agilex5.
Disabling GICV3 in Agilex5 target, as well as disabling GICV2 enabled by
default for all SoCFPGA devices.
All the other SoCFPGA devices uses GICV2, thus enabling GICV2 in each of
the devices.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
There are 5 L4 watchdogs and one SDM triggered warm reset bit
in Agilex5 reset manager "stat" register where bit 16:20 for L4
watchdogs. Assigning value 1 to these bits in the register address
will initiate SDM to trigger warm reset.
Introducing new warm reset mask for Agilex5 to trigger warm reset
to all five L4 watchdogs.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Agilex5 retrieves its clock manager address via probing its own clock
driver model during SPL initialization.
Therefore, excluding Agilex5 from calling generic clock driver in misc
driver.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
