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arm: socfpga: misc: Exclude Agilex5 from clock manager base address retrieval
Agilex5 retrieves its clock manager address via probing its own clock driver model during SPL initialization. Therefore, excluding Agilex5 from calling generic clock driver in misc driver. Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
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parent
35638172f9
commit
6d07e1980c
@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
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* Copyright (C) 2012-2025 Altera Corporation <www.altera.com>
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*/
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#include <config.h>
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@ -248,15 +248,16 @@ void socfpga_get_managers_addr(void)
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if (ret)
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hang();
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#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
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ret = socfpga_get_base_addr("intel,agilex-clkmgr",
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&socfpga_clkmgr_base);
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#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
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ret = socfpga_get_base_addr("intel,n5x-clkmgr",
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&socfpga_clkmgr_base);
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#else
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ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
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#endif
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if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX))
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ret = socfpga_get_base_addr("intel,agilex-clkmgr",
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&socfpga_clkmgr_base);
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else if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X))
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ret = socfpga_get_base_addr("intel,n5x-clkmgr",
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&socfpga_clkmgr_base);
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else if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5))
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ret = socfpga_get_base_addr("altr,clk-mgr",
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&socfpga_clkmgr_base);
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if (ret)
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hang();
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}
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