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arm: socfpga: smc: Add memory coherency support to mailbox command

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As cache is enabled in U-Boot and disabled in ATF(BL31). We need to
perform cache flush of buffers that are shared between U-Boot and
ATF using secure monitor calls.

Signed-off-by: Mahesh Rao <mahesh.rao@altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
This commit is contained in:
Alif Zakuan Yuslaimi 2025-02-18 16:35:03 +08:00 committed by Tom Rini
parent 19f20cfc49
commit 034ebe3302
1 changed files with 10 additions and 2 deletions
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12
arch/arm/mach-socfpga/smc_api.c
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@ -1,9 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2020 Intel Corporation <www.intel.com>
* Copyright (C) 2025 Altera Corporation <www.altera.com>
*
*/
#include <cpu_func.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <linux/errno.h>
@ -40,10 +42,16 @@ int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
args[2] = len;
args[3] = urgent;
args[4] = (u64)resp_buf;
if (resp_buf_len)
if (arg && len > 0)
flush_dcache_range((uintptr_t)arg, (uintptr_t)arg + len);
if (resp_buf && resp_buf_len && *resp_buf_len > 0) {
args[5] = *resp_buf_len;
else
flush_dcache_range((uintptr_t)resp_buf, (uintptr_t)resp_buf + *resp_buf_len);
} else {
args[5] = 0;
}
ret = invoke_smc(INTEL_SIP_SMC_MBOX_SEND_CMD, args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp));