The way that the NAND driver under DM_NAND_ATMEL is probed is by the
dummy memory driver controlled by ATMEL_EBI. Rather than require that
for NAND to work both be enabled, make NAND select ATMEL_EBI and do not
prompt for ATMEL_EBI as it only triggers the probe for NAND.
Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
A large number of mtd drivers cannot build without access to some
platform specific header files. Express those requirements in Kconfig as
well.
Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Initialize mtd->writesize in nand_init() as otherwise
nand_page_size() returns 0 and this affects NAND read
operations.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
File system such as YAFFS2 need to know the number of available
OOB bytes per page to be able to choose if they should locate their
metadata in the data area or in the spare area.
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
The driver currently does:
mtd->dev->parent = cadence->dev;
This works in Linux because `struct mtd_info` embeds a `struct device`,
so `mtd->dev` is always valid and its `.parent` can be set.
In U-Boot, however, `mtd->dev` is only a pointer to a `struct udevice`.
Dereferencing it before assignment is invalid, which breaks the device
hierarchy. As a result, consumers relying on `mtd->dev` (e.g. partition
parser, reset and re-init paths) operate on a dangling pointer. This
leads to failures during warm reset when the NAND device is accessed
again.
Fix by assigning the device pointer directly:
mtd->dev = cadence->dev;
This matches U-Boot’s device model, preserves a valid hierarchy, and
resolves the warm reset issue on Cadence NAND.
Fixes: ebc41cad ("drivers: mtd: nand: Add driver for Cadence Nand")
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
As no platforms use this driver anymore let's go ahead and remove it.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
In mxs_nand_init_ctrl there are a couple of error paths that do not set
err which could lead to the errors being silently ignored despite the
function not completing. Rather than just using if to detect these
errors use err to collect the error return value from the called
functions.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
In denali_wait_for_irq the code will either return from inside the while
loop or exit with time_left being 0. The following test for time_left
being 0 is guranteed to be true so remove the test and the following
unreachable code.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
In init_nand_dma there was code to detect failure to allocate memory but
it had two problems. Firstly the 2nd clause when info->tx_desc was NULL
attempted to free info->tx_desc when it should be freeing info->rx_desc.
Secondly there was no detection of both allocations failing, arguably
the more likely scenario. Refactor the code to simplify it and just fail
as soon as either allocation fails.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Add kfree calls on error paths for memory that was allocated. This will
prevent memory leaks.
This issue found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-By: Michael Trimarchi <michael@amarulasolutions.com>
In stm32_fmc2_nfc_probe there are 3 error returns that do not set the
error code before returning which could lead to the error being silently
ignored. Just return -EINVAL in each case.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
In pxa3xx_nand_probe_dt if the function detects an error after
allocating memory that memory is not freed before exit. Add the
appropriate free.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: MIchael Trimarchi <michael@amarulasolutions.com>
E Shattow <e@freeshell.de> says:
Make consistent use of lowercase hexadecimal prefix '0x' throughout U-Boot.
There are a few remaining uses of uppercase 'X' to denote hexadecimal prefix
or placeholder in documentation and error messages.
External devicetree-rebasing dts/upstream and the generated code of
xilinx/zynq are ignored for the series.
Link: https://lore.kernel.org/r/20250606224558.1117422-1-e@freeshell.de
Use consistent lowercase hex prefix style in drivers/*
Does not change hex prefix case in allcaps uppercase style error messages
Signed-off-by: E Shattow <e@freeshell.de>
The clock driver allows to boost the NAND performance
controller. Make changes to let it use the new clock driver
=> time nand read ${loadaddr} kernel
NAND read: device 0 offset 0x500000, size 0x800000
8388608 bytes read: OK
time: 0.488 seconds
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Make simple the clock registration and enable and allow later
to add support for other platforms
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Andre Przywara <andre.przywara@arm.com> says:
C's implicit fallthrough behaviour in switch/case statements can lead to
subtle bugs. Quite some while ago many compilers introduced warnings in
those cases, requiring intentional fallthrough's to be annotated.
So far we were not enabling that compiler option, so many ambiguities
and some bugs in the code went unnoticed.
This series adds the required annotations in code paths that the first
stage of the U-Boot CI covers. There is a large number of cases left
in the libbz2 code. The usage of switch/case is borderline insane there,
labels are hidden in macros, and there are no breaks, but just goto's.
Upstream still uses very similar code, without any annotations. I still
am not 100% sure those are meant to fall through or not, and plan to do
further investigations, but didn't want to hold the rest of the patches
back. You can see for yourself by applying patch 18/18 and building for
sandbox64, for instance.
Because of this we cannot quite enable the warning in the Makefile yet,
but those fixes are worth regardless, and be it to increase readability.
Please note that those patches do not fix anything, really, they just add
those fallthrough annotations, so the series is not really critical.
Link: https://lore.kernel.org/r/20250327153313.2105227-1-andre.przywara@arm.com
The raw NAND flash code uses an implicit switch/case fallthrough to
share code when dealing with different ECC modes, and also when handling
some read command.
Add our "fallthrough;" statement-like macro before the respective labels
in the NAND code, to avoid a warning when GCC's -Wimplicit-fallthrough
warning option is enabled.
This copies the fallthrough annotations that the original kernel code
gained, before this function got refactored there.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Michael Trimrachi <michael@amarulasolutions.com>
If 'oob_required' is not set by the caller (for example 'oobbuf' is NULL),
then driver doesn't copy OOB data from 'oob_poi' to special controller
structures, so zeroes will be written as OOB. But, generic raw NAND logic
in 'nand_base.c' already handles case when OOB is not required to write by
filling 'oob_poi' with 0xFF's. So let's remove 'oob_required' check to
always read 'oob_poi' data for OOB.
Kernel driver (drivers/mtd/nand/raw/meson_nand.c) works in the same way,
so need to keep same behaviour here.
Fixes: c2e8c4d09a7a ("mtd: rawnand: Meson NAND controller support")
Signed-off-by: Arseniy Krasnov <avkrasnov@salutedevices.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Add SYS_NAND_PAGE_SIZE dependency for cadence NAND.
This config is needed as the SPL driver will use this parameter
to read uboot-proper image in NAND during booting.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Add support for spl nand to load binary image from NAND
to RAM. Leverage the existing nand_spl_load_image from nand_spl_loaders.c
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Enable nand to use bounce buffer. In bounce buffer,
read/write buf will use cadence->buf which has been allocated
using malloc. This will align the memory and avoid memory to be
allocated in different addresses.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Poll for thread complete status to ensure the
descriptor processing is complete. If complete then can ensure
controller already update the descriptor status.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Ensure ddr memory is updated with the data from dcache.
This would help to ensure cdma always reading the latest dma descriptor
from ddr memory.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Support NAND_CMD_SET_FEATURES & NAND_CMD_GET_FEATURES.
These commands is one of the basic commands of NAND. The parameters get
from these commands will be used to set timing mode
of NAND data interface.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Add support for reading param page of NAND device.
These paramaters are unique and used for identification purpose.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Add support for readid command in Cadence NAND driver.
The id is unique and used for flash identification.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Add support for read status command
in Cadence NAND driver. This status bit is important to check
whether the flash is write-protected.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Enable driver for Cadence NAND for the family
device agilex5. This driver is leveraged from the path
/drivers/mtd/nand/raw/cadence-nand-controller.c from the
stable version 6.11.2.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
From reading the S34ML02G1 and the SAM9X60 datasheets again, it seems
like we have to wait tREA after rising RE# before sampling the data.
Thus pulse time must be at least tREA.
Without this fix we got PMECC errors when reading, after switching to
ONFI timing mode 3 on SAM9X60 SoC with S34ML02G1 raw NAND flash chip.
The approach to set timings used before worked on sam9g20 and sama5d2
with the same flash (S34ML02G1), probably because those have a slower
mck clock rate and thus the resolution of the timings setup is not as
tight as with sam9x60.
The approach to fix the issue was carried over from at91bootstrap, and
has been successfully tested in at91bootstrap, U-Boot and Linux.
Link: https://github.com/linux4sam/at91bootstrap/issues/174
Cc: Li Bin <bin.li@microchip.com>
Signed-off-by: Alexander Dahl <ada@thorsis.com>
The condition 'ret' is always true as it is never set to other than
-EIO.
Remove 'ret' and the condition for copy.
Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com>
Reviewed-by: Michael Trimarchi <micheal@amarulasolutions.com>
Always probing pmecc in the generic nand controller probe function and
bailing out if pmecc is missing, prevents the driver to be usable for
SoCs which do not have a pmecc hardware ecc engine like older sam9 SoCs,
for example at91sam9g20. Tested on sam9x60 that the call, which the
comment was moved to, is sufficient to probe the pmecc.
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Update log level messages so that more critical messages can be logged
to console and help the troubleshooting with field devices.
This is a port of the upstream Linux patch to U-Boot.
https://lore.kernel.org/linux-mtd/20240223034758.13753-4-william.zhang@broadcom.com/
Signed-off-by: david regan <dregan@broadcom.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Anand Gore <anand.gore@broadcom.com>
Set parameter_page_big_endian to zero for bcmbca
Signed-off-by: david regan <dregan@broadcom.com>
Reviewed-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Anand Gore <anand.gore@broadcom.com>
These device specific nand driver files can be removed because
they are now replaced by a common driver bcmbca_nand.c
Signed-off-by: david regan <dregan@broadcom.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Anand Gore <anand.gore@broadcom.com>
The Broadcom BCA platforms are broadband access SoCs.
This is a port of the upstream Linux driver to U-Boot.
It was based on drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c
from Linux v6.11.
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
When ECC parameters are not specified in DT, first try ONFI ECC parameters
before fallback to maximum strength.
It's the Linux driver behavior since the driver rewriting in f88fc12.
From then 2 nand system refactors have been done in 6a1b66d6 and 53576c7b,
chip->ecc_strength_ds and chip->ecc_step_ds became
nanddev_get_ecc_requirements(). U-Boot didn't follow the refactor and
always use these 2 fields.
v2: Fix formatting, add upstream commit hash.
Signed-off-by: Zixun LI <zli@ogga.fr>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Balamanikandan Gunasundar
Simon Glass <sjg@chromium.org> says:
When the SPL build-phase was first created it was designed to solve a
particular problem (the need to init SDRAM so that U-Boot proper could
be loaded). It has since expanded to become an important part of U-Boot,
with three phases now present: TPL, VPL and SPL
Due to this history, the term 'SPL' is used to mean both a particular
phase (the one before U-Boot proper) and all the non-proper phases.
This has become confusing.
For a similar reason CONFIG_SPL_BUILD is set to 'y' for all 'SPL'
phases, not just SPL. So code which can only be compiled for actual SPL,
for example, must use something like this:
#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
In Makefiles we have similar issues. SPL_ has been used as a variable
which expands to either SPL_ or nothing, to chose between options like
CONFIG_BLK and CONFIG_SPL_BLK. When TPL appeared, a new SPL_TPL variable
was created which expanded to 'SPL_', 'TPL_' or nothing. Later it was
updated to support 'VPL_' as well.
This series starts a change in terminology and usage to resolve the
above issues:
- The word 'xPL' is used instead of 'SPL' to mean a non-proper build
- A new CONFIG_XPL_BUILD define indicates that the current build is an
'xPL' build
- The existing CONFIG_SPL_BUILD is changed to mean SPL; it is not now
defined for TPL and VPL phases
- The existing SPL_ Makefile variable is renamed to SPL_
- The existing SPL_TPL Makefile variable is renamed to PHASE_
It should be noted that xpl_phase() can generally be used instead of
the above CONFIGs without a code-space or run-time penalty.
This series does not attempt to convert all of U-Boot to use this new
terminology but it makes a start. In particular, renaming spl.h and
common/spl seems like a bridge too far at this point.
The series is fully bisectable. It has also been checked to ensure there
are no code-size changes on any commit.
Use PHASE_ as the symbol to select a particular XPL build. This means
that SPL_TPL_ is no-longer set.
Update the comment in bootstage to refer to this symbol, instead of
SPL_
Signed-off-by: Simon Glass <sjg@chromium.org>
These are a number of assorted upstream Linux fixes to the
BRCMNAND driver.
This patch set lowers the hamming distance between the Linux
and U-Boot drivers a bit as well, while we deviate quite
a bit it is still possible to bring fixes over thanks to
exercises like this.
The patches pass the pipeline CI:
https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/22535
