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https://source.denx.de/u-boot/u-boot.git
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Merge branch 'u-boot-nand-20241005' of https://gitlab.denx.de/u-boot/custodians/u-boot-nand-flash into next
These are a number of assorted upstream Linux fixes to the BRCMNAND driver. This patch set lowers the hamming distance between the Linux and U-Boot drivers a bit as well, while we deviate quite a bit it is still possible to bring fixes over thanks to exercises like this. The patches pass the pipeline CI: https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/22535
This commit is contained in:
Tom Rini
commit
28dc47038e
@ -25,6 +25,7 @@
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#include <linux/completion.h>
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#include <linux/errno.h>
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#include <linux/log2.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/rawnand.h>
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#include <asm/processor.h>
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#include <dm.h>
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@ -218,6 +219,7 @@ struct brcmnand_controller {
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const unsigned int *page_sizes;
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unsigned int page_size_shift;
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unsigned int max_oob;
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u32 ecc_level_shift;
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u32 features;
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/* for low-power standby/resume only */
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@ -544,6 +546,34 @@ enum {
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INTFC_CTLR_READY = BIT(31),
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};
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/***********************************************************************
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* NAND ACC CONTROL bitfield
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*
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* Some bits have remained constant throughout hardware revision, while
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* others have shifted around.
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***********************************************************************/
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/* Constant for all versions (where supported) */
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enum {
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/* See BRCMNAND_HAS_CACHE_MODE */
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ACC_CONTROL_CACHE_MODE = BIT(22),
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/* See BRCMNAND_HAS_PREFETCH */
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ACC_CONTROL_PREFETCH = BIT(23),
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ACC_CONTROL_PAGE_HIT = BIT(24),
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ACC_CONTROL_WR_PREEMPT = BIT(25),
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ACC_CONTROL_PARTIAL_PAGE = BIT(26),
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ACC_CONTROL_RD_ERASED = BIT(27),
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ACC_CONTROL_FAST_PGM_RDIN = BIT(28),
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ACC_CONTROL_WR_ECC = BIT(30),
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ACC_CONTROL_RD_ECC = BIT(31),
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};
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#define ACC_CONTROL_ECC_SHIFT 16
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/* Only for v7.2 */
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#define ACC_CONTROL_ECC_EXT_SHIFT 13
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static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
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{
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return brcmnand_readl(ctrl->nand_base + offs);
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@ -675,6 +705,12 @@ static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
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#endif /* __UBOOT__ */
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ctrl->features |= BRCMNAND_HAS_WP;
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/* v7.2 has different ecc level shift in the acc register */
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if (ctrl->nand_version == 0x0702)
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ctrl->ecc_level_shift = ACC_CONTROL_ECC_EXT_SHIFT;
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else
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ctrl->ecc_level_shift = ACC_CONTROL_ECC_SHIFT;
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return 0;
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}
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@ -733,6 +769,20 @@ static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl,
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__raw_writel(val, ctrl->nand_fc + word * 4);
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}
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static inline void brcmnand_read_data_bus(struct brcmnand_controller *ctrl,
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void __iomem *flash_cache, u32 *buffer, int fc_words)
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{
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struct brcmnand_soc *soc = ctrl->soc;
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int i;
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if (soc && soc->read_data_bus) {
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soc->read_data_bus(soc, flash_cache, buffer, fc_words);
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} else {
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for (i = 0; i < fc_words; i++)
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buffer[i] = brcmnand_read_fc(ctrl, i);
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}
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}
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static void brcmnand_clear_ecc_addr(struct brcmnand_controller *ctrl)
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{
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@ -844,30 +894,6 @@ static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
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return 0;
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}
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/***********************************************************************
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* NAND ACC CONTROL bitfield
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*
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* Some bits have remained constant throughout hardware revision, while
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* others have shifted around.
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***********************************************************************/
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/* Constant for all versions (where supported) */
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enum {
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/* See BRCMNAND_HAS_CACHE_MODE */
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ACC_CONTROL_CACHE_MODE = BIT(22),
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/* See BRCMNAND_HAS_PREFETCH */
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ACC_CONTROL_PREFETCH = BIT(23),
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ACC_CONTROL_PAGE_HIT = BIT(24),
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ACC_CONTROL_WR_PREEMPT = BIT(25),
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ACC_CONTROL_PARTIAL_PAGE = BIT(26),
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ACC_CONTROL_RD_ERASED = BIT(27),
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ACC_CONTROL_FAST_PGM_RDIN = BIT(28),
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ACC_CONTROL_WR_ECC = BIT(30),
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ACC_CONTROL_RD_ECC = BIT(31),
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};
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static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
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{
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if (ctrl->nand_version == 0x0702)
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@ -880,18 +906,15 @@ static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
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return GENMASK(4, 0);
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}
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#define NAND_ACC_CONTROL_ECC_SHIFT 16
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#define NAND_ACC_CONTROL_ECC_EXT_SHIFT 13
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static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl)
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{
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u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f;
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mask <<= NAND_ACC_CONTROL_ECC_SHIFT;
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mask <<= ACC_CONTROL_ECC_SHIFT;
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/* v7.2 includes additional ECC levels */
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if (ctrl->nand_version >= 0x0702)
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mask |= 0x7 << NAND_ACC_CONTROL_ECC_EXT_SHIFT;
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if (ctrl->nand_version == 0x0702)
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mask |= 0x7 << ACC_CONTROL_ECC_EXT_SHIFT;
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return mask;
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}
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@ -905,8 +928,8 @@ static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)
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if (en) {
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acc_control |= ecc_flags; /* enable RD/WR ECC */
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acc_control |= host->hwcfg.ecc_level
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<< NAND_ACC_CONTROL_ECC_SHIFT;
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acc_control &= ~brcmnand_ecc_level_mask(ctrl);
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acc_control |= host->hwcfg.ecc_level << ctrl->ecc_level_shift;
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} else {
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acc_control &= ~ecc_flags; /* disable RD/WR ECC */
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acc_control &= ~brcmnand_ecc_level_mask(ctrl);
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@ -957,6 +980,43 @@ static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)
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nand_writereg(ctrl, acc_control_offs, tmp);
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}
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static int brcmnand_get_spare_size(struct brcmnand_host *host)
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{
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struct brcmnand_controller *ctrl = host->ctrl;
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u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
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BRCMNAND_CS_ACC_CONTROL);
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u32 acc = nand_readreg(ctrl, acc_control_offs);
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return (acc & brcmnand_spare_area_mask(ctrl));
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}
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static void brcmnand_get_ecc_settings(struct brcmnand_host *host, struct nand_chip *chip)
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{
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struct brcmnand_controller *ctrl = host->ctrl;
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u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
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BRCMNAND_CS_ACC_CONTROL);
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bool sector_size_1k = brcmnand_get_sector_size_1k(host);
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int spare_area_size, ecc_level;
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u32 acc;
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spare_area_size = brcmnand_get_spare_size(host);
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acc = nand_readreg(ctrl, acc_control_offs);
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ecc_level = (acc & brcmnand_ecc_level_mask(ctrl)) >> ctrl->ecc_level_shift;
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if (sector_size_1k)
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chip->ecc.strength = ecc_level * 2;
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else if (spare_area_size == 16 && ecc_level == 15)
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chip->ecc.strength = 1; /* hamming */
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else
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chip->ecc.strength = ecc_level;
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if (chip->ecc.size == 0) {
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if (sector_size_1k)
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chip->ecc.size = 1024;
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else
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chip->ecc.size = 512;
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}
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}
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/***********************************************************************
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* CS_NAND_SELECT
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***********************************************************************/
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@ -1003,6 +1063,14 @@ static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl,
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} while (get_timer(base) < limit);
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#endif /* __UBOOT__ */
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/*
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* do a final check after time out in case the CPU was busy and the driver
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* did not get enough time to perform the polling to avoid false alarms
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*/
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val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
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if ((val & mask) == expected_val)
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return 0;
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dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n",
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expected_val, val & mask);
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@ -1318,19 +1386,33 @@ static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i,
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const u8 *oob, int sas, int sector_1k)
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{
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int tbytes = sas << sector_1k;
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int j;
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int j, k = 0;
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u32 last = 0xffffffff;
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u8 *plast = (u8 *)&last;
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/* Adjust OOB values for 1K sector size */
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if (sector_1k && (i & 0x01))
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tbytes = max(0, tbytes - (int)ctrl->max_oob);
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tbytes = min_t(int, tbytes, ctrl->max_oob);
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for (j = 0; j < tbytes; j += 4)
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/*
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* tbytes may not be multiple of words. Make sure we don't read out of
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* the boundary and stop at last word.
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*/
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for (j = 0; (j + 3) < tbytes; j += 4)
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oob_reg_write(ctrl, j,
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(oob[j + 0] << 24) |
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(oob[j + 1] << 16) |
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(oob[j + 2] << 8) |
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(oob[j + 3] << 0));
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/* handle the remaing bytes */
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while (j < tbytes)
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plast[k++] = oob[j++];
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if (tbytes & 0x3)
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oob_reg_write(ctrl, (tbytes & ~0x3), (__force u32)cpu_to_be32(last));
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return tbytes;
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}
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@ -1781,7 +1863,7 @@ static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
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{
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struct brcmnand_host *host = nand_get_controller_data(chip);
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struct brcmnand_controller *ctrl = host->ctrl;
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int i, j, ret = 0;
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int i, ret = 0;
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brcmnand_clear_ecc_addr(ctrl);
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@ -1794,8 +1876,8 @@ static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
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if (likely(buf)) {
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brcmnand_soc_data_bus_prepare(ctrl->soc, false);
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for (j = 0; j < FC_WORDS; j++, buf++)
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*buf = brcmnand_read_fc(ctrl, j);
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brcmnand_read_data_bus(ctrl, ctrl->nand_fc, buf, FC_WORDS);
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buf += FC_WORDS;
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brcmnand_soc_data_bus_unprepare(ctrl->soc, false);
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}
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@ -2225,7 +2307,7 @@ static int brcmnand_set_cfg(struct brcmnand_host *host,
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tmp &= ~brcmnand_ecc_level_mask(ctrl);
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tmp &= ~brcmnand_spare_area_mask(ctrl);
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if (ctrl->nand_version >= 0x0302) {
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tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
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tmp |= cfg->ecc_level << ctrl->ecc_level_shift;
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tmp |= cfg->spare_area_size;
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}
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nand_writereg(ctrl, acc_control_offs, tmp);
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@ -2274,14 +2356,37 @@ static int brcmnand_setup_dev(struct brcmnand_host *host)
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{
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struct mtd_info *mtd = nand_to_mtd(&host->chip);
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struct nand_chip *chip = &host->chip;
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struct nand_device *nanddev = mtd_to_nanddev(mtd);
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struct nand_memory_organization *memorg = nanddev_get_memorg(nanddev);
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struct brcmnand_controller *ctrl = host->ctrl;
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struct brcmnand_cfg *cfg = &host->hwcfg;
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char msg[128];
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u32 offs, tmp, oob_sector;
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bool use_strap = false;
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char msg[128];
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int ret;
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memset(cfg, 0, sizeof(*cfg));
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#ifndef __UBOOT__
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use_strap = of_property_read_bool(nand_get_flash_node(chip),
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"brcm,nand-ecc-use-strap"):
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#else
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use_strap = ofnode_read_bool(nand_get_flash_node(chip),
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"brcm,nand-ecc-use-strap");
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#endif /* __UBOOT__ */
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/*
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* Either nand-ecc-xxx or brcm,nand-ecc-use-strap can be set. Error out
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* if both exist.
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*/
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if (chip->ecc.strength && use_strap) {
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dev_err(ctrl->dev,
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"ECC strap and DT ECC configuration properties are mutually exclusive\n");
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return -EINVAL;
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}
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if (use_strap)
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brcmnand_get_ecc_settings(host, chip);
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#ifndef __UBOOT__
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ret = of_property_read_u32(nand_get_flash_node(chip),
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"brcm,nand-oob-sector-size",
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@ -2291,20 +2396,25 @@ static int brcmnand_setup_dev(struct brcmnand_host *host)
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"brcm,nand-oob-sector-size",
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&oob_sector);
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#endif /* __UBOOT__ */
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if (ret) {
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/* Use detected size */
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cfg->spare_area_size = mtd->oobsize /
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(mtd->writesize >> FC_SHIFT);
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if (use_strap)
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cfg->spare_area_size = brcmnand_get_spare_size(host);
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else
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/* Use detected size */
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cfg->spare_area_size = mtd->oobsize /
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(mtd->writesize >> FC_SHIFT);
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} else {
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cfg->spare_area_size = oob_sector;
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}
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if (cfg->spare_area_size > ctrl->max_oob)
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cfg->spare_area_size = ctrl->max_oob;
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/*
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* Set oobsize to be consistent with controller's spare_area_size, as
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* the rest is inaccessible.
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* Set mtd and memorg oobsize to be consistent with controller's
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* spare_area_size, as the rest is inaccessible.
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*/
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mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT);
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memorg->oobsize = mtd->oobsize;
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cfg->device_size = mtd->size;
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cfg->block_size = mtd->erasesize;
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@ -2796,8 +2906,17 @@ int brcmnand_probe(struct udevice *dev, struct brcmnand_soc *soc)
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/* Disable XOR addressing */
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brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0);
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/* Check if the board connects the WP pin */
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#ifndef __UBOOT__
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if (of_property_read_bool(dn, "brcm,wp-not-connected"))
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#else
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if (dev_read_bool(ctrl->dev, "brcm,wp-not-connected"))
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#endif /* __UBOOT__ */
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wp_on = 0;
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/* Read the write-protect configuration in the device tree */
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wp_on = dev_read_u32_default(dev, "write-protect", wp_on);
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if (dev_read_bool(ctrl->dev, "write-protect"))
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wp_on = dev_read_u32_default(dev, "write-protect", wp_on);
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if (ctrl->features & BRCMNAND_HAS_WP) {
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/* Permanently disable write protection */
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@ -11,6 +11,8 @@ struct brcmnand_soc {
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void (*ctlrdy_set_enabled)(struct brcmnand_soc *soc, bool en);
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void (*prepare_data_bus)(struct brcmnand_soc *soc, bool prepare,
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bool is_param);
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void (*read_data_bus)(struct brcmnand_soc *soc, void __iomem *flash_cache,
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u32 *buffer, int fc_words);
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void *ctrl;
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};
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