This is a PC-like platform board.
Enable drivers for most on-board devices to make it useful.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Some drivers need this header.
Provide this dummy header as riscv did.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
In-line ECC support was added for LPDDR by reserving the last one-eighth
of the memory space for ECC data. Full memory initialization using the
BIST MEM INIT mailbox command, based on address and size, is required to
correctly generate ECC data and enable proper ECC logic verification.
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Cache allocation for dirty writes in the CCU system cache was disabled
for performance optimization.
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
LMB_ARCH_MEM_MAP is enabled, and lmb_arch_add_memory() is introduced to
correctly handle memory reservations for the second and third DDR
memory banks.
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
As of 2025, Altera is now a standalone company prior to
being a subsidiary of Intel Corporation.
Update CPU info printout naming from Intel to Altera.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Use GPIO hogging method in device tree to set SDIO_SEL pin (portb3)
direction as output with value 0 after power-on reset.
This is to ensure stable 0V voltage reading from SDIO_SEL GPIO pin
after board init.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
The use of both "imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION" and
"imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE" here is wrong as
those are both part of the same choice statement. Furthermore you cannot
select/imply something from a choice statement, it must be a "default ...
if ..." construct within the choice statement in question.
Signed-off-by: Tom Rini <trini@konsulko.com>
Vendor Authorized Boot flow configurations are enabled for boards
based on Agilex5 SoCFPGA. Also, required changes are made to the
SoCFPGA make file for building and linking relevant secure source
code files.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Load and entry addresses are corrected for Agilex5 SoCFPGA board
which would enable to generate the kernel itb file with the right
addresses.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Send out "HPS_STAGE_NOTIFY" mailbox command to the
Secure Device Manager (SDM) in SPL to inform SDM on
FSBL execution.
This is necessary for the SDM to recognize that the
FSBL stage has begun its execution and should be
made as early as possible in the FSBL process.
Therefore, the mailbox will initialize and send out
the notification right after the completion of timer
initialization.
Signed-off-by: Mahesh Rao <mahesh.rao@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Enable reset support for FPGA2SDRAM bridge for Stratix10, as well as
FPGA2SoC and SoC2FPGA bridges for all SoC64 families.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Add reset manager registers in preparation for F2S bridge reset
support as well as the mask support to enable/disable the bridges.
Mask value:
BIT0: soc2fpga
BIT1: lwhps2fpga
BIT2: fpga2soc
These bridges are available only in Stratix10:
BIT3: f2sdram0
BIT4: f2sdram1
BIT5: f2sdram2
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Introducing a new mailbox command "HPS_STAGE_NOTIFY" to notify Secure
Device Manager (SDM) on the stage of HPS code execution.
Generally, there are three main code execution stages: First Stage Boot
Loader (FSBL) which is U-Boot SPL, Second Stage Boot Loader (SSBL) which
is U-Boot, and the Operating System (OS) which is Linux.
This enables the user to query the SDM for HPS error details.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Merge tag 'u-boot-at91-2025.07-b' of https://source.denx.de/u-boot/custodians/u-boot-at91
Second set of u-boot-at91 features for the 2025.07 cycle:
This feature set includes the addition of sam9x60 usb gadget, and a fix
for sama5d2 SPL.
MIPS_RELOCATION_TABLE_SIZE=0x8000 is too small to enable UNIT_TEST.
Increase it by 50 % (16 KiB).
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Since commit f98cd471f06b ("clk: clk-composite: Resolve parent clock by
name") the StarFive VisionFive 2 board fails to boot.
Before that patch the SPL debug UART showed warnings like:
clk_register: failed to get pll0_out device (parent of perh_root)
clk_register: failed to get pll0_out device (parent of qspi_ref_src)
clk_register: failed to get pll0_out device (parent of usb_125m)
clk_register: failed to get pll0_out device (parent of gmac_src)
clk_register: failed to get pll0_out device (parent of gmac1_gtxclk)
clk_register: failed to get pll0_out device (parent of gmac0_gtxclk)
The &pllclk clock needs to be enabled early.
Fixes: f98cd471f06b ("clk: clk-composite: Resolve parent clock by name")
Suggested-by: Marek Vasut <marex@denx.de>
Tested-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
The PIT timer needs to be available early in the SPL phase,
otherwise SPL fails to boot and only prints:
Could not initialize timer (err -96)
Fix this problem by passing 'bootph-all' to the sama5d2 PIT node.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Add the USB gadget DT node for the sam9x60 SoC's.
Signed-off-by: Zixun LI <admin@hifiphile.com>
Reviewed-by: Eugen Hristev <eugen.hristev@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
CU_CLKOUT0 can be driven by two input clocks: a 25 MHz and a 50 MHz source.
Currently, the 25 MHz option is not selectable due to an incorrect mux
configuration where the 50 MHz clock is duplicated in the parent list.
This patch fixes the mux setup, allowing proper selection of the 25 MHz
clock source for MCU_CLKOUT0.
Similar configuration is already correctly implemented in AM62 clock
data for 'hsdiv4_16fft_main_2_hsdivout1_clk10', where MCU_CLKOUT0
parent switching behaves as expected.
Link: http://downloads.ti.com/tisci/esd/latest/5_soc_doc/am62px/clocks.html#clocks-for-board0-device
Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Add eMMC nodes with the fixed regulator and fixed clock. It's also
needed to assign the clock and set it to 200MHz as it's set to 150Mhz by
default.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
This commit adds support for the brcp1, brsmarc2, brcp150 and brcp170
boards. This boards are based on the Xilinx Zynq SoC.
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20250404072819.69642-5-bernhard.messerklinger@br-automation.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
The source code for the versal loadpdi command and the
CONFIG_CMD_VERSAL configuration has been removed. It now utilizes
the fpga load <dev> <address> <length> command to load secure &
non-secure pdi images.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Link: https://lore.kernel.org/r/20250327105200.1262615-4-prasad.kummari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Add support for loading the secure & non-secure pdi images and PL
bitstream on the Versal Gen2 platform. The FPGA driver is enabled
to load the bitstream in PDI format on the AMD Versal Gen2 device.
PDI is the new programmable device image format for Versal Gen2,
and the bitstream for the Versal Gen2 platform is generated exclusively
in this format.
With the enhanced SMC format in TF-A ensuring transparent payload
forwarding for Versal Gen2, the u-boot driver must now handle the
word swapping of PDI address that was previously done in TF-A for
this API. The source code for the Versal2 loadpdi command and the
CONFIG_CMD_VERSAL2 configuration has been removed. It now utilizes
the fpga load <dev> <address> <length> command to load secure &
non-secure pdi images.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Link: https://lore.kernel.org/r/20250327105200.1262615-3-prasad.kummari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Add support for loading the secure & non-secure pdi images and
PL bitstream on the Versal NET platform. The FPGA driver is enabled
to load the bitstream in PDI format on the AMD Versal NET device.
PDI is the new programmable device image format for Versal NET,
and the bitstream for the Versal NET platform is generated exclusively
in this format.
The source code for the versalnet loadpdi command and the
CONFIG_CMD_VERSAL_NET configuration has been removed. It now utilizes
the fpga load <dev> <address> <length> command to load secure &
non-secure pdi images.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Link: https://lore.kernel.org/r/20250327105200.1262615-2-prasad.kummari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Update the firmware driver UFS APIs zynqmp_pm_ufs_* to directly
read/write to the pmc_iou_slcr and efuse_cache registers. Replace
these raw reads/writes with the xilinx_pm_request() API with the
correct arguments once the PM related changes are done.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ee2d1ad2e07e96f1948ab6ffe8f3c50a3b8f9be9.1742462001.git.michal.simek@amd.com
Adjust configuration and devicetree so the topic-miami board actually
boots.
Replace the custom scripting and just use distro_boot. Override the
standard zynq routines.
The board attempts to boot from SD card first, and falls back to booting
UBIFS from the QSPI NOR flash.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Link: https://lore.kernel.org/r/20250312153741.24007-2-mike.looijmans@topic.nl
Signed-off-by: Michal Simek <michal.simek@amd.com>
Added extended support for retrieving the PMC muti boot mode
register via the firmware interface, which is preferred when
U-Boot runs in EL2 and cannot directly access PMC registers
via raw reads. Ideally, all secure registers should be accessed
via xilinx_pm_request(). Introduced the secure
zynqmp_pm_get_pmc_multi_boot_reg() call, which uses
xilinx_pm_request() to read the PMC multi boot mode register.
BootROM increments the MultiBoot register (PMC_MULTI_BOOT) read
address offset by 32 KB and retries. For SD and eMMC boot modes,
it can search up to 8191 FAT files for the identification string.
A 13-bit mask (0x1FFF) is applied to PMC_MULTI_BOOT_MASK to obtain
the correct values in BootROM.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Link: https://lore.kernel.org/r/20250305134845.3182193-1-prasad.kummari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Add the UFS boot mode support and update the boot_targets with
ufs mode. If the UFS device is not accessible from APU and
running this is detected as a warning, as the device is not
accessible.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250225032806.1842581-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Turn anonymous enum TCM_LOCK/TCM_SPLIT into enum tcm_mode {}, set
TCM_LOCK as 0 and TCM_SPLIT as 1 to match LOCK and SPLIT macros in
mach-zynqmp/mp.c, and unify all the functions and their parameters
on this one single enum tcm_mode {} instead of a mix of bool and u8.
No functional change intended.
Signed-off-by: Marek Vasut <marex@denx.de>
Tested-by: Love Kumar <love.kumar@amd.com>
Link: https://lore.kernel.org/r/20250206213039.42756-1-marex@denx.de
Signed-off-by: Michal Simek <michal.simek@amd.com>
As the code is today, we get a warning about "select" statements on
"choice" options not doing anything. However, it also works as intended
because SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is the default option
within that choice statement. To guard against future regressions, make
the choice statement in common/spl/Kconfig have an explicit default if
MVEBU_SPL_BOOT_DEVICE_MMC.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Much like what was fixed on the AM62x and AM62Px platforms[0]. The
CU_CLKOUT0 has two (25mhz and 50mhz) mux options however the clock
structure incorrectly duplicated the first 50mhz option twice. Fix this
for the AM62A platforms so the 25mhz option is selectable.
[0] https://lore.kernel.org/all/20250408161211.3165588-1-parth105105@gmail.com/
Reported-by: Parth Pancholi <parth.pancholi@toradex.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
When FIT image with multiple dtbs are involved for R5 boot process,
R5 SPL starts off with the first instance of dtb to probe the
eeprom, then once we have identified the type of board, invocation
of setup_multi_dtb_fit will replace the gd->fdt_blob with the proper
board dtb match. However, when we do this, two things happen:
a) Prior to the invocation of setup_multi_dtb_fit, as part of the eeprom
discovery process, i2c controller device is already probed and marked
as exclusive with the match of the very first tisci match (from the
original boot dtb). This list is stored in the info->dev_list of the
first probe.
b) When the second dtb is loaded, tisci is probed again (since this is a
new node) and the new info->dev_list is empty.
At this stage, the exclusive devices such as i2c instances used to
probe the board information is left in the old info->dev_list that is
no longer used actively by the system using the replaced dtb.
As a result of this, the cleanup we intend to do with
ti_sci_cmd_release_exclusive_devices is no longer complete and
leaves the instances such as i2c for eeprom marked used as we scan just
the new info->dev_list.
This creates a problem when Device Manager(DM) firmware starts up later
on in the boot process and identifies that this instance of i2c is
already marked active, so it assumes this can no longer be controlled
by software and is marked internally as reserved and HLOS can no
longer control these instances. This defeated the purpose of
ti_sci_cmd_release_exclusive_devices.
NOTE: This scheme works just fine if the FIT has just a single dtb as
the info->dev_list is upto date.
To fix this, let us make ti_sci_cmd_release_exclusive_devices scan the
all registrations of tisci instances and cleanup all exclusive devices
that have ever been registered.
As part of this, change the prototype of release_exclusive_devices to
drop the handle since that has no further meaning now.
Though this issue was identified on AM64-sk, this can be present in
other builds which use multi-fit-dtb for R5 SPL startup.
Fixes: 9566b777ae0a ("firmware: ti_sci: Add a command for releasing all exclusive devices")
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Jerome Forissier <jerome.forissier@linaro.org> says:
This series replaces the dynamic initcalls (with function pointers) with
static calls, and gets rid of initcall_run_list(), init_sequence_f,
init_sequence_f_r and init_sequence_r. This makes the code simpler and the
binary slighlty smaller: -2281 bytes/-0.21 % with LTO enabled and -510
bytes/-0.05 % with LTO disabled (xilinx_zynqmp_kria_defconfig).
Execution time doesn't seem to change noticeably. There is no impact on
the SPL.
The inline assembly fixes, although they look unrelated, are triggered
on some platforms with LTO enabled. For example: kirkwood_defconfig.
CI: https://source.denx.de/u-boot/custodians/u-boot-net/-/pipelines/25514
Link: https://lore.kernel.org/r/20250404135038.2134570-1-jerome.forissier@linaro.org
Change board_init_f(), board_init_f_r() and board_init_r() to make
static calls instead of iterating over the init_sequence_f,
init_sequence_f_r and init_sequence_r arrays, respectively. This makes
the code a simpler (and even more so when initcall_run_list() is
later removed) and it reduces the binary size as well. Tested with
xilinx_zynqmp_kria_defconfig; bloat-o-meter results:
- With LTO
add/remove: 106/196 grow/shrink: 10/28 up/down: 31548/-33829 (-2281)
Total: Before=1070471, After=1068190, chg -0.21%
- Without LTO
add/remove: 0/54 grow/shrink: 3/0 up/down: 2322/-2832 (-510)
Total: Before=1121723, After=1121213, chg -0.05%
Execution time does not change in a noticeable way.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
The mcr and msr instructions are available in Thumb mode only if
Thumb2 is supported. Therefore, if __thumb2__ is not set, make
sure we switch to ARM mode by inserting a .arm directive in the
inline assembly.
Fixes LTO link errors with kirkwood platforms, triggered by a later
commit:
tools/buildman/buildman -o /tmp/build -eP sheevaplug
[...]
{standard input}:24085: Error: selected processor does not support `mrc p15,0,r3,c1,c0,0' in Thumb mode
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
UART-A can be exposed through uSD, this was tested on Transformer T20
but should work on all Ventana-based boards.
TX is exported on SDD pingroup corresponding to uSD CLK pin
RX is exported on SDB which is CMD pin in uSD slot
Signed-off-by: Artur Kowalski <arturkow2000@gmail.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
The Tegra Note 7 is a mini tablet computer and the second Tegra 4
based mobile device designed by Nvidia that runs the Android operating
system. The Tegra Note has a 7" IPS display with 1280 x 800 (217 ppi)
resolution. The 1 GB of RAM and 16 GB of internal memory can be
supplemented with a microSDXC card giving up to 64 GB of additional
storage.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
The ASUS Transformer Pad TF701T is an Android tablet computer made by
ASUS, successor to the ASUS Transformer Pad Infinity. The tablet includes
a Tegra 4 T114 processor clocked at 1.9 GHz, and an upgraded 2560×1600
pixel resolution screen, increasing the pixel density to 300 PPI and
a mobile dock. Transformers (t114) board derives from Nvidia Macallan
development board.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
The clock initialization routine sets the DISP* clock parent to PLLC,
resulting in DC failure in the case when PLLD was previously configured.
This issue disrupts chainloading and to prevent failures caused by DISP*
clock parent conflicts, clock initialization should not modify DISP*. The
DC driver handles DISP* configuration.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
