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arm: socfpga: mailbox: Notify SDM on HPS code execution stages

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Introducing a new mailbox command "HPS_STAGE_NOTIFY" to notify Secure
Device Manager (SDM) on the stage of HPS code execution.

Generally, there are three main code execution stages: First Stage Boot
Loader (FSBL) which is U-Boot SPL, Second Stage Boot Loader (SSBL) which
is U-Boot, and the Operating System (OS) which is Linux.

This enables the user to query the SDM for HPS error details.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
This commit is contained in:
Alif Zakuan Yuslaimi 2025-03-10 23:38:51 -07:00 committed by Tien Fong Chee
parent 9aa85e01a4
commit ef16992e3e
2 changed files with 16 additions and 0 deletions
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4
arch/arm/mach-socfpga/include/mach/mailbox_s10.h
View File

@ -128,6 +128,7 @@ enum ALT_SDM_MBOX_RESP_CODE {
#define MBOX_QSPI_CLOSE 51
#define MBOX_QSPI_DIRECT 59
#define MBOX_REBOOT_HPS 71
#define MBOX_HPS_STAGE_NOTIFY 93
/* Mailbox registers */
#define MBOX_CIN 0 /* command valid offset */
@ -385,6 +386,8 @@ enum MBOX_CFGSTAT_MINOR_ERR_CODE {
#define RCF_SOFTFUNC_STATUS_SEU_ERROR BIT(3)
#define RCF_PIN_STATUS_NSTATUS BIT(31)
#define HPS_EXECUTION_STATE_FSBL 0
int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent,
u32 *resp_buf_len, u32 *resp_buf);
int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
@ -401,6 +404,7 @@ int mbox_qspi_open(void);
#endif
int mbox_reset_cold(void);
int mbox_hps_stage_notify(u32 execution_stage);
int mbox_get_fpga_config_status(u32 cmd);
int mbox_get_fpga_config_status_psci(u32 cmd);
#endif /* _MAILBOX_S10_H_ */

12
arch/arm/mach-socfpga/mailbox_s10.c
View File

@ -6,6 +6,7 @@
#include <asm/arch/clock_manager.h>
#include <asm/arch/mailbox_s10.h>
#include <asm/arch/smc_api.h>
#include <asm/arch/system_manager.h>
#include <asm/global_data.h>
#include <asm/io.h>
@ -474,6 +475,17 @@ int __secure mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len,
urgent, resp_buf_len, resp_buf);
}
int mbox_hps_stage_notify(u32 execution_stage)
{
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
return smc_send_mailbox(MBOX_HPS_STAGE_NOTIFY, 1, &execution_stage,
0, 0, NULL);
#else
return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_HPS_STAGE_NOTIFY,
MBOX_CMD_DIRECT, 1, &execution_stage, 0, 0, NULL);
#endif
}
int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg)
{
return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg);