CI: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=390&view=results

- mvebu_espressobin_ultra-88f3720_defconfig: disable SATA
- helios4: enable ddr odt0 on write for both chip-select
- clearfog,helios4: disable sdhci sdma
- mvebu/bubt: Correct usage of IS_ENABLED() macro
- mvebu: Correct SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR usage
This commit is contained in:
Tom Rini 2025-04-16 08:12:30 -06:00
commit da4dd9ed7a
9 changed files with 9 additions and 10 deletions

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@ -260,7 +260,7 @@ config DDR_LOG_LEVEL
failure, RL, WL errors and other algorithm failure. At level 1,
provides the D-Unit setup (SPD/Static configuration). At level 2,
provides the windows margin as a results of DQS centeralization.
At level 3, rovides the windows margin of each DQ as a results of
At level 3, provides the windows margin of each DQ as a results of
DQS centeralization.
config DDR_IMMUTABLE_DEBUG_SETTINGS
@ -394,7 +394,6 @@ config MVEBU_SPL_BOOT_DEVICE_MMC
imply SPL_LIBDISK_SUPPORT
imply SPL_MMC
select SUPPORT_EMMC_BOOT if SPL_MMC
select SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR if SPL_MMC
select SPL_BOOTROM_SUPPORT
config MVEBU_SPL_BOOT_DEVICE_SATA
@ -450,7 +449,7 @@ config MVEBU_EFUSE_VHV_GPIO
string "VHV_Enable GPIO name for eFuse programming"
depends on MVEBU_EFUSE && !ARMADA_3700
help
The eFuse programing (burning) phase requires supplying 1.8V to the
The eFuse programming (burning) phase requires supplying 1.8V to the
device on the VHV power pin, while for normal operation the VHV power
rail must be left unconnected. See Marvell AN-389: ARMADA VHV Power
document (Doc. No. MV-S302545-00 Rev. C, August 2, 2016) for details.

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@ -73,7 +73,11 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
{0} /* timing parameters */
{0}, /* timing parameters */
{ {0} }, /* electrical configuration */
{0,}, /* electrical parameters */
0x30000, /* ODT configuration */
0x3, /* clock enable mask */
};
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)

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@ -931,7 +931,7 @@ static int check_image_header(void)
size = le32_to_cpu(hdr->blocksize);
if (hdr->blockid == 0x78) { /* SATA id */
struct blk_desc *blk_dev = IS_ENABLED(BLK) ? blk_get_devnum_by_uclass_id(UCLASS_SCSI, 0) : NULL;
struct blk_desc *blk_dev = IS_ENABLED(CONFIG_BLK) ? blk_get_devnum_by_uclass_id(UCLASS_SCSI, 0) : NULL;
unsigned long blksz = blk_dev ? blk_dev->blksz : 512;
offset *= blksz;
}

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@ -537,6 +537,7 @@ if SPL_SYS_MMCSD_RAW_MODE
choice
prompt "Method for locating next phase of boot (e.g. U-Boot)"
default SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR if MVEBU_SPL_BOOT_DEVICE_MMC
config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
bool "MMC raw mode: by sector"

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@ -61,7 +61,6 @@ CONFIG_SYS_I2C_MVTWSI=y
CONFIG_I2C_EEPROM=y
CONFIG_SPL_I2C_EEPROM=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y

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@ -62,7 +62,6 @@ CONFIG_I2C_EEPROM=y
CONFIG_SPL_I2C_EEPROM=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y

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@ -62,7 +62,6 @@ CONFIG_I2C_EEPROM=y
CONFIG_SPL_I2C_EEPROM=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y

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@ -61,7 +61,6 @@ CONFIG_SYS_I2C_MVTWSI=y
CONFIG_I2C_EEPROM=y
CONFIG_SPL_I2C_EEPROM=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y

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@ -34,7 +34,6 @@ CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SATA=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_WDT=y