101298 Commits

Author SHA1 Message Date
Andrew Goodbody
34bc71f2db net: mv88e6xxx: Fix logical operator instead of bitwise
In mv88e6xxx_port_enable when attempting to mask out the previous
settings of two bits a logical operator was used instead of a bitwise
operator. Fix this.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-18 15:47:57 +02:00
Andrew Goodbody
ff36afe346 net: mediatek: Use correct variable for return
In mtk_eth_of_to_plat, the last error check has the value in
'priv->phy_addr' but returns ret. Correct to return 'priv->phy_addr'
instead.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-18 15:47:57 +02:00
Andrew Goodbody
ed3b08874f net: ldpaa_eth: Fix buffer overflow in memset
In ldpaa_eth_open a memset is used to initialise a struct to 0 but the
size passed is that of a different struct. Correct to pass the sizeof
the struct that is being initialised.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-18 15:47:57 +02:00
Max Merchel
4800a6a0b3 net: add missing SPDX-License-Identifier for files originating from LiMon
The header of LiMon imported files reference a License file which
does not exist in U-Boot. Some files were forgotten when adding the
SPDX-License-Identifier.
The LiMon files were originally licensed under GPLv2 as can be seen in
commit [2ea91039].

Based on this commit, add the correct SPDX license identifier.
While at it drop the reference to the non-existing License file from all
LiMon files and update the SPDX-License-Identifier to SPDX version 3.

Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com>
2025-08-18 15:47:57 +02:00
Jerome Forissier
6b914d5596 net: lwip: add Kconfig option to show ICMP unreachable errors
Add Kconfig symbol LWIP_ICMP_SHOW_UNREACH which, when enabled, prints a
message to the console upon reception of ICMP unreachable messages. For
example:

 $ make qemu_arm64_lwip_defconfig
 $ qemu-system-aarch64 -M virt -cpu max -nographic -bios u-boot.bin
 [...]
 => dhcp
 DHCP client bound to address 10.0.2.15 (0 ms)
 => tftp 192.168.0.100:69:Image
 Using virtio-net#32 device
 TFTP from server 192.168.0.100; our IP address is 10.0.2.15
 Filename 'Image'.
 Load address: 0x40200000
 Loading: ICMP destination unreachable (host unreachable) from 192.168.0.16
 Timeout!
 => tftp 192.168.0.16:69:Image
 Using virtio-net#32 device
 TFTP from server 192.168.0.16; our IP address is 10.0.2.15
 Filename 'Image'.
 Load address: 0x40200000
 Loading: ICMP destination unreachable (port unreachable) from 192.168.0.16
 Timeout!
 =>

Submitted upstream as https://github.com/lwip-tcpip/lwip/pull/73.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-08-18 14:08:57 +02:00
Jerome Forissier
fbd79b493d lwip: icmp: allow reporting ICMP destination unreachable
Allow reporting ICMP destination unreachable messages via a user-defined
callback.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-08-18 14:08:57 +02:00
Jim Liu
0cabbe3235 net: phy: broadcom: add support for BCM54612E
It's Broadcom PHY simply described as single-port
RGMII 10/100/1000BASE-T PHY.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2025-08-18 14:08:57 +02:00
Jim Liu
59ec495f6c net: designware: Fix get_timer value overflow
get_timer returns a ulong value representing system time in ms.
On a 64-bit system, this ulong value is 64 bits long. However,
the driver stores it in a 32-bit unsigned integer, which overflows
after 49 days up time, causing the driver to get an incorrect time.

Replace the unsigned int variable with a ulong type to properly store
the value returned by get_timer.

Signed-off-by: Stanley Chu <yschu@nuvoton.com>
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2025-08-18 14:08:57 +02:00
Andrew Goodbody
2e9155cb9f phy: marvell: Cannot test unsigned field to be negative
In comphy_cp110_init_serdes_map in comphy_cp110.c there are two fields
in cfg, comphy_lanes_count and comphy_mux_bitcount, which are fetched
from the FDT blob with fdtdec_get_int which returns an int. These two
fields are then tested for being negative. However the fields are
declared as unsigned so those tests must always fail. Change the
declaration of those fields to be int instead of u32 and the code will
work as expected.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Stefan Roese <stefan.roese@mailbox.org>
2025-08-18 14:08:57 +02:00
Andrew Goodbody
a75c8a4b88 phy: marvell: Fix off by 1 limit checks
The limit checks in get_speed_string and get_type_string are off by 1 as
they do not account for the maximum index into an array that can be used
is 1 less than the number of elements in that array. Adjust the limit
checks to allow for this.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Stefan Roese <stefan.roese@mailbox.org>
2025-08-18 14:08:57 +02:00
Andrew Goodbody
4b2d64f388 net: phy: vitesse: Fix incorrect test for timeout
In vsc8514_config there is a while loop for detecting a config failure
using a timeout counter with a post-decrement. In the case of a timeout
this will result in the loop exiting with timeout == -1 so use that as
the test below the loop to detect that the timeout occurred.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-08-18 14:08:57 +02:00
Andrew Goodbody
0ce7fef9e2 net: octeontx: Free allocated memory on error
In octeontx_smi_probe if an error is detected then memory that was
allocated is not freed. Small refactor of the code to use a common
return and free memory. Also return -ENOMEM for an allocation failure.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-18 14:08:57 +02:00
Andrew Goodbody
62b4a482b9 net: octeontx: Remove unneeded test
In nicvf_cq_handler there is a test for !cqe_count which will return if
true so it is guaranteed that cqe_count will true after that point. This
makes the later test for cqe_count redundant so it can be removed.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-18 14:08:57 +02:00
Andrew Goodbody
45eedb7b80 net: octeontx: Remove unneeded code
In nicvf_rcv_pkt_handler there is no need to initialise err as it is
assigned to immediately after. Also the test for !pkt will return if
true meaning that pkt is guaranteed to be true after that code block and
so no need to test for it and the redundant test can be removed.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-18 14:08:57 +02:00
Martin Schwan
0c558bbad9 bootstd: rauc: Change global method to check any partition
The bootmeth rauc should scan all partitions, in particular whole
devices, and not be a global method. There may exist multiple RAUC
systems on different devices and they should all be detected. This also
fixes a bug, where both a global bootflow and one using an actual,
complete device would be detected at the same time, when scanning for
valid bootflows.

Signed-off-by: Martin Schwan <m.schwan@phytec.de>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
2025-08-14 09:18:43 -06:00
Tom Rini
6531aeed37 env: Correct Kconfig type for ENV_MMC_SW_PARTITION
As part of renaming environment related Kconfig options,
ENV_MMC_SW_PARTITION was inadvertently changed from a string to a bool.
Correct this.

Fixes: ffc4914703a2 ("env: Rename ENV_MMC_PARTITION to ENV_MMC_SW_PARTITION")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-14 09:17:02 -06:00
Tom Rini
5e2ade730a Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/27379

- Board: mbv: Prepare MBV for CI
- Board: MPFS Icicle Kit cleanup
- Board: Add Andes Voyager board support
- RISCV: Update SYS_BOOTM_LEN to commonly used value
- starfive: fix return code of `mac write_eeprom`
- arch/riscv/lib: update memmove and memcpy for big-endian
2025-08-14 08:51:42 -06:00
Ben Dooks
35d6caad6d arch/riscv/lib: update memmove and memcpy for big-endian
Change the shift patterns for the unaligned memory move and copy code
to deal with big-endian by definign macros to change the shfit left and
right to go the opposite way.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Heinrich Schuchardt
909ceacf4a starfive: fix return code of mac write_eeprom
When writing the EEPROM fails, the command usage help text is displayed
after the error message. We should only display the error message instead.

If writing the EEPROM fails, return CMD_RET_FAILURE (1) instead of
CMD_RET_USAGE (-1).

Fixes: aea1bd95b61e ("eeprom: starfive: Enable ID EEPROM configuration")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: E Shattow <e@freeshell.de>
2025-08-14 15:33:00 +08:00
Leo Yu-Chi Liang
3856d93ea3 board: MAINTAINERS: Add Voyager board maintainer
Add Voyager board maintainer.

Signed-off-by: Randolph Sheng-Kai Lin <randolph@andestech.com>
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Leo Yu-Chi Liang
2da685378f doc: board: voyager: Add documentation for Voyager
Add documentation for Voyager board.

Signed-off-by: Randolph Sheng-Kai Lin <randolph@andestech.com>
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Leo Yu-Chi Liang
3239ef494c configs: andes: add Voyager board defconfig
Add default configuration file for Voyager board.

Signed-off-by: Randolph Sheng-Kai Lin <randolph@andestech.com>
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Leo Yu-Chi Liang
35995f7ebf board: andestech: Add Voyager board support
Introduce Voyager board specific code, including
- dram info
- shared cache enabling

Signed-off-by: Randolph Sheng-Kai Lin <randolph@andestech.com>
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Leo Yu-Chi Liang
a25e1aacdb riscv: dts: andes: Add Voyager device tree
Introduce the initial device tree support for Andes Voyager board.
We will convert to OF_UPSTREAM once the patch series for kernel is merged.

Signed-off-by: Randolph Sheng-Kai Lin <randolph@andestech.com>
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Leo Yu-Chi Liang
87f98d9225 riscv: board: Add Andes Voyager board Kconfig support
The Voyager is Andes' first RISC-V development board.
It is built around Qilai SoC,
which includes Andes AX45MP quad-core cluster.

Introduce the Kconfig entry for the Voyager board.

Signed-off-by: Randolph Sheng-Kai Lin <randolph@andestech.com>
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Leo Yu-Chi Liang
89e4154431 common: spl: fix compilation warning
Explicitly specify the type by replacing macro with variable
to fix the possible compilation warning.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Jamie Gibbons
f6da31b634 board: microchip: mpfs_icicle: update to use system controller
A new system controller driver has been created to make code modular and
improve and clean code. Update and remove functions to account for these
additional drivers.

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Jamie Gibbons
c93a93e4f2 board: microchip: mpfs_icicle: enable new driver configs
Enable the MPFS mailbox and system controller drivers for use with the
Icicle kit. These functions are crucial for the board setup functions
that run in the Icicle board file - mpfs_icicle.c.

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Jamie Gibbons
b7a0ad16f9 misc: add PolarFire SoC system controller
This driver provides an interface to access the functions of the system
controller on the Microchip PolarFire SoC.
This driver includes functions to use the system controller to read
the device serial number.

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Jamie Gibbons
111e9bf6a5 mailbox: add PolarFire SoC mailbox driver
This driver adds support for the single mailbox channel of the MSS
system controller on the Microchip PolarFire SoC.

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Jamie Gibbons
69539ef2f1 board: microchip: mpfs_icicle: make use of ft_board_setup()
Move ethernet mac address setting to ft_board_setup() to remove the need
for fdt set in custom boot script.

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Jamie Gibbons
c22c40546b configs: microchip_mpfs_icicle: enable CONFIG_OF_BOARD_SETUP
Enable CONFIG_OF_BOARD_SETUP and other dependencies to allow the use of
the ft_board_setup() function to replace fdt set in boot scripts for
Microchip's MPFS Icicle kit.

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Michal Simek
87bd5806e6 xilinx: mbv: Use separate DTB for binman nodes
The commit d92fdb60677b ("binman: Add option for pointing to separate
description") added support for separating binman description to own file
not the be the part of DT for OS.
The main reason is that binman is not passing dt schema validation that's
why want to keep it separated.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 14:32:00 +08:00
Michal Simek
5fe8b53209 xilinx: mbv: Fix dt properties in interrupt controller node
Properties didn't match dt binding that's why should be fixed.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 14:32:00 +08:00
Michal Simek
441ac08142 xilinx: mbv: Add missing mmu-type cpu property
OpenSBI expects mmu-type to be present in DT that's why add it. Without it
OpenSBI disable CPU node which ends up in not working boot.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 14:32:00 +08:00
Michal Simek
5f5bba72c2 xilinx: mbv: Disable OF_HAS_PRIOR_STAGE
There is no reason to use OF_BOARD for MBV because reduced DT is used by
SPL and full DT is passed via u-boot.img or u-boot.itb. There is no reason
to pick up DTB from certain address.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 14:32:00 +08:00
Martin Herren
4bd206a423 riscv: Increase Microchip Icicle's SYS_BOOTM_LEN
Increase Icicle's SYS_BOOTM_LEN to 0x4000000 which is the new default
value.
Done on Conor Dooley's request.

Signed-off-by: Martin Herren <sputnik@on-the-web.ch>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 14:32:00 +08:00
Martin Herren
2fd48ef2d7 riscv: Remove default SYS_BOOTM_LEN from defconfig
Remove CONFIG_SYS_BOOTM_LEN from all riscv defconfigs where the new
default value is used.

Signed-off-by: Martin Herren <sputnik@on-the-web.ch>
Acked-by: Michal Simek <michal.simek@amd.com> # xilinx_mbv
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 14:32:00 +08:00
Martin Herren
b8e140c1f2 riscv: Set SYS_BOOTM_LEN default to 0x4000000
This changes the default value to the most commonly used one among
existing defconfigs.

Signed-off-by: Martin Herren <sputnik@on-the-web.ch>
Acked-by: Michal Simek <michal.simek@amd.com> # xilinx_mbv
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-08-14 14:32:00 +08:00
Martin Herren
4da366de5d riscv: Set SYS_BOOTM_LEN explicitly to 0x800000
For all riscv defconfigs that use the current default value.

This is done in provision of changing the default value to the most
common used value of 0x4000000.

Signed-off-by: Martin Herren <sputnik@on-the-web.ch>
Acked-by: Michal Simek <michal.simek@amd.com> # xilinx_mbv
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 14:32:00 +08:00
Michal Simek
c64fc632a8 riscv: cpu: Use CONFIG_IS_ENABLED(CPU) instead of plain ifdef
ifdef CONFIG_CPU only works in U-Boot proper but macro is not working when
XPL phases are used. In this case CONFIG_SPL_CPU is also defined and can be
disabled which is causing compilation error.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 14:32:00 +08:00
Tom Rini
869217ee29 Merge tag 'qcom-fixes-13Aug2025' of https://source.denx.de/u-boot/custodians/u-boot-snapdragon
CI: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/pipelines/27364

Quite a few Smatch issues reported by Andrew, and the LMB allocation
fix.
2025-08-13 08:57:49 -06:00
Andrew Goodbody
d9fbc1d70b pinctrl: qcom: sdm845: Limit check off by 1
The driver specifies 154 pins so should have a maximum selector of 153
to ensure that the index into the array special_pins_names does not
overflow.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Link: https://lore.kernel.org/r/20250807-pinctrl_qcom-v1-2-42fac6707fd5@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-08-13 15:18:49 +02:00
Andrew Goodbody
be12b6e158 pinctrl: qcom: sa8775: Limit check for array index not correct
In sa8775p_get_pin_name the limit check for the index into
msm_special_pins_data allows for more elements than exist. Add code to
ensure the array index remains in bounds.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Link: https://lore.kernel.org/r/20250807-pinctrl_qcom-v1-1-42fac6707fd5@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-08-13 15:18:49 +02:00
Andrew Goodbody
8a0bb0b176 button: qcom-pmic: Fix dereference of uninitialised pointer
The pointer 'label' is declared and later dereferenced without ever
having a value assigned to it. Add an assignment to this pointer so it
will be valid later when dereferenced.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250723-button-qcom-pmic-v1-1-9c317ac71167@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-08-13 15:17:46 +02:00
Andrew Goodbody
10e65926a3 serial: msm-geni: No need to NULL check priv
The NULL check for priv in qcom_geni_serial_poll_bit serves no useful
prupose as too much other code surrounding it relies on priv being
valid. Remove the NULL check for priv and other related code.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Link: https://lore.kernel.org/r/20250811-serial_msm_geni-v1-2-4499179491bc@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-08-13 15:17:36 +02:00
Andrew Goodbody
f236451cb4 serial: msm-geni: Detect error from get_clk_div_rate
In msm_serial_setbrg if the call to get_clk_div_rate fails then there
will not have been an assignment to clk_div which will lead to the call
to geni_serial_baud using an uninitialised value.
Check for an error from get_clk_div_rate and return an error code if so.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250811-serial_msm_geni-v1-1-4499179491bc@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-08-13 15:17:36 +02:00
Casey Connolly
23e1a11f4e mach-snapdragon: fix erroneous lmb allocations
In commit 6e4675b8e5d8 ("lmb: replace the lmb_alloc() and
lmb_alloc_base() API's") an additional allocation was mistakenly
introduced resulting in ${kernel_comp_size} containing the address of a
second 64mb region rather than the actual value of KERNEL_COMP_SIZE.

Additionally, in commit b40d7b8f72f1 ("Merge patch series "lmb: use
a single API for all allocations"") merge conflict resulted in an
additional 128mb allocation for ${loadaddr} when CONFIG_FASTBOOT
is enabled, where it should actually be set to the same value as
${fastboot_addr_r} to respect size constraints (and since it doesn't
seem to interfer with any bootflows).

Fixup both of these, freeing up 192mb of memory.

Fixes: 6e4675b8e5d8 ("lmb: replace the lmb_alloc() and lmb_alloc_base() API's")
Fixes: b40d7b8f72f1 ("Merge patch series "lmb: use a single API for all allocations"")
Link: https://lore.kernel.org/r/20250811104710.1896382-1-casey.connolly@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-08-13 15:14:04 +02:00
Andrew Goodbody
fda7bee646 phy: qcom: Fix ret is uninitialised
In qcom_snps_eusb2_phy_probe after the call to devm_clk_get if an error
is found then ret is printed but has not been assigned to by the code.
Decode the error from the pointer and assign it to ret.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250806-phy_qcom_snps-v1-1-5cda830026c7@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-08-13 15:13:16 +02:00
Tom Rini
8385793c4c Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
These changes are  mostly smaller fixes, and some additions that were
dependent on recent DT updates: We switch the S3/V3/V3s over to
OF_UPSTREAM, the DTs were already identical anyway. While at it, Paul
sent more fixes for this SoC, I am pulling in two easy fixes that were
ready and low risk. Apart from other assorted fixes, this PR also
enables Ethernet on the new A527/T527 boards, made possible by the DT
update from the DT rebasing repository.

This passed the CI, and was boot tested on boards with Allwinner A10,
A20, A33, V40, A80, A83T, T113s3, F1C100s, H3, A64, H6, H616, A133 and
T527 SoCs.
2025-08-12 09:23:13 -06:00