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riscv: dts: andes: Add Voyager device tree
Introduce the initial device tree support for Andes Voyager board. We will convert to OF_UPSTREAM once the patch series for kernel is merged. Signed-off-by: Randolph Sheng-Kai Lin <randolph@andestech.com> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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Leo Yu-Chi Liang
parent
87f98d9225
commit
a25e1aacdb
@ -1,6 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0+
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dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb
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dtb-$(CONFIG_TARGET_ANDES_VOYAGER) += qilai-voyager.dtb
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dtb-$(CONFIG_TARGET_BANANAPI_F3) += k1-bananapi-f3.dtb
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dtb-$(CONFIG_TARGET_K230_CANMV) += k230-canmv.dtb
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dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb
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227
arch/riscv/dts/qilai-voyager.dts
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227
arch/riscv/dts/qilai-voyager.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/dts-v1/;
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#include "binman.dtsi"
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#include "voyager-u-boot.dtsi"
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/ {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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compatible = "andestech,voyager", "andestech,qilai";
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model = "Voyager";
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aliases {
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uart0 = &serial0;
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spi0 = &spi;
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};
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chosen {
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bootargs = "console=ttyS0,115200n8 earlycon=sbi debug loglevel=7";
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stdout-path = "uart0:115200n8";
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};
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cpus {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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timebase-frequency = <0x3938700>;
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CPU0: cpu@0 {
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device_type = "cpu";
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reg = <0x0>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdc";
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riscv,priv-major = <0x1>;
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riscv,priv-minor = <0xa>;
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mmu-type = "riscv,sv39";
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clock-frequency = <0x3938700>;
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i-cache-size = <0x8000>;
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i-cache-line-size = <0x20>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <0x20>;
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next-level-cache = <&L2>;
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CPU0_intc: interrupt-controller {
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#interrupt-cells = <0x1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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reg = <0x1>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdc";
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riscv,priv-major = <0x1>;
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riscv,priv-minor = <0xa>;
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mmu-type = "riscv,sv39";
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clock-frequency = <0x3938700>;
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i-cache-size = <0x8000>;
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i-cache-line-size = <0x20>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <0x20>;
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next-level-cache = <&L2>;
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CPU1_intc: interrupt-controller {
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#interrupt-cells = <0x1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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reg = <0x2>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdc";
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riscv,priv-major = <0x1>;
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riscv,priv-minor = <0xa>;
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mmu-type = "riscv,sv39";
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clock-frequency = <0x3938700>;
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i-cache-size = <0x8000>;
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i-cache-line-size = <0x20>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <0x20>;
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next-level-cache = <&L2>;
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CPU2_intc: interrupt-controller {
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#interrupt-cells = <0x1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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reg = <0x3>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdc";
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riscv,priv-major = <0x1>;
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riscv,priv-minor = <0xa>;
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mmu-type = "riscv,sv39";
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clock-frequency = <0x3938700>;
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i-cache-size = <0x8000>;
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i-cache-line-size = <0x20>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <0x20>;
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next-level-cache = <&L2>;
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CPU3_intc: interrupt-controller {
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#interrupt-cells = <0x1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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};
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L2: l2-cache@200000 {
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compatible = "cache";
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cache-level = <0x2>;
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cache-size = <0x40000>;
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reg = <0x0 0x00200000 0x0 0x100000>;
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andes,inst-prefetch = <0x3>;
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andes,data-prefetch = <0x3>;
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andes,tag-ram-ctl = <0x0 0x0>;
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andes,data-ram-ctl = <0x0 0x0>;
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};
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memory@400000000 {
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device_type = "memory";
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reg = <0x04 0x00000000 0x0 0x40000000>;
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};
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soc {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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compatible = "simple-bus";
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ranges;
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plic0: interrupt-controller@2000000 {
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compatible = "riscv,plic0";
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#address-cells = <0x2>;
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#interrupt-cells = <0x2>;
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interrupt-controller;
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reg = <0x0 0x02000000 0x0 0x2000000>;
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riscv,ndev = <0x47>;
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interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9
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&CPU1_intc 11 &CPU1_intc 9
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&CPU2_intc 11 &CPU2_intc 9
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&CPU3_intc 11 &CPU3_intc 9>;
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};
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plic1: interrupt-controller@400000 {
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compatible = "andestech,plicsw";
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#address-cells = <0x2>;
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#interrupt-cells = <0x2>;
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interrupt-controller;
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reg = <0x0 0x00400000 0x0 0x400000>;
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riscv,ndev = <0x1>;
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interrupts-extended = <&CPU0_intc 3
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&CPU1_intc 3
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&CPU2_intc 3
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&CPU3_intc 3>;
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};
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plmt0@100000 {
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compatible = "andestech,plmt0";
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reg = <0x0 0x00100000 0x0 0x100000>;
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interrupts-extended = <&CPU0_intc 7
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&CPU1_intc 7
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&CPU2_intc 7
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&CPU3_intc 7>;
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};
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};
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spiclk: virt_100mhz {
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#clock-cells = <0x0>;
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compatible = "fixed-clock";
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clock-frequency = <0x5f5e100>;
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};
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serial0: serial@30300000 {
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compatible = "andestech,uart16550", "ns16550a";
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reg = <0x0 0x30300000 0x0 0x1000>;
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interrupts = <0x9 0x4>;
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clock-frequency = <0x12c0000>;
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reg-shift = <0x2>;
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reg-offset = <0x20>;
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no-loopback-test = <0x1>;
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interrupt-parent = <&plic0>;
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};
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mmc0: mmc@30c00000 {
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compatible = "andestech,atfsdc010";
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max-frequency = <0x5f5e100>;
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clock-freq-min-max = <0x61a80 0x5f5e100>;
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fifo-depth = <0x10>;
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reg = <0x0 0x30c00000 0x0 0x1000>;
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interrupts = <0x12 0x4>;
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cap-sd-highspeed;
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interrupt-parent = <&plic0>;
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dma-coherent;
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};
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spi: spi@30900000 {
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compatible = "andestech,atcspi200";
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reg = <0x0 0x30900000 0x0 0x100000>;
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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num-cs = <0x1>;
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clocks = <&spiclk>;
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interrupts = <0x4 0x4>;
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interrupt-parent = <&plic0>;
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flash@0 {
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compatible = "mx25u1635e", "jedec,spi-nor";
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spi-max-frequency = <0x2faf080>;
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reg = <0x0>;
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spi-cpol;
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spi-cpha;
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};
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};
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};
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52
arch/riscv/dts/voyager-u-boot.dtsi
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52
arch/riscv/dts/voyager-u-boot.dtsi
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@ -0,0 +1,52 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/ {
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cpus {
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bootph-pre-ram;
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CPU0: cpu@0 {
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bootph-pre-ram;
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CPU0_intc: interrupt-controller {
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bootph-pre-ram;
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};
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};
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CPU1: cpu@1 {
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bootph-pre-ram;
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CPU1_intc: interrupt-controller {
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bootph-pre-ram;
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};
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};
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CPU2: cpu@2 {
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bootph-pre-ram;
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CPU2_intc: interrupt-controller {
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bootph-pre-ram;
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};
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};
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CPU3: cpu@3 {
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bootph-pre-ram;
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CPU3_intc: interrupt-controller {
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bootph-pre-ram;
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};
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};
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};
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memory@0 {
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bootph-pre-ram;
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};
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soc {
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bootph-pre-ram;
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plic1: interrupt-controller@400000 {
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bootph-pre-ram;
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};
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plmt0@100000 {
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bootph-pre-ram;
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};
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};
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serial0: serial@30300000 {
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bootph-pre-ram;
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};
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};
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