The current code uses the state of tuning block received by SCC to
determine whether or not to send transmission stop command. This is
not correct. Use the state of tuning block transfer to determine
whether or not to send transmission stop command instead, because
the transmission stop command has to be sent in case the tuning
block transfer failed.
This requires two changes, separate variable to store and check the
state of tuning block received by SCC, and another separate variable
to store and check return value from transmission stop command.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Tested-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
In case a CRC error occurs during DMA transfer, the transfer completion
flag is not set in TMIO_SD_DMA_INFO1 and the transfer would eventually
time out. The timeout could be very long in case the transfer consists
of a large amount of blocks, the base timeout is 10 seconds and every
block adds 100 us more.
In case a CRC error does occur, a completion flag is set in a different
register, TMIO_SD_INFO1. Use this other completion flag to detect DMA
transfer ended and stop waiting for TMIO_SD_DMA_INFO1 completion flag.
This reduces the lengthy timeout in case of an error. The unconditional
check of TMIO_SD_DMA_INFO2 register for DMA related errors must not be
skipped in any case to actually recognize the DMA error and report it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Tested-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
The PL180/MMCI driver is implied to use CONFIG_DM and the ARM
defconfigs such as configs/vexpress_ca9x4_defconfig will get it
as well.
With a simple oneline to default to not being the v2 variant,
the original ARM MMCI variant works fine with the driver as well.
The IP version actually needs to be read out from a register on
the ARM versions, but we will simply assume we are running on the
original hardware if arm,primecell-periphid is not explicitly
specified in the device tree.
Drop the !CONFIG_DM code and depend on DM_MMC.
Tested on the Versatile Express CA9x4 board.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
With MMC_PWRSEQ enabled the following link issue may happen when
building SPL and SPL_PWRSEQ is not enabled.
aarch64-linux-gnu-ld.bfd: drivers/mmc/meson_gx_mmc.o: in function `meson_mmc_probe':
drivers/mmc/meson_gx_mmc.c:295: undefined reference to `pwrseq_set_power'
Fix this by adding a SPL_MMC_PWRSEQ Kconfig option used to enable mmc
pwrseq support in SPL.
Also add depends on DM_GPIO to fix following link issue:
aarch64-linux-gnu-ld.bfd: drivers/mmc/mmc-pwrseq.o: in function `mmc_pwrseq_set_power':
drivers/mmc/mmc-pwrseq.c:26: undefined reference to `gpio_request_by_name'
aarch64-linux-gnu-ld.bfd: drivers/mmc/mmc-pwrseq.c:29: undefined reference to `dm_gpio_set_value'
aarch64-linux-gnu-ld.bfd: drivers/mmc/mmc-pwrseq.c:31: undefined reference to `dm_gpio_set_value'
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Ferass El Hafidi <vitali64pmemail@protonmail.com>
If the CSD register contains a reserved value (4 - 7) in bits 0:2 of the
TRAN_SPEED field, a buffer overrun occurs. Resize the mapping table.
According to the original report
https://lore.kernel.org/u-boot/20180826231332.2491-11-erosca@de.adit-jv.com/
reserved values have been observed resulting in a buffer overrun.
Reported-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Fixes: 272cc70b21 ("Add MMC Framework")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Rename rmobile_is_gen3_mmc0() to rcar_is_gen3_mmc0() because
this particular function is specific to Renesas R-Car Gen3.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Rename ARCH_RMOBILE to ARCH_RENESAS because all the chips are made
by Renesas, while only a subset of them is from the R-Mobile
line.
Use the following command to perform the rename:
"
$ git grep -l 'ARCH_RMOBILE' | xargs -I {} sed -i 's@ARCH_RMOBILE@ARCH_RENESAS@g' {}
"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Rename RMOBILE_CPU_TYPE_* to RENESAS_CPU_TYPE_* because all
the chips are made by Renesas, while only a subset of them is
from the R-Mobile line.
Use the following command to perform the rename:
"
$ git grep -l '\<RMOBILE_CPU_TYPE_[A-Z0-9]\+\>' | \
xargs -I {} sed -i 's@\<RMOBILE\(_CPU_TYPE_[A-Z0-9]\+\)\>@RENESAS\1@g' {}
"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Rename rmobile_get_cpu_rev_*() to renesas_get_cpu_rev_*() because
all the chips are made by Renesas, while only a subset of them is
from the R-Mobile line.
Use the following command to perform the rename:
"
$ git grep -l '\<rmobile_get_cpu_rev_\(integer\|fraction\)\>' | \
xargs -I {} sed -i 's@\<rmobile_get_cpu_rev_\(integer\|fraction\)\>@renesas_get_cpu_rev_\1@g' {}
"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Rename rmobile_get_cpu_type() to renesas_get_cpu_type() because
all the chips are made by Renesas, while only a subset of them
is from the R-Mobile line.
Use the following command to perform the rename:
"
$ git grep -l '\<rmobile_get_cpu_type\>' | \
xargs -I {} sed -i 's@\<rmobile_get_cpu_type\>@renesas_get_cpu_type@g' {}
"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Use the clk_* helper functions and the correct property name for clocks.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Testing has shown that writing to eMMC using HS400 modes on RK3568
result in an ERROR.
Change the tap number for transmit clock to fix this.
Also stop DLL when config_dll() is called to disable DLL.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Make sure that core SDHCI accessors are used and add
device specific card detection initialization, which
is borrowed from vendor Linux driver code.
Tested-by: Jens Maus <mail@jens-maus.de>
Tested-by: Darko Alavanja <darko.alavanja@konsulko.com>
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
The driver currently hard-codes the max freqency for the sdhci
controllers. If the controller is unable to operate at the max
frequency, the mmc card will not be available on the first scan.
Subsequent scans will eventually find a working combination.
Fix this by allowing the driver to check for the max-frequency
property and default to the original value if it doesn't exist.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
The block count limit on MMC based devices should be set according to
CONFIG_SYS_MMC_MAX_BLK_COUNT instead of hardcoding value.
Signed-off-by: Julien Masson <jmasson@baylibre.com>
Now that we have time conversion defines from in time.h there is no need
for each driver to define their own version.
Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com> # tegra
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com> #at91
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> #qcom geni
Reviewed-by: Stefan Bosch <stefan_b@posteo.net> #nanopi2
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Currently the renesas_sdhi_reset_tuning() unconditionally leaves SDHI
clock enabled after the tuning reset. This is not always necessary.
After the driver performed tuning reset at the end of probe function,
or in the unlikely case that tuning failed during regular operation,
the SDHI clock can be disabled after the tuning reset. The following
set_ios call would reconfigure the clock as needed.
In case of regular set_ios call which requires a tuning reset, keep
the clock enabled or disabled according to the mmc->clk_disable state.
With this in place, the controllers which have not been accessed via
block subsystem after boot are left in quiescent state. However, if an
MMC device is used e.g. for environment storage, that controller would
be accessed during the environment load and left active, including its
clock which would still be generated. This is due to the design of the
MMC subsystem, which does not deinit a controller after it was started
once, the controller is only deinited in case of mmc rescan, or before
OS boot.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Tested-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Thuan Nguyen Hong <thuan.nguyen-hong@banvien.com.vn>
commit 95168d77d3 ("sunxi: add Allwinner R528/T113 SoC support") added
the new entry out of order.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
The MMC controller driver is (and ought to be) the only user of these
register definitions. Put them in a header next to the driver to remove
the dependency on a specific ARM platform's headers.
Due to the sunxi_mmc_init() prototype, the file was not renamed. None of
the register definitions were changed.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Default-tap and default-trim values are used for eMMC setup
mostly on T114+ devices. As for now, those values are hardcoded
for T210 and ignored for all other Tegra generations. Fix this
by passing tap and trim values from dts.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
In line with changes elsewhere, drop inclusion of the common header.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
As noted in commit 3a6383207b ("mmc: sdhci: add the quirk for broken
r1b response"), some MMC controllers don't always set the transfer
complete bit with R1b responses.
According to the SD Host Controller Simplified Specification v4.20,
> In the case of a command pairing with response-with-busy[, Transfer
> Complete] is set when busy is de-asserted. Refer to DAT Line Active
> and Command Inhibit (DAT) in the Present State register.
By polling the DAT Line Active bit in the present state register, we can
detect when we are no longer busy, without waiting for a long timeout.
This results in much faster reads/writes on buggy controllers.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Tested-by: Henrik Grimler <henrik@grimler.se>
dm_pci_map_bar() return a value of (void *) already, hence no need
to cast it again before assigning to host->ioaddr.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
mmc_bind() in mmc-uclass.c calls blk_create_devicef() which is
defined in blk-uclass.c, so SPL_BLK is required by SPL_DM_MMC.
Implicitly select SPL_BLK for SPL_DM_MMC.
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
The R-Car Gen3 SD_CLK_CTRL register does not use BIT(16) to implement
divider 1/1024, instead BIT(16) is reserved bit and divider 1/1024 is
not supported. The divider 1/1024 is specific to Socionext variant of
the IP, as is indicated by Linux commit:
0196c8db8363 ("mmc: tmio: move tmio_mmc_set_clock() to platform hook")
"
Socionext (and Panasonic) uses bit 10 (CLKSEL) for 1/1. Also, newer
versions of UniPhier SoC variants use bit 16 for 1/1024.
"
Do not set the TMIO_SD_CAP_DIV1024 on Renesas R-Car platforms even if
the IP VERSION register does exist, and indicates IP version is newer
or equal to version 1.0 . The IP version 1.0 or newer does not imply
presence of the 1/1024 divider.
Since the TMIO driver is used exactly by two supported platforms, that
is Renesas R-Car and Socionext UniPhier, it is OK to check whether the
TMIO_SD_CAP_RCAR capability is not set to identify the UniPhier platform
and add the capability only on that platform.
Fixes: 58c35b17aa ("mmc: matsushita-common: Always check controller version")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Thuan Nguyen Hong <thuan.nguyen-hong@banvien.com.vn>
Unconditionally check for errors even after successful reception
of IRQ flag, since the hardware may set both an IRQ completion
flag and an error flag at the same time.
This mode of failure happens in case of an error during transfer,
in which case the hardware may set the expected IRQ completion
flag as well as error flags. The later is currently not checked
by the driver and such an error is not detected. Improve the
error detection.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Thuan Nguyen Hong <thuan.nguyen-hong@banvien.com.vn>
This driver is long superseded by renesas-sdhi.c and unused.
Drop the driver.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Paul Barker <paul.barker.ct@bp.renesas.com>
We should ensure that reset_free() is called in the error path.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Fixes: 93c811b733 ("mmc: renesas-sdhi: Initialize module on RZ/G2L")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This adds the remaining code bits to teach U-Boot about Allwinner's
newest SoC generation. This was introduced with the RISC-V based
Allwinner D1 SoC, which actually shares a die with the ARM cores versions
called R528 (BGA, without DRAM) and T113s (QFP, with embedded DRAM).
This adds the new Kconfig stanza, using the two newly introduced symbols
for the new SoC generation and pincontroller. It also adds the new symbols
to the relavent code places, to set all the hardcoded bits directly.
We need one DT override:
The ARM core version of the DT specifies the CPUX watchdog as
"reserved", which means it won't be recognised by U-Boot. Override this
in our generic sunxi-u-boot.dtsi, to let U-Boot pick up this watchdog,
so that the generic reset driver will work.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Allwinner seems to typically stick to a common MMIO memory map for
several SoCs, but from time to time does some breaking changes, which
also introduce new generations of some peripherals. The last time this
happened with the H6, which apart from re-organising the base addresses
also changed the clock controller significantly. We added a
CONFIG_SUN50I_GEN_H6 symbol back then to mark SoCs sharing those traits.
Now the Allwinner D1 changes the memory map again, and also extends the
pincontroller, among other peripherals.
To mark this generation of SoCs, add a CONFIG_SUNXI_GEN_NCAT2 symbol,
this name is reportedly used in the Allwinner BSP code, and prevents us
from inventing our own name.
Add this new symbol to some guards that were already checking for the H6
generation, since many features are shared between the two (like the
renovated clock controller).
This paves the way to introduce a first user of this generation.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Samuel Holland <samuel@sholland.org>
U-Boot's generic GPIO_EXTRA_HEADER is a convenience symbol to allow code
to more easily include platform specific GPIO headers. This should not
be needed in a DM world anymore, since the generic GPIO framework
handles that nicely.
For Allwinner boards we still need to deal with non-DM GPIO in the SPL,
but this should become the exception, not the rule.
Make this more obvious by removing the definition of GPIO_EXTRA_HEADER,
and just force every legacy user of platform specific GPIO to include
the new sunxi_gpio.h header explicitly. Everyone doing so should feel
ashamed and should find a way to avoid it from now on.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Samuel Holland <samuel@sholland.org>
On the Renesas RZ/G2L SoC family, we must ensure that the required clock
signals are enabled and the reset signal is de-asserted before we try to
communicate with the SDHI module.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Move the assignment of priv->quirks earlier in the function. This allows
us to drop the quirks local variable and makes it easier to maintain
clean error handling when we add RZ/G2L support in the next patch.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This old patch was marked as deferred. Bring it back to life, to continue
towards the removal of common.h
Move this out of the common header and include it only where needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
With the commit 4fcba5d556 ("regulator: implement basic reference
counter"), keeping regulator enablement in balance become more important.
Disable vqmmc-supply before signal voltage is changed to keep regulator
enable counter in balance.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
With the commit 4fcba5d556 ("regulator: implement basic reference
counter") the return value of regulator_set_enable may be EALREADY or
EBUSY for fixed/gpio regulators.
Change to use the more relaxed regulator_set_enable_if_allowed to
continue if regulator already was enabled or disabled.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # P895 Tegra 3;
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # rockpro64-rk3399
This name is a little confusing since it suggests that it sets up the
sibling block device. In fact it sets up a bootdev for it. Rename the
function to make this clearer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
If the device attached to the MMC bus is not removable, set force card-detect
bit to bypass card detection procedure, so card detection pin can be used for
other purposes.
It's also a workaround for SAMA5D2 who doesn't drive CMD if using GPIO for card
detection.
Signed-off-by: Zixun LI <zli@ogga.fr>
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
Dll reset is needed only for ZynqMP platforms, add condition in tuning
to call arasan_zynqmp_dll_reset() just for ZynqMP platforms.
On other platforms like Versal NET, If this condition is not added, we
see PLM error messages when dll reset smc is called.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d673ff3bdc5c236a7f0403c920e719684abd6059.1688991117.git.michal.simek@amd.com
Set MMC clock when reverting to safe bus mode and speed
in case current MMC mode fails. Otherwise, trying out
the other modes may fail as well.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
[hp: fallback to legacy_speed]
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
When tuning command (CMD21) fails with command error, call
mmc_send_stop_transmission() to send stop command (CMD12).
Reviewed-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Add dev_dbg() message in case tuning abort fails
Move tuning opcode check from mmc_abort_tuning()]
Reviewed-by: Peng Fan <peng.fan@nxp.com>
If a tuning command times out, the card could still be processing it,
which will cause problems for recovery. The eMMC specification section
6.6 Data transfer mode (cont’d) claims that CMD12 can be used to stop
CMD21:
"
The relationship between the various data transfer modes is summarized (see Figure 27):
- All data read commands can be aborted any time by the stop command (CMD12).
The data transfer will terminate and the Device will return to the Transfer State.
The read commands are: ... send tuning block (CMD21) ....
"
Add a function that does that.
Based on Linux commit [1] and [2].
[1] e711f0309109 ("mmc: mmc: Introduce mmc_abort_tuning()")
[2] 21adc2e45f4e ("mmc: Improve function name when aborting a tuning
cmd")
Reviewed-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Update commit message, quote relevant part of the specification.
Rename to mmc_send_stop_transmission().
Remove tuning opcode check, this is controller driver specific.
Deduplicate part of mmc_read_blocks() using this function.]
Reviewed-by: Peng Fan <peng.fan@nxp.com>
For MMC/eMMC, the MMC_CMD_STOP_TRANSMISSION response is R1 for read
transfers and R1b for write transfers per JEDEC Standard No. 84-B51
Page 126 . The response is R1b unconditionally per Physical Layer
Simplified Specification Version 9.00.
Correct the response type and add a comment about it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
It seems better to call this a 'bootdev' since this is name used in the
documentation. The older 'Bootdevice' name is no-longer used and may cause
confusion with the 'bootdevice' environment variable.
Update throughout to use bootdev.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Buffers created through DEFINE_(CACHE_)ALIGN_BUFFER are actually
pointers to the real underlying buffer. Using sizeof(...) is
not appropriate in this case.
Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Loading part of TF-A into SRAM from eMMC using DMA fails on RK3399
similar to other Rockchip SoCs. Checksum validation fails with:
## Checking hash(es) for Image atf-2 ... sha256 error!
Bad hash value for 'hash' hash node in 'atf-2' image node
spl_load_simple_fit: can't load image loadables index 1 (ret = -1)
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Add a device tree property, u-boot,spl-fifo-mode, to control when the
rockchip_sdhci driver should disable the use of DMA and fallback on PIO
mode. Same device tree property is used by the rockchip_dw_mmc driver.
In commit 2cc6cde647 ("mmc: rockchip_sdhci: Limit number of blocks
read in a single command") the DMA mode was disabled using a CONFIG
option on RK3588. Revert that and instead disable DMA using the device
tree property for all RK3588 boards, also apply similar workaround for
all RK3399 boards.
Fixes: 2cc6cde647 ("mmc: rockchip_sdhci: Limit number of blocks read in a single command")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Quentin Schulz <foss+uboot@0leil.net> # RK3399 Puma, RK3588 Tiger
The workaround to limit number of blocks to read in a single command
should only be applied to RK3568 and RK3588. Change to be more strict
when to apply the workaround.
Fixes: 2cc6cde647 ("mmc: rockchip_sdhci: Limit number of blocks read in a single command")
Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Quentin Schulz <foss+uboot@0leil.net> # RK3399 Puma, RK3588 Tiger
This reverts commit a034ec06ff.
Commit 4a3ea75de4 ("Revert "mmc: sdhci: set to INT_DATA_END when
there are data"") reverted the alternative fix that was added for
Exynos 4 devices, causing an error when trying to boot from an sdcard:
<...>
Loading Environment from MMC... sdhci_send_command: Timeout for status update!
mmc fail to send stop cmd
<...>
Re-add the quirk to allow booting from sdcards again.
Signed-off-by: Henrik Grimler <henrik@grimler.se>
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_index_ptr instead of the devfdt_get_addr_index function
in the various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_ptr instead of the dev_read_addr function in the
various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
It adds compatible "hisilicon,hi3798mv200-dw-mshc" for HC2910 SoC
Hi3798MV200 to probe this mmc driver.
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
Using DMA to load TF-A into SRAM fails when booting from eMMC on RK3588.
## Checking hash(es) for Image atf-3 ... sha256 error!
Bad hash value for 'hash' hash node in 'atf-3' image node
spl_load_simple_fit: can't load image loadables index 2 (ret = -1)
mmc_load_image_raw_sector: mmc block read error
Fix this by using PIO mode in SPL and limit the number of blocks used in
a single read command to avoid triggering Data End Bit Error interrupt.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Rockchip emmc devices have a similar issue to Rockchip dwmmc devices,
where performing DMA to SRAM later causes issues with suspend/resume.
Allow us to toggle SDMA in SPL for sdhci similar to ADMA support, so we
can ensure DMA is not used when loading the SRAM code.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
[jonas@kwiboo.se: add Kconfig default value and fix ADMA typo]
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Add support for RK3588 to the rockchip sdhci driver.
Use driver data to handle differences between RK3568 and RK3588:
- Set "Receive original clock source is auto gating" for RK3588.
- Set "Receive clock source is no-inverted" only on RK3568 and "Transmit
clock source is invertion of original clock input" for RK3588.
- Use different txclk_tapnum for HS400 modes on RK3588.
- Configure the CMDOUT reg for HS400 modes for RK3588.
This is based on the mainline linux and vendor kernel driver and have
successfully been tested with rock5b-rk3588_defconfig and
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_SPEED_MODE_SET=y
using the following command to switch mode and then read 512 MiB of data
from eMMC into memory,
=> mmc dev 0 0 <mode> && mmc info && mmc read 10000000 2000 10000
for each of the modes below.
0 = MMC legacy
1 = MMC High Speed (26MHz)
3 = MMC High Speed (52MHz)
4 = MMC DDR52 (52MHz)
10 = HS200 (200MHz)
11 = HS400 (200MHz)
12 = HS400ES (200MHz)
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Adjust tap number for transmit clock, tap number and delay number for
strobe input to fix HS400 modes on RK3568.
New values have been picked from vendor kernel and u-boot and have
successfully been tested with rock-3a-rk3568_defconfig and
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_SPEED_MODE_SET=y
using the following command to switch mode and then read 512 MiB of data
from eMMC into memory,
=> mmc dev 0 0 <mode> && mmc info && mmc read 10000000 2000 10000
for each of the modes below.
0 = MMC legacy
1 = MMC High Speed (26MHz)
3 = MMC High Speed (52MHz)
4 = MMC DDR52 (52MHz)
10 = HS200 (200MHz)
11 = HS400 (200MHz)
12 = HS400ES (200MHz)
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This rearrange and remove duplicate defines to make the code cleaner.
There is no need to read vendor area1 and use an offset each time, it is
easier and clearer to just use the reg offset defined in TRM, same as
the other vendor regs.
This also removes use of the misspelled const for the RK3588 CMDOUT reg,
it will be re-added when support for RK3588 is introduced.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Remove empty implementations of get_phy and set_enhanced_strobe ops.
Change driver set_enhanced_strobe to return 0 in order to allow missing
implementation of the ops.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Refactor set_ios_post ops to correctly set UHS Speed Select field values
according to TRM. Also set or unset Enhanced Strobe Enable bit and
eMMC Card present bit in set_ios_post, the Enhanced Strobe Enable bit
was never unset after switching to HS400ES mode.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Check return value from mmc_send_cmd and clear HOST_CONTROL2 when there
is an error. Also skip enable of interrupt signaling and remove a delay,
a delay is already happening in sdhci_send_command.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Change to configure clock and DLL in set_clock and config_dll ops
instead of in the set_ios_post ops.
With this change the output clock is turned off while configuring DLL
parameters, according to the design recommendations.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add support for the set_clock and config_dll sdhci_ops. Use of these ops
will allow configuration of DLL while the output clock is disabled.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Remove the unneeded emmc_phy_init now that the no-inverter flag is
handled correctly after commit 2321a991bb ("rockchip: sdhci: rk3568:
bypass DLL when clk <= 52 MHz").
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The device private data is misused in rockchip_sdhci_of_to_plat and
rockchip_sdhci_execute_tuning.
In these functions dev_get_priv is assigned to struct sdhci_host:
struct sdhci_host *host = dev_get_priv(dev);
Instead, the sdhci host should refer to host in struct rockchip_sdhc:
struct rockchip_sdhc *priv = dev_get_priv(dev);
struct sdhci_host *host = &priv->host;
Because host is the first member in struct rockchip_sdhc this is not a
real problem, lets fix it anyway and also use priv name consistently.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Set correct UHS Mode Select field value for UHS SDR25 (50MHz) mode.
Fixes: d1c0a2200a ("mmc: sdhci: Add support for HOST_CONTROL2 and setting UHS timings")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Set High Speed Enable bit for MMC High Speed (52MHz) mode.
Fixes: f12341a952 ("mmc: sdhci: Fix HISPD bit handling")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
mmc->tran_speed is max clock, but currently rk3568_sdhci_set_ios_post
uses it if its != 0, regardless of mmc->clock value, and it breaks
eMMC controller.
Without this patch 'mmc dev 0; mmc dev 1; mmc dev 0' is enough for
breaking eMMC, since first initialization sets mmc->mmc_tran speed
to non-zero value (26MHz in my case), and on subsequent re-init when
mmc layer asks for 400KHz it sets 26MHz instead.
Fix it by using MAX(mmc->tran_speed, mmc->clock)
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Use IS_ENABLED() instead of CONFIG_IS_ENABLED() to check for CONFIG_
option which is identical across all of U-Boot and xPL builds.
Fixes: 2769ddc99f ("mmc: tmio: Replace ifdeffery with IS_ENABLED/CONFIG_IS_ENABLED macros")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
All build targets using this driver already use DM_MMC. So let's depend
this driver on this Kconfig symbol and remove the non-DM driver part.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
CONFIG_MMC_SDHCI_IO_ACCESSORS is not supported and/or used by this
driver so let's remove these unused parts completely.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
This driver already depends on CONFIG_ARCH_MVEBU, so there is no need
to have some checks for this Kconfig symbol in the driver itself. Let's
remove these superfluous checks.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
The default erase command applies on erase group unit, and
simply round down to erase group size. When the start block
is not aligned to erase group size (e.g. erasing partition)
it causes unwanted erasing of the previous blocks, part of
the same erase group (e.g. owned by other logical partition,
or by the partition table itself).
To prevent this issue, a simple solution is to use TRIM as
argument of the Erase command, which is usually supported
with eMMC > 4.0, and allow to apply erase operation to write
blocks instead of erase group
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
When secure/insecure TRIM operations are supported.
When used as erase command argument it applies the
erase operation to write blocks instead of erase
groups.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
The DM_REGULATOR symbol has SPL counterpart in:
drivers/power/regulator/Kconfig:config SPL_DM_REGULATOR
Use CONFIG_IS_ENABLED() macro to match on the correct
variant depending on the build stage.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Support R-Car Gen4 family. The default quirk is similar to previous
generation.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Use RCAR_64 Kconfig
Instead of #if and #ifdef, use IS_ENABLED and CONFIG_IS_ENABLED macros.
This improves build test coverage. The CONFIG_SPL_BUILD must remain an
ifdef, as CONFIG_SPL_STACK may not always be defined, e.g. in U-Boot
proper build. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
The 64bit limitation check is compiled and optimized out on 32bit
platforms, but generates a type width warning:
drivers/mmc/tmio-common.c: In function ‘tmio_sd_addr_is_dmaable’:
drivers/mmc/tmio-common.c:376:26: warning: right shift count >= width of type [-Wshift-count-overflow]
376 | if (addr >> 32)
| ^~
Fix the warning by checking the addr type width to see whether the
shift even makes sense in the first place. The width check is also
optimized out at compile time.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
- Fixes for booting newer revs of the SoC in the Raspberry Pi 4
- Propagate some firmware DT properties to the loaded DT
- Update the Zero2W upstream DT name
Newer firmware can manage the SDCDIV clock divisor register, allowing
the divisor to scale with the core as necessary.
Leverage this ability if the firmware supports it.
Adapted from the following raspberrypi Linux kernel commit:
bcm2835-sdhost: Firmware manages the clock divisor
08532d242d
Signed-off-by: Vincent Fazio <vfazio@xes-inc.com>
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
For Rockchip platform, DLL bypass bit and start bit need to be set if
DLL is not locked.
With this change applied eMMC in my NanoPi R5S can run at 52 MHz.
Based on linux commit b75a52b0dda3 ("mmc: sdhci-of-dwcmshc: Update DLL
and pre-change delay for rockchip platform")
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The get_mmc_clk ops is expected to set a clock rate and return the
configured rate as an unsigned value. However, if clk_set_rate fails,
e.g. using a fixed rate clock, a negative error value is returned.
The mmc core will treat this as a valid unsigned rate and tries to
configure a divider based on this bogus clock rate.
Use 0 as the return value when setting clock rate fails, the mmc core
will configure to use bypass mode instead of using a bogus divider.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
In case one of the calls in probe fail, trigger a fail path and
undo all the steps done in probe until the point of failure.
The current implementation failed to stop controller clock and
free claimed clock, so fix that. Furthermore, print return code
in error prints for easier debugging.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The prior stage bootloader might have left the SDnCKCR register in completely
arbitrary state before passing control to U-Boot, which includes the register
being populated with incorrect values. Currently the SDHI driver will attempt
to use clock framework to configure SDn clock, which may fail in case SDnCKCR
contains invalid values for the SDnH clock, because the clock framework would
not be able to determine SDnH clock rate and would get -EINVAL instead, which
in turn would not allow the clock framework to determine the correct SDn clock
divider ratio.
This failure occurs specifically in case SDnCKCR reads back 0x209 .
Correct the problem by first setting default SDnH clock rate to 800 MHz, thus
assuring the SDnCKCR SDnH bits are correct, and only afterward set up the SDn
clock rate to default 200 MHz.
Note that the SDHI driver may reconfigure SDnH clock later based on IOS
settings obtained from the attached card, the 800 MHz set up here is only
the default value.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
There are missing Kconfig dependencies in the code which is using
firmware interface.
The commit 71efd45a5f ("arm64: zynqmp: Change firmware dependency")
add option to also disable ZYNQMP_FIRMWARE. But not all Kconfig
dependencies were properly described and also sdhci and gem drivers
didn't protect the code properly.
So, add the missing ZYNQMP_FIRMWARE dependencies.
Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230201095553.11219-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
As the file spear_sdhci.c file is already removed, delete the associated
configuration CONFIG_MMC_SDHCI_SPEAR.
Fixes: c942fc925e ("mmc: spear: remove the entire spear_sdhci.c file")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
The RK3288 TRM states that, for 8-bit DDR modes:
The CLKDIV register should always be programmed with a value
higher than zero (0); that is, a clock divider should always be
used for 8-bit DDR mode.
In Linux, the driver applies this logic for all SoCs using the driver
and does not distinguish RK3288, so presumably this requirement is the
same for all other Rockchip SoCs using this IP.
Add the necessary code to double the clock frequency when 8-bit DDR is
selected. The dw_mmc core already handles setting CLKDIV correctly
given the input clock and desired bus clock.
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_SUPPORT_EMMC_RPMB defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_RENESAS_SDHI defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_MMC_QUIRKS defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
The old SD handling code was huge and could not handle all the details
which showed up on R-Car Gen3 SoCs meanwhile. It is time to switch to
another design. Have SDnH a separate clock, use the existing divider
clocks and move the errata handling from the clock driver to the SDHI
driver where it belongs.
Based on Linux series by Wolfram Sang, commit bb6d3fa98a41 ("clk:
renesas: rcar-gen3: Switch to new SD clock handling") and commit
e5f7e81ee430a ("mmc: renesas_sdhi: Parse DT for SDnH")
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek: - Add rcar_clk_* prefix to all functions
- Fix missing ~ in GENMASK(a, b), use clrsetbits_le32 instead
- Use DIV_ROUND_CLOSEST, else if parent clock = 199999992 and
rate = 200000000, the divider would be 0 and table lookup
would fail.
- Turn rcar_clk_get_table_val into signed integer, so it can
return 0 as a valid value and negative values as errors.
- Make the code operate on correct clock and add comment
which explains the reasoning behind it.
- Rebase on changes to
clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function
V3M handles SDnH differently than other Gen3 SoCs, so let's add a
separate entry for that. This will allow better SDnH handling in the
future.
Based on Linux commit 627151b4966f ("mmc: renesas_sdhi: Flag
non-standard SDnH handling for V3M") by Wolfram Sang
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
It is unnecessary, so clean it up.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # update commit message, mention ES3.0
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Support R8A77961 M3-W+ SoC.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Still uses 0x3 for now, adjust the offset value to TMPPORT3 accordingly
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Adjust HS400 calibration tables based on Linux settings
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Further filter out HS400 support on certain SoCs.
Since M3-W r1.2 does not support HS400, drop the calibration table and
rename the one for M3-W r1.3 to r8a7796_rev13_calib_table
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Early ES revisions of M3-W SoCs requires 4-tap HS400. Reflect the status
from datasheet.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add support for HS400 in mode2timing array.
Add a quirk for Versal NET platform to indicate that HS400 is supported
through bit63 of capability register.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
HS400 is indicated in bit63 of capability register in few IP's.
Add a quirk to check this and add HS400 to host capabilities.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Check if the low level driver supports config_dll callback function and
call it if it does. Call with dll disable before calling set_clock and
with dll enable after it.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Add support for eMMC 5.1 for Versal NET platform
- Add new compatible string(xlnx,versal-net-5.1-emmc).
- Add CONFIG_ARCH_VERSAL_NET condition wherever required.
- Add DLL and Delay Chain mode support
- Add input and output tap delays for eMMC.
- Add Strobe select tap for HS400 mode.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Add more capable "bkops" command which allows enabling and disabling both
manual and automatic bkops. The existing 'mmc bkops-enable' subcommand is
poorly named to cover all the possibilities, hence the new-ish subcommand.
Note that both commands are wrappers around the same common code.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
makefile:
- Add multi_dtb_fit dependency
clk:
- Handle error cases
microblaze:
- Disable falcon mode and cleanup code around
xilinx:
- Enable regular expression matching in board_fit_config_name_match()
- Fix FRU handling for 0xC1 format
- Fix Xilinx legacy format eeprom parsing
zynqmp:
- Some DT updates/cleanups
- Fix IDcode for xck24
- Remove empty mini config files
- Add support for k24
versal:
- Remove empty mini config files
versal_net:
- Setup timer when runs in EL3
- Build u-boot.elf for mini configurations
zynq-gem:
- Add support for new compatible strings
- Remove support for Avnet Ultrazedev SOM
- Handle SGMII with PCS phy
spi:
- Add support for gigadevice parts
misc:
- Remove CONFIG_TARGET_VENUS ifdef
- Add missing headers to remove sparse warnings
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Merge tag 'xilinx-for-v2023.04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx chnages for v2023.04-rc1
makefile:
- Add multi_dtb_fit dependency
clk:
- Handle error cases
microblaze:
- Disable falcon mode and cleanup code around
xilinx:
- Enable regular expression matching in board_fit_config_name_match()
- Fix FRU handling for 0xC1 format
- Fix Xilinx legacy format eeprom parsing
zynqmp:
- Some DT updates/cleanups
- Fix IDcode for xck24
- Remove empty mini config files
- Add support for k24
versal:
- Remove empty mini config files
versal_net:
- Setup timer when runs in EL3
- Build u-boot.elf for mini configurations
zynq-gem:
- Add support for new compatible strings
- Remove support for Avnet Ultrazedev SOM
- Handle SGMII with PCS phy
spi:
- Add support for gigadevice parts
misc:
- Remove CONFIG_TARGET_VENUS ifdef
- Add missing headers to remove sparse warnings
tuning_loop_counter is of char type, which is not capable of handling
the entire data range of this variable. This is pointed by below sparse
warning. Change datatype to int to fix this.
warning: comparison is always false due to limited range of data type.
Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230120053617.32463-5-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
This contains some fixes, and the first bunch of some clean up patches
to get rid of legacy GPIO and PMIC code.
Highlight is the DM AXP PMIC driver, which is required to convert some
drivers over to use DM regulators, and also is required to get rid
of some less optimal PMIC setup code in Trusted Firmware. This isn't
enabled by any defconfig yet, but can be enabled manually and works. For
the full glory some patches are still missing, and this requires more
testing, which would be simpler if the core code is upstream.
We need extensions to be set up before we start trying to boot any of the
bootdevs. Add a new priority before all the others for tht sort of thing.
Also add a 'none' option, so that the first one is not 0.
While we are here, comment enum bootdev_prio_t fully and expand the test
for the 'bootdev hunt' command.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a hunter for MMC. This doesn't do anything at present, since MMC is
currently set up when U-Boot starts. If MMC moves to lazy init then we can
add a hunter function.
Signed-off-by: Simon Glass <sjg@chromium.org>
The code in these functions turns out to often be the same. Add a default
get_bootflow() function and allow the drivers to select it by setting
the method to NULL.
This saves a little code space.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present MMC uses the bootdev_setup_for_dev() function to set up the
bootdev. This is because MMC only has one block-device child, so does not
need to worry about naming of the bootdev.
However this inconsistency with other bootdevs that use block devices is a
bit annoying. The only real reason for it is to have a name like
'mmc0.bootdev' instead of 'mmc0.blk.bootdev'.
Update bootdev_setup_sibling_blk() to drop '.blk' from the name where it
appears, thus removing the only reason to use the bootdev_setup_for_dev().
Switch MMC over to the subling function.
Signed-off-by: Simon Glass <sjg@chromium.org>
When running multiple tests the mmc emulator calls malloc() to obtain the
memory for its disk image. Since the memory is not cleared, it is possible
that it happens to contain a partition table.
The dm_test_part() test (for one) relies on mmc0 being empty on startup.
Zero the memory to ensure that it is.
Signed-off-by: Simon Glass <sjg@chromium.org>
As the SPL code for sunxi boards does not use the driver model, we have
two mmc_ops structures, one for DM, one for non-DM. The actual hardware
access code is shared, with the respective callback functions using that
common code.
To make this more obvious and easier to read, reorder the functions to
group them: we first have the common code, then the non-DM bits, and
the proper DM implementation at the end.
Also document this structure in the comment at the beginning of the file.
No functional change intended.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
The sunxi MMC code does not use the DM in the SPL, as we don't have a
device tree available that early, also no space for it.
This also means we cannot access the card-detect GPIO information from
there, so we have Kconfig symbols called CONFIG_MMCx_CD_PIN, which each
board has to define. This is a burden, also requires extra GPIO code in
the SPL.
As the SPL is the natural successor of the BootROM (from which we are
loaded), we can actually ignore the CD pin completely, as this is what
the BootROM does as well: CD GPIOs are board specific, but the BootROM
is not, so accesses the MMC devices anyway.
Also, as we must have been loaded from an MMC device when reaching this
code, there must have been a card in the slot.
Remove the card detect code from the non-DM implementation of the sunxi
MMC driver, to get rid of this unneeded code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
This converts the following to Kconfig:
CONFIG_FLASH_SPANSION_S29WS_N
CONFIG_FLASH_VERIFY
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
CONFIG_FSL_ISBC_KEY_EXT
CONFIG_FSL_TRUST_ARCH_v1
CONFIG_FSL_SDHC_V2_3
CONFIG_MAX_DSP_CPUS
CONFIG_MIU_2BIT_INTERLEAVED
CONFIG_SERIAL_BOOT
CONFIG_SPI_BOOTING
CONFIG_X86EMU_RAW_IO
Signed-off-by: Tom Rini <trini@konsulko.com>
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This converts the following to Kconfig:
CONFIG_SYS_MMC_MAX_BLK_COUNT
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
When MMC_WRITE is disabled this driver produced a build error. Fix this.
Also update a comment while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Use the correct SPL_TPL_ variable so that these features can be enabled in
TPL and VPL as needed.
Disable it by default in TPL to avoid any code-size increase. No boards
are actually using it since the Makefile rules don't allow including
drivers/block/ with TPL_DM enabled. It can be manually enabled as needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Correct pointer dereferencing check to be more consistent.
Eliminate the below smatch warning:
drivers/mmc/mmc.c:3118 mmc_init_device()
warn: variable dereferenced before check 'm' (see line 3116)
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Unconditionally clearing DTO when RXDR is set leads to spurious timeouts
in FIFO mode transfers if events occur in the following order:
mask = dwmci_readl(host, DWMCI_RINTSTS);
// Hardware asserts DWMCI_INTMSK_DTO here
dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_DTO);
if (mask & DWMCI_INTMSK_DTO) {
// Unreachable as DTO is cleared without being handled!
return 0;
}
Only clear interrupts that we have seen and are handling so that DTO is
not missed.
Signed-off-by: John Keeping <john@metanate.com>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (Rock PI 4B)
Tested-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
The SDMMC IOs can be in an IO domain, that has to be enabled.
This is done by enabling vqmmc in the driver.
This has no impact on configurations not using an IO domain, the check
can then be executed on all platforms managing regulator, and the vqmmc
regulator enabled on all platforms having it in their DT.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
The UHS modes for SD, HS200 and HS400 modes for eMMC are not supported
by the stm32_sdmmc2 driver.
Make it clear by removing the corresponding caps after parsing the DT.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
To support dual data rate with STM32 sdmmc2 driver, the dedicated bit
(DDR - BIT(18)) needs to be set in the CLKRC register. Clock bypass
(no divider) is not allowed in this case. This is required for the
eMMC DDR modes.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Add Socionext F_SDH30_E51 IP support. The features of this IP includes
CMD/DAT line delay and force card insertion mode for non-removable cards.
And the IP needs to add some quirks.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
This patch defines a quirk to disable the block count
for single block transactions.
This is similar to Linux kernel commit d3fc5d71ac4d
("mmc: sdhci: add a quirk for single block transactions").
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Get rid of discrepancy beween comment /* 250 ms */ and code
which shifts by 4 thus dividing by 16.
So change code to shift by 2 and make the timeout value 250 ms.
Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Move init_clk_usdhc to non-clk driver case, since assigned-clocks properties
will initialize the clocks by clk driver.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
There is a number of users that use uclass_first_device to access the
first and (assumed) only device in uclass.
Some check the return value of uclass_first_device and also that a
device was returned which is exactly what uclass_first_device_err does.
Some are not checking that a device was returned and can potentially
crash if no device exists in the uclass. Finally there is one that
returns NULL on error either way.
Convert all of these to use uclass_first_device_err instead, the return
value will be removed from uclass_first_device in a later patch.
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Firmware calls need node_id which is basically "power-domains" id.
At present static values are used based on the "device_id" property of
dt.
Instead of this, read "power-domains" id from dt and use it. Add a
element called node_id in priv structure and read it from dt. Replace
static node_id with this priv->node_id across the driver.
Since "device_id" is not used anywhere else simply remove it.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220930092548.18453-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
In Versal platform power domain node_id is bigger than u8, hence
change prototype to u32 to accommodate. Change u8 to u32 in the function
prototypes that use node_id and remove casting to u32 from
xilinx_pm_request() call parameters.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220930092548.18453-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Add eMMC and SDXC support for MediaTek MT7981/MT7986 SoCs
Both chips support SDXC and eMMC 4.5. MT7986A supports eMMC 5.1.
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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Merge tag 'u-boot-at91-2023.01-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next
First set of u-boot-at91 features for the 2023.01 cycle:
This feature set includes the important update on PIO4 pinctrl driver
that solves a long time mismatch between Linux and U-boot, related on
the unification of pinctrl and gpio driver support, now respecting the
pinctrl bindings ABI; and also support for pinctrl subnodes. The feature
set also adds support for PDA screen detection for sam9x60_curiosity
board , one fix for SD-Card reinsertion and one fix for sam9x60 clocks.
Whenever the SD Card would be removed and then re-inserted while in the
U-Boot command line, the `SDBPWR` bit of the `SDMMC_PCR` register would
remain unset afterwards. In order for the bit to be set again after
re-insertion, register an additional `deferred_probe` method that the
DM would then transparently call. This method will call the generic
`sdhci_probe` which will, during its execution flow, set this bit to 1.
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reported-by: Mihai Sain <mihai.sain@microchip.com>
Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
Globally replace all occurances of WATCHDOG_RESET() with schedule(),
which handles the HW_WATCHDOG functionality and the cyclic
infrastructure.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
When fixed offset via CONFIG_SYS_MMC_U_BOOT_OFFS is not specified then
expects that U-Boot proper is placed immediately after SPL without any
additional padding.
This allows to generate smaller SPL+U-Boot final binary as it is not
required to specify fixed offset to U-Boot proper at SPL compile time.
In this case offset to U-Boot proper is calculated at SPL compile time in
linker script.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Marek Behún <kabel@kernel.org>
This allows to concatenate SPL and proper U-Boot without extra alignment.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Marek Behún <kabel@kernel.org>
We currently have an if_type (interface type) and a uclass id. These are
closely related and we don't need to have both.
Drop the if_type values and use the uclass ones instead.
Maintain the existing, subtle, one-way conversion between UCLASS_USB and
UCLASS_MASS_STORAGE for now, and add a comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
Selecting this option can be handled in the Kconfig option itself, as it
is with BLK. Update this an drop the various 'select' clauses.
Signed-off-by: Simon Glass <sjg@chromium.org>
This option is fact really related to SPL. For U-Boot proper we always use
driver model for block devices, so CONFIG_BLK is enabled if block devices
are in use.
It is only for SPL that we have two cases:
- SPL_BLK is enabled, in which case we use driver model and blk-uclass.c
- SPL_BLK is not enabled, in which case (if we need block devices) we must
use blk_legacy.c
Rename the symbol to SPL_LEGACY_BLOCK to make this clear. This is
different enough from BLK and SPL_BLK that there should be no confusion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Commit 44645f87de ("mmc: Fix mmc_switch excessive timeout") introduced
a side effect where CMD13 SEND_STATUS is issued in case mmc_wait_dat0()
does not return -ENOSYS and $send_status is not set. This happens on all
hardware which does implement .mmc_wait_dat0 callback, e.g. i.MX8M .
This leads to lengthy timeout before booting OS in case of eMMC in one
of the HS200/HS400 modes, since the card cannot respond to CMD13 while
downgrading from HS200/HS400 to regular HS mode.
Fix this by adding the missing conditional.
Fixes: 44645f87de ("mmc: Fix mmc_switch excessive timeout")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Kirill Kapranov <kirill.kapranov@compulab.co.il>
Cc: Marek Behún <marek.behun@nic.cz>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Ye Li <ye.li@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
sandbox_defconfig builds the PCI MMC driver. It should be possible to
build the sandbox without ACPI support.
ACPI support in the PCI MMC driver is only needed when creating an ACPI
table. Fix building with ACPIGEN=n.
Fixes: dba7ee419d ("acpi: mmc: Generate ACPI info for the PCI SD Card")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Add features to write protect single boot area rather than all boot
areas.
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Only newer eSDHC controllers set PRSSTAT_SDSTB flag. So do not wait until
flag PRSSTAT_SDSTB is set on old pre-2.2 controllers. Instead sleep for
fixed amount of time like it was before commit 6f883e501b ("mmc:
fsl_esdhc: Add emmc hs200 support").
This change fixes error 'Internal clock never stabilised.' which is printed
on P2020 board at every access to SD card.
Fixes: 6f883e501b ("mmc: fsl_esdhc: Add emmc hs200 support")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Timing macro's are wrong for MMC_HS_52 and MMC_DDR_52. Fix it with
correct values of MMC_TIMING_MMC_HS and MMC_TIMING_MMC_DDR52 respectively.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/1656319965-12124-1-git-send-email-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
For SDCC version 5.0.0, MCI registers are removed from SDCC interface
and some registers are moved to HC. So add support to use the new
compatible string "qcom,sdhci-msm-v5". Based on this new msm variant,
pick the relevant variant data and use it to detect MCI presence thereby
configuring register read/write to msm specific registers.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
SPL on mvebu loads proper U-Boot from custom Marvell kwbimage format and
therefore support for other binary formats is not required to be present in
SPL. Boot source of proper U-Boot is defined by compile time options and
therefore it is not required to enable all possible and unused peripherals
in SPL by default.
This change decrease size of SPL binaries.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Add the uclass ops of_to_plat to parse the device tree properties
to respect the expected sequence by the driver model.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
All the elements of privdata are static and build from device tree,
they are moved in platdata to prepare the support of ops
of_to_plat.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Rename stm32_sdmmc_bind to stm32_sdmmc2_bind as all other functions
in SDMMCv2 driver
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Ic51acdfbbba6e971809c1029dd2227038bfe879d
With the last platform for this architecture removed, remove the rest of
the architecture support as well.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tighten up symbol dependencies in a number of places. Ensure that a SPL
specific option has at least a direct dependency on SPL. In places
where it's clear that we depend on something more specific, use that
dependency instead. This means in a very small number of places we can
drop redundant dependencies.
Reported-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
The Aspeed SDHCI controller is arranged with some shared control
registers, followed by one or two sets of actual SDHCI registers.
Adjust the driver to probe this controller device first. The driver then
wants to iterate over the child nodes to probe the SDHCI proper:
ofnode node;
dev_for_each_subnode(node, parent) {
struct udevice *dev;
int ret;
ret = device_bind_driver_to_node(parent, "aspeed_sdhci",
ofnode_get_name(node),
node, &dev);
if (ret)
return ret;
}
However if we did this the sdhci driver would probe twice; once
"naturally" from the device tree and a second time due to this code.
Instead of doing this we can rely on the probe order, where the
controller will be set up before the sdhci devices. A better solution is
preferred.
Select MISC as the controller driver is implemented as a misc device.
Signed-off-by: Joel Stanley <joel@jms.id.au>
- Correct livetree support in stm32mp1 boards
- Activate livetree for stm32mp15 DHSOM boards
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Merge tag 'u-boot-stm32-20220620' of https://source.denx.de/u-boot/custodians/u-boot-stm into next
- Add STM32MP13 SoCs support with associated board STM32M135F-DK
- Correct livetree support in stm32mp1 boards
- Activate livetree for stm32mp15 DHSOM boards
Currently default fallback SDHC mode is 1-bit. Add new config option
CONFIG_SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH to allow specifying default fallback
mode. This is useful e.g. for SPL builds which loads other parts from SD
card during boot process.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
8-bit mode is not supported by SD cards and on P2020 are four SDHC pins
shared with SPI (so if P2020 board have also SPI then only 4-bit SDHC mode
is provided). So 8-bit SDHC mode is really bad default.
When max bus width is not provided then set mode to 1-bit. This mode is
supported by all cards, so it is the best option for fallback mode.
Also P2020 bootrom sets mode to 1-bit when booting from SD/MMC card.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Although not recommended, the reset property could be made optional.
This way the driver will probe even if no reset property is provided
in an sdmmc node in DT. This reset is already optional in Linux.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
There is no wait_dat0 mmc ops, causing operations waiting for data
line state change (e.g mmc_switch_voltage) to fallback to a 250ms
active delay. mmc_ops still used when DM_MMC is not enabled, which
is often the case for SPL. The result can be unexpectly long SPL
boot time.
This change adds support for wait_dat0() mmc operation.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Fix the end address in the message for unaligned erase request in
mmc_berase() when start + blkcnt is aligned to erase_grp_size.
for example:
- start = 0x2000 - 26
- count = 26
- erase_grp_size = 0x400
Caution! Your devices Erase group is 0x400
The erase range would be change to 0x2000~0x27ff
But no issue when the end address is not aligned, for example
- start = 0x2000 - 2 * 26
- count = 26
- erase_grp_size = 0x400
Caution! Your devices Erase group is 0x400
The erase range would be change to 0x2000~0x23ff
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
The phy used in the 8 bit instance has been changed to the phy used in 4
bit instance on AM62 SoC. This implies the phy configuration required for
both the instances of mmc are similar. Therefore, add a new compatible
for AM62 SoC using the driver data of am64 4 bit instance.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is needed on some Marvell SoCs when
booting from MMC. All existing usages of this have the same value so
make this the default and have the Kconfig option depend on SPL &&
MVEBU_SPL_BOOT_DEVICE_MMC.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
zynqmp:
- Fix DP PLL configuration for zcu102/zcu106 and SOM
- Fix split mode for starting R5s
- DT fixes
- Remove firmware node for mini configurations
- Wire TEE for multi DTB fit image
xilinx:
- Handle board_get_usable_ram_top(0) properly
phy:
- Extend psgtr timeout
mmc:
- Fix mini configuration which misses zynqmp_pm_is_function_supported()
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Merge tag 'xilinx-for-v2022.07-rc4' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2022.07-rc4
zynqmp:
- Fix DP PLL configuration for zcu102/zcu106 and SOM
- Fix split mode for starting R5s
- DT fixes
- Remove firmware node for mini configurations
- Wire TEE for multi DTB fit image
xilinx:
- Handle board_get_usable_ram_top(0) properly
phy:
- Extend psgtr timeout
mmc:
- Fix mini configuration which misses zynqmp_pm_is_function_supported()
The bulk of it is (finally!) some DT sync from the kernel. We refrained
from syncing one incompatible change, as this would spoil booting Linux
kernels before v5.13 with U-Boot's DT (via UEFI, for instance).
I test booted Linux v5.18 and v5.4 with that new DT on some boards, and
the headless peripherals (MMC, USB, Ethernet) seemed to work.
The rest are fixes:
- silencing missing clock warnings due to the new pinctrl driver
- fixing "UART0 on PortF", allowing UART access through the SD card pins
- add an F1C100s clock driver, to enable MMC support (SPI comes later)
- some cleanups for CONS_INDEX_n in Kconfig
Tested on BananaPi-M1, Pine64-LTS, Pine-H64, X96-Mate (H616) and
OrangePi-Zero.
Now that the pinmux conflict is handled in the board code (by skipping
setup for the one conflicting MMC controller), the driver does not need
to be entirely disabled based on the UART pinmux.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Commit 0980cbba7b ("mmc: fsl_esdhc_spl: pre-PBL: implement redundancy
support") changed number of sectors which are read but did not adjusted
error check.
Fix it and check for if correct number of sectors were read.
Fixes: 0980cbba7b ("mmc: fsl_esdhc_spl: pre-PBL: implement redundancy support")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
