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ee3630f0bc
zynqmp-mini-nand wasn't aligned with dt binding that's why fix it. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/3916fde2e896b8be8863505305118903e0644ab0.1717684544.git.michal.simek@amd.com
66 lines
1.1 KiB
Plaintext
66 lines
1.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* dts file for Xilinx ZynqMP Mini Configuration
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*
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* (C) Copyright 2018, Xilinx, Inc.
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*
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* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
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* Michal Simek <michal.simek@amd.com>
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*/
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/dts-v1/;
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/ {
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model = "ZynqMP MINI NAND";
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compatible = "xlnx,zynqmp";
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#address-cells = <2>;
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#size-cells = <1>;
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aliases {
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serial0 = &dcc;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x40000000>;
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};
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dcc: dcc {
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compatible = "arm,dcc";
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status = "disabled";
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bootph-all;
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};
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amba: amba {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges;
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nand0: nand@ff100000 {
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compatible = "arasan,nfc-v3p10";
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status = "okay";
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reg = <0x0 0xff100000 0x1000>;
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clock-names = "clk_sys", "clk_flash";
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#address-cells = <1>;
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#size-cells = <0>;
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arasan,has-mdma;
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num-cs = <2>;
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nand@0 {
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reg = <0>;
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#address-cells = <2>;
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#size-cells = <1>;
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nand-ecc-mode = "hw";
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};
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};
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};
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};
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&dcc {
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status = "okay";
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};
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