Yao Zi 85cfabe895 riscv: cpu: th1520: Support cache enabling/disabling in M mode only ...

These operations rely on a customized M-mode CSR, MHCR, which isn't
available when running in S mode.

Let's fallback to the generic weak stub when running in S mode to avoid
illegal accesses.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

2025-06-09 10:44:06 +08:00

..

andes

andes: Use UCCTLCOMMAND instead of MCCTLCOMMAND

2024-05-30 16:01:13 +08:00

ast2700

riscv: Add AST2700 SoC initial platform support

2024-09-11 20:35:03 +08:00

cv1800b

riscv: lib: Split out support for T-Head cache management operations

2025-05-21 16:49:52 +08:00

fu540

arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD

2024-10-11 11:44:47 -06:00

fu740

arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD

2024-10-11 11:44:47 -06:00

generic

riscv: cpu: generic: fallback to generic cleanup_before_linux()

2025-02-03 15:26:06 +08:00

jh7110

riscv: cpu: jh7110: fallback to generic cleanup_before_linux()

2025-02-03 15:26:06 +08:00

k1

Add reset config options for k1

2025-03-25 16:34:50 +08:00

k230

riscv: cpu: k230: Add support for Canaan Kendryte K230 SoC

2025-01-16 15:55:27 +08:00

th1520

riscv: cpu: th1520: Support cache enabling/disabling in M mode only

2025-06-09 10:44:06 +08:00

cpu.c

riscv: Access gd with inline assembly when building with LTO or Clang

2025-05-21 16:46:16 +08:00

Makefile

riscv: Move trap handler codes to mtrap.S

2018-12-18 09:56:27 +08:00

mtrap.S

riscv: Align the trap handler to 64 bytes

2023-11-02 15:15:46 +08:00

start.S

spl: Use CONFIG_VAL() to obtain the SPL stack

2025-03-13 10:36:10 -06:00

u-boot-spl.lds

riscv: Provide __image_copy_{start_end} symbols in linkerscript

2025-04-25 16:31:29 +08:00

u-boot.lds

riscv: Provide __image_copy_{start_end} symbols in linkerscript

2025-04-25 16:31:29 +08:00