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riscv: cpu: th1520: Support cache enabling/disabling in M mode only

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These operations rely on a customized M-mode CSR, MHCR, which isn't
available when running in S mode.

Let's fallback to the generic weak stub when running in S mode to avoid
illegal accesses.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Yao Zi 2025-05-30 09:48:48 +00:00 committed by Leo Yu-Chi Liang
parent 0463545678
commit 85cfabe895
1 changed files with 2 additions and 0 deletions
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2
arch/riscv/cpu/th1520/cache.c
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@ -11,6 +11,7 @@
#define CSR_MHCR_IE BIT(0)
#define CSR_MHCR_DE BIT(1)
#if CONFIG_IS_ENABLED(RISCV_MMODE)
void icache_enable(void)
{
csr_write(CSR_MHCR, csr_read(CSR_MHCR) | CSR_MHCR_IE);
@ -30,3 +31,4 @@ int dcache_status(void)
{
return (csr_read(CSR_MHCR) & CSR_MHCR_DE) != 0;
}
#endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */