Benoît Thébaudeau ada02b8463 imx: mx6q DDR3 init: Fix SDE_to_RST
MMDC1_MDOR.SDE_to_RST should be set to 200 µs according to the JEDEC
specification for DDR3. With a cycle of 15.258 µs, this gives 14 cycles encoded
as 0x10 for the bit-field MMDC1_MDOR[13:8].

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-02-12 13:52:30 +01:00
..
2012-12-05 17:31:23 +01:00
2011-11-27 19:44:21 +01:00
2010-12-09 10:25:56 +01:00
2012-02-12 15:03:25 -05:00
2011-10-15 22:20:36 +02:00
2010-12-09 10:25:56 +01:00
2010-12-09 10:25:56 +01:00
2012-04-01 21:37:53 +10:00
2011-10-15 22:20:36 +02:00
2012-12-17 15:38:14 +01:00
2012-10-15 11:54:14 -07:00
2011-10-15 22:20:36 +02:00
2011-10-15 22:20:36 +02:00
2012-03-26 23:09:23 +02:00
2012-11-20 00:16:07 +01:00
2011-10-15 22:20:36 +02:00
2010-12-09 10:25:56 +01:00
2010-12-09 10:25:56 +01:00
2010-11-28 21:45:32 +01:00
2012-02-12 15:03:25 -05:00
2011-10-15 22:20:36 +02:00
2012-10-04 16:59:13 +02:00
2011-10-15 22:20:36 +02:00
2012-10-04 16:57:36 +02:00