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8c0eb06fbe
If DISP1 is a PLLD/D2 child, it cannot go over 370MHz. The cause of this is not quite clear. This can be overcomed by further halving the PLLD/D2 if the target parent rate is over 800MHz. This way DISP1 and DSI clocks will have the same frequency. The shift divider in this case has to be calculated from the original PLLD/D2 frequency and is passed from the DSI driver. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565 Tested-by: Ion Agorria <ion@agorria.com> # HTC One X Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Microsoft Surface 2 Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com>
46 lines
1.4 KiB
C
46 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2010
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#ifndef _TEGRA_DC_H
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#define _TEGRA_DC_H
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#endif
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/* arch-tegra/dc exists only because T124 uses it */
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#include <asm/arch-tegra/dc.h>
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#define TEGRA_DC_A "dc@54200000"
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#define TEGRA_DC_B "dc@54240000"
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#define TEGRA_DSI_A "dsi@54300000"
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#define TEGRA_DSI_B "dsi@54400000"
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struct tegra_dc_plat {
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struct udevice *dev; /* Display controller device */
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struct dc_ctlr *dc; /* Display controller regmap */
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bool pipe; /* DC number: 0 for A, 1 for B */
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ulong scdiv; /* Shift clock divider */
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};
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/* This holds information about a window which can be displayed */
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struct disp_ctl_win {
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enum win_color_depth_id fmt; /* Color depth/format */
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unsigned int bpp; /* Bits per pixel */
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phys_addr_t phys_addr; /* Physical address in memory */
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unsigned int x; /* Horizontal address offset (bytes) */
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unsigned int y; /* Veritical address offset (bytes) */
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unsigned int w; /* Width of source window */
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unsigned int h; /* Height of source window */
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unsigned int stride; /* Number of bytes per line */
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unsigned int out_x; /* Left edge of output window (col) */
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unsigned int out_y; /* Top edge of output window (row) */
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unsigned int out_w; /* Width of output window in pixels */
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unsigned int out_h; /* Height of output window in pixels */
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};
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#endif /* _TEGRA_DC_H */
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