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fd55792e14
The instruction and data cache line sizes of Andes core are 64-byte. Select SYS_CACHE_SHIFT_6 for RISCV_NDS so the SYS_CACHELINE_SIZE is enabled with a default value. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
18 lines
478 B
Plaintext
18 lines
478 B
Plaintext
config RISCV_NDS
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bool
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select ARCH_EARLY_INIT_R
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select SYS_CACHE_SHIFT_6
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imply CPU
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imply CPU_RISCV
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imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
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imply ANDES_PLMT_TIMER
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imply SPL_ANDES_PLMT_TIMER
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imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE)
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imply V5L2_CACHE
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imply SPL_CPU
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imply SPL_OPENSBI
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imply SPL_LOAD_FIT
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help
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Run U-Boot on AndeStar V5 platforms and use some specific features
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which are provided by Andes Technology AndeStar V5 families.
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