Yu Chien Peter Lin fd55792e14 riscv: andesv5: Set default cache line size to 64-bytes ...

The instruction and data cache line sizes of Andes core
are 64-byte. Select SYS_CACHE_SHIFT_6 for RISCV_NDS so
the SYS_CACHELINE_SIZE is enabled with a default value.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

2024-05-01 22:40:00 +08:00

..

cache.c

riscv: Remove common.h usage

2023-10-24 16:34:45 -04:00

cpu.c

andes: cpu: Enable cache and TLB ECC support

2023-12-27 17:29:07 +08:00

Kconfig

riscv: andesv5: Set default cache line size to 64-bytes

2024-05-01 22:40:00 +08:00

Makefile

riscv: Rename Andes cpu and board names

2023-02-17 19:07:48 +08:00

spl.c

riscv: Remove common.h usage

2023-10-24 16:34:45 -04:00