mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2025-08-15 11:46:59 +02:00
a5ac47911a
We currently set both and print both PXN and UXN bits when removing
execution for pages. This happens even in the existing per platform
definitions of 'struct mm_region'.
That's not entirely correct though. For stage-1 translations, if a
platform runs on a translation regime with a single privilege level or the
the translation regime supports two privilege levels and we are not
in EL1&0 with HCR_EL2.{NV, NV1} = {1, 1} only BIT54 (XN) is needed
and BIT53(PXN) is reserved 0.
Currently we support Non-Secure EL2, Non-secure EL2&0 and Non-secure
EL1&0.
We already have get_effective_el() which returns 1 if we are
- Running in EL1 so we assume an EL1 translation regime but without
checking HCR_EL2.{NV, NV1} != {1,1}
- Running in EL2 with HCR_EL2.E2H = 1
The only problem with the above is that if we are in EL1&0 and
HCR_EL2.{NV1, NV} == {1, 1}, then
- Bit[54] holds the PXN instead of the UXN
- The Effective value of UXN is 0
- Bit[53] is RES0
So let's re-use that function and set PXN only when we are in
and EL[2|1]&0 translation regime.
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
|
||
|---|---|---|
| .. | ||
| bcmns3 | ||
| fsl-layerscape | ||
| hisilicon | ||
| xen | ||
| acpi_park_v8.S | ||
| cache_v8.c | ||
| cache.S | ||
| config.mk | ||
| cpu-dt.c | ||
| cpu.c | ||
| exception_level.c | ||
| exceptions.S | ||
| fel_utils.S | ||
| fwcall.c | ||
| generic_timer.c | ||
| Kconfig | ||
| linux-kernel-image-header-vars.h | ||
| Makefile | ||
| psci.S | ||
| sec_firmware_asm.S | ||
| sec_firmware.c | ||
| sha1_ce_core.S | ||
| sha1_ce_glue.c | ||
| sha256_ce_core.S | ||
| sha256_ce_glue.c | ||
| smccc-call.S | ||
| spin_table_v8.S | ||
| spin_table.c | ||
| spl_data.c | ||
| start.S | ||
| sysinfo.c | ||
| tlb.S | ||
| transition.S | ||
| u-boot-spl.lds | ||
| u-boot.lds | ||