Yao Zi 3dbff9eecc riscv: lib: Split out support for T-Head cache management operations ... Designed before a standard set of cache management operations defined in RISC-V, earlier T-Head cores like C906 and C910 provide CMO through the customized extension XTheadCMO, which has been used in the CV1800B port of U-Boot. This patch splits XTheadCMO-related code into a generic module, allowing SoCs shipping T-Head cores to share the code. Link: https://github.com/XUANTIE-RV/thead-extension-spec Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>		2025-05-21 16:49:52 +08:00
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andes	andes: Use UCCTLCOMMAND instead of MCCTLCOMMAND	2024-05-30 16:01:13 +08:00
ast2700	riscv: Add AST2700 SoC initial platform support	2024-09-11 20:35:03 +08:00
cv1800b	riscv: lib: Split out support for T-Head cache management operations	2025-05-21 16:49:52 +08:00
fu540	arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD	2024-10-11 11:44:47 -06:00
fu740	arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD	2024-10-11 11:44:47 -06:00
generic	riscv: cpu: generic: fallback to generic cleanup_before_linux()	2025-02-03 15:26:06 +08:00
jh7110	riscv: cpu: jh7110: fallback to generic cleanup_before_linux()	2025-02-03 15:26:06 +08:00
k1	Add reset config options for k1	2025-03-25 16:34:50 +08:00
k230	riscv: cpu: k230: Add support for Canaan Kendryte K230 SoC	2025-01-16 15:55:27 +08:00
cpu.c	riscv: Access gd with inline assembly when building with LTO or Clang	2025-05-21 16:46:16 +08:00
Makefile	riscv: Move trap handler codes to mtrap.S	2018-12-18 09:56:27 +08:00
mtrap.S	riscv: Align the trap handler to 64 bytes	2023-11-02 15:15:46 +08:00
start.S	spl: Use CONFIG_VAL() to obtain the SPL stack	2025-03-13 10:36:10 -06:00
u-boot-spl.lds	riscv: Provide __image_copy_{start_end} symbols in linkerscript	2025-04-25 16:31:29 +08:00
u-boot.lds	riscv: Provide __image_copy_{start_end} symbols in linkerscript	2025-04-25 16:31:29 +08:00