Masahisa Kojima f81aaa0b33 spi: synquacer: simplify tx completion checking
There is a TX-FIFO and Shift Register empty(TFES) status
bit in spi controller. This commit checks the TFES bit
to wait the TX transfer completes.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-06-10 13:37:32 -04:00
..
2020-06-11 15:14:04 +05:30
2022-03-30 13:02:55 -04:00
2022-01-19 18:11:34 +01:00
2021-09-25 09:46:15 -06:00
2021-06-25 20:59:45 +05:30
2021-02-23 10:45:55 -05:00