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8d05cbef73
AM62P SoC has multiple speed grades. Add function to delete non-relevant CPU frequency nodes, based on the information retrieved from hardware registers. Fastest grade's maximum frequency also depends on PMIC voltage, hence to simplify implementation use the smaller value. Signed-off-by: Aparna Patra <a-patra@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com>
149 lines
4.3 KiB
C
149 lines
4.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* K3: AM62Px SoC definitions, structures etc.
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*
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* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef __ASM_ARCH_AM62P_HARDWARE_H
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#define __ASM_ARCH_AM62P_HARDWARE_H
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#include <config.h>
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#endif
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#define PADCFG_MMR0_BASE 0x04080000
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#define PADCFG_MMR1_BASE 0x000f0000
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#define CTRL_MMR0_BASE 0x00100000
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#define MCU_CTRL_MMR0_BASE 0x04500000
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#define WKUP_CTRL_MMR0_BASE 0x43000000
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#define CTRLMMR_WKUP_JTAG_DEVICE_ID (WKUP_CTRL_MMR0_BASE + 0x18)
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#define JTAG_DEV_CORE_NR_MASK GENMASK(19, 18)
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#define JTAG_DEV_CORE_NR_SHIFT 18
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#define JTAG_DEV_CANFD_MASK BIT(15)
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#define JTAG_DEV_CANFD_SHIFT 15
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#define JTAG_DEV_VIDEO_CODEC_MASK BIT(14)
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#define JTAG_DEV_VIDEO_CODEC_SHIFT 14
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#define JTAG_DEV_SPEED_MASK GENMASK(10, 6)
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#define JTAG_DEV_SPEED_SHIFT 6
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#define JTAG_DEV_TEMP_MASK GENMASK(5, 3)
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#define JTAG_DEV_TEMP_SHIFT 3
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#define JTAG_DEV_TEMP_AUTOMOTIVE 0x5
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#define JTAG_DEV_TEMP_EXTENDED_VALUE 105
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#define JTAG_DEV_TEMP_AUTOMOTIVE_VALUE 125
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#define CTRLMMR_MAIN_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
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#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(6, 3)
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#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
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#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK GENMASK(9, 7)
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#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7
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#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK GENMASK(12, 10)
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#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10
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#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK BIT(13)
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#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13
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/* Primary Bootmode MMC Config macros */
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#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x4
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#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2
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#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK 0x1
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#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT 0
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/* Primary Bootmode USB Config macros */
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#define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT 1
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#define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02
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/* Backup Bootmode USB Config macros */
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#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01
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/*
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* The CTRL_MMR0 memory space is divided into several equally-spaced
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* partitions, so defining the partition size allows us to determine
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* register addresses common to those partitions.
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*/
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#define CTRL_MMR0_PARTITION_SIZE 0x4000
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/*
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* CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism
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* shared register definitions. The same registers are also used for
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* PADCFG_MMR lock/kick-mechanism.
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*/
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#define CTRLMMR_LOCK_KICK0 0x1008
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#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
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#define CTRLMMR_LOCK_KICK1 0x100c
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#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
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#define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038)
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#define MCU_CTRL_LFXOSC_TRIM (MCU_CTRL_MMR0_BASE + 0x803c)
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#define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7)
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#define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL (MCU_CTRL_MMR0_BASE + 0x8058)
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#define MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL (0x3)
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#define ROM_EXTENDED_BOOT_DATA_INFO 0x43c4f1e0
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#define K3_BOOT_PARAM_TABLE_INDEX_OCRAM 0x7000F290
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#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c30000
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static inline int k3_get_core_nr(void)
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{
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u32 dev_id = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
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return ((dev_id & JTAG_DEV_CORE_NR_MASK) >> JTAG_DEV_CORE_NR_SHIFT) + 1;
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}
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static inline int k3_has_video_codec(void)
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{
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u32 dev_id = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
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return !((dev_id & JTAG_DEV_VIDEO_CODEC_MASK) >> JTAG_DEV_VIDEO_CODEC_SHIFT);
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}
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static inline int k3_has_canfd(void)
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{
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u32 dev_id = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
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return (dev_id & JTAG_DEV_CANFD_MASK) >> JTAG_DEV_CANFD_SHIFT;
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}
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static inline int k3_get_max_temp(void)
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{
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u32 dev_id = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
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u32 dev_temp = (dev_id & JTAG_DEV_TEMP_MASK) >> JTAG_DEV_TEMP_SHIFT;
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if (dev_temp == JTAG_DEV_TEMP_AUTOMOTIVE)
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return JTAG_DEV_TEMP_AUTOMOTIVE_VALUE;
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else
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return JTAG_DEV_TEMP_EXTENDED_VALUE;
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}
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static inline char k3_get_speed_grade(void)
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{
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u32 dev_id = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
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u32 speed_grade = (dev_id & JTAG_DEV_SPEED_MASK) >>
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JTAG_DEV_SPEED_SHIFT;
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return 'A' - 1 + speed_grade;
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}
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static inline int k3_get_a53_max_frequency(void)
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{
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if (k3_get_speed_grade() == 'O')
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return 1000000000;
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else
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return 1250000000;
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}
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#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__)
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static const u32 put_device_ids[] = {};
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static const u32 put_core_ids[] = {};
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#endif
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#endif /* __ASM_ARCH_AM62P_HARDWARE_H */
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