4 Commits

Author SHA1 Message Date
Aparna Patra
8d05cbef73 arm: mach-k3: am62p: Fixup a53 max cpu frequency by speed-grade
AM62P SoC has multiple speed grades. Add function to delete
non-relevant CPU frequency nodes, based on the information
retrieved from hardware registers. Fastest grade's maximum
frequency also depends on PMIC voltage, hence to simplify
implementation use the smaller value.

Signed-off-by: Aparna Patra <a-patra@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2025-01-14 15:50:07 -06:00
Aparna Patra
a226a6422c arm: mach-k3: am62p: Fixup thermal zone critical points
Read the max temperature for the SoC temperature grade from the hardware
and modify the critical trip nodes on each thermal zone of FDT at
runtime so they are correct with the hardware value for its grade.

Signed-off-by: Aparna Patra <a-patra@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2025-01-14 15:50:07 -06:00
Aparna Patra
e44098d1aa arm: mach-k3: am62p: Fixup CPU core, CAN-FD and Video-codec nodes in fdt
AM62P SOC is available in multiple variants:
-CPU cores (Cortex-A) AM62Px1 (1 core),
 AM62Px2 (2 cores), AM62Px4 (4 cores)
-With and without CAN-FD & Video-codec support

Remove the relevant FDT nodes by reading the actual configuration
from the SoC registers, with that change it is possible to have a single
dts/dtb file handling the different variant at runtime.

Signed-off-by: Aparna Patra <a-patra@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2025-01-14 15:50:07 -06:00
Bryan Brattlof
7f88327e94 arch: mach-k3: introduce basic files to support the am62px SoC family
Introduce the basic functions and definitions needed to properly
initialize TI's am62p family of SoCs

Signed-off-by: Bryan Brattlof <bb@ti.com>
2024-03-13 10:10:05 -04:00