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5b359312e5
The PCIe PIPE clock requires a special setup function to mux & enable the clock from the PCIe PHY before the PHY has enabled the clock. Import the clk_phy_mux_enable() from the Linux driver to use the same implementation regarding the PIPE clock. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241125-topic-pcie-clk-v1-1-4315d1e4e164@linaro.org Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
119 lines
2.8 KiB
C
119 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
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*/
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#ifndef _CLOCK_QCOM_H
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#define _CLOCK_QCOM_H
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#include <asm/io.h>
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#include <linux/bitfield.h>
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#define CFG_CLK_SRC_CXO (0 << 8)
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#define CFG_CLK_SRC_GPLL0 (1 << 8)
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#define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8)
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#define CFG_CLK_SRC_GPLL9 (2 << 8)
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#define CFG_CLK_SRC_GPLL0_ODD (3 << 8)
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#define CFG_CLK_SRC_GPLL6 (4 << 8)
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#define CFG_CLK_SRC_GPLL7 (3 << 8)
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#define CFG_CLK_SRC_GPLL4 (5 << 8)
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#define CFG_CLK_SRC_GPLL0_EVEN (6 << 8)
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#define CFG_CLK_SRC_MASK (7 << 8)
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#define RCG_CFG_REG 0x4
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#define RCG_M_REG 0x8
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#define RCG_N_REG 0xc
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#define RCG_D_REG 0x10
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struct pll_vote_clk {
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uintptr_t status;
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int status_bit;
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uintptr_t ena_vote;
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int vote_bit;
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};
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struct vote_clk {
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uintptr_t cbcr_reg;
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uintptr_t ena_vote;
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int vote_bit;
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};
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struct freq_tbl {
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uint freq;
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uint src;
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u8 pre_div;
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u16 m;
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u16 n;
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};
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#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
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struct gate_clk {
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uintptr_t reg;
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u32 en_val;
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const char *name;
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};
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#ifdef DEBUG
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#define GATE_CLK(clk, reg, val) [clk] = { reg, val, #clk }
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#else
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#define GATE_CLK(clk, reg, val) [clk] = { reg, val, NULL }
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#endif
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struct qcom_reset_map {
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unsigned int reg;
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u8 bit;
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};
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struct qcom_power_map {
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unsigned int reg;
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};
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struct clk;
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struct msm_clk_data {
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const struct qcom_power_map *power_domains;
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unsigned long num_power_domains;
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const struct qcom_reset_map *resets;
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unsigned long num_resets;
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const struct gate_clk *clks;
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unsigned long num_clks;
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const phys_addr_t *dbg_pll_addrs;
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unsigned long num_plls;
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const phys_addr_t *dbg_rcg_addrs;
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unsigned long num_rcgs;
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const char * const *dbg_rcg_names;
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int (*enable)(struct clk *clk);
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unsigned long (*set_rate)(struct clk *clk, unsigned long rate);
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};
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struct msm_clk_priv {
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phys_addr_t base;
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struct msm_clk_data *data;
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};
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int qcom_cc_bind(struct udevice *parent);
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void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0);
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void clk_bcr_update(phys_addr_t apps_cmd_rgcr);
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void clk_enable_cbc(phys_addr_t cbcr);
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void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk);
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const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate);
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void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr,
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int div, int m, int n, int source, u8 mnd_width);
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void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div,
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int source);
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void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled);
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static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
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{
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u32 val;
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if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0)
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return;
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val = readl(priv->base + priv->data->clks[id].reg);
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writel(val | priv->data->clks[id].en_val, priv->base + priv->data->clks[id].reg);
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}
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#endif
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