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clk: qcom: add clk_phy_mux_enable() for PCIe PIPE clock

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The PCIe PIPE clock requires a special setup function to
mux & enable the clock from the PCIe PHY before the PHY
has enabled the clock.

Import the clk_phy_mux_enable() from the Linux driver to
use the same implementation regarding the PIPE clock.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241125-topic-pcie-clk-v1-1-4315d1e4e164@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
This commit is contained in:
Neil Armstrong 2024-11-25 09:34:26 +01:00 committed by Caleb Connolly
parent bc09b58e2a
commit 5b359312e5
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GPG Key ID: 7930459FB9303217
2 changed files with 21 additions and 0 deletions
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19
drivers/clk/qcom/clock-qcom.c
View File

@ -166,6 +166,25 @@ void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div,
clk_bcr_update(base + cmd_rcgr);
}
#define PHY_MUX_MASK GENMASK(1, 0)
#define PHY_MUX_PHY_SRC 0
#define PHY_MUX_REF_SRC 2
void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled)
{
u32 cfg;
/* setup src select and divider */
cfg = readl(base + cmd_rcgr);
cfg &= ~(PHY_MUX_MASK);
if (enabled)
cfg |= FIELD_PREP(PHY_MUX_MASK, PHY_MUX_PHY_SRC);
else
cfg |= FIELD_PREP(PHY_MUX_MASK, PHY_MUX_REF_SRC);
writel(cfg, base + cmd_rcgr);
}
const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate)
{
if (!f)

2
drivers/clk/qcom/clock-qcom.h
View File

@ -6,6 +6,7 @@
#define _CLOCK_QCOM_H
#include <asm/io.h>
#include <linux/bitfield.h>
#define CFG_CLK_SRC_CXO (0 << 8)
#define CFG_CLK_SRC_GPLL0 (1 << 8)
@ -102,6 +103,7 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr,
int div, int m, int n, int source, u8 mnd_width);
void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div,
int source);
void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled);
static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
{