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Add SPL_PHY_J721E_WIZ configuration option to enable the WIZ SERDES wrapper driver in SPL stage. This is required for PCIe boot support where SERDES configuration must be done early in the boot sequence before loading the bootloader image over PCIe. Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
20 lines
768 B
Plaintext
20 lines
768 B
Plaintext
config PHY_J721E_WIZ
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tristate "TI J721E WIZ (SERDES Wrapper) support"
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depends on ARCH_K3
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help
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This option enables support for WIZ module present in TI's J721E
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SoC. WIZ is a serdes wrapper used to configure some of the input
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signals to the SERDES (Sierra/Torrent). This driver configures
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three clock selects (pll0, pll1, dig) and resets for each of the
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lanes.
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config SPL_PHY_J721E_WIZ
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bool "TI J721E WIZ (SERDES Wrapper) support"
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depends on ARCH_K3
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help
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This option enables support for WIZ module present in TI's J721E
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SoC at SPL stage. WIZ is a serdes wrapper used to configure some
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of the input signals to the SERDES (Sierra/Torrent). This driver
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configures three clock selects (pll0, pll1, dig) and resets for
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each of the lanes.
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