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phy: ti: Add config to enable J721E WIZ SERDES wrapper at SPL stage

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Add SPL_PHY_J721E_WIZ configuration option to enable the WIZ SERDES
wrapper driver in SPL stage. This is required for PCIe boot support
where SERDES configuration must be done early in the boot sequence
before loading the bootloader image over PCIe.

Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
This commit is contained in:
Hrushikesh Salunke 2026-02-16 15:58:31 +05:30 committed by Tom Rini
parent 2a21f48771
commit 35e1083fb9
1 changed files with 10 additions and 0 deletions
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drivers/phy/ti/Kconfig
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@ -7,3 +7,13 @@ config PHY_J721E_WIZ
signals to the SERDES (Sierra/Torrent). This driver configures
three clock selects (pll0, pll1, dig) and resets for each of the
lanes.
config SPL_PHY_J721E_WIZ
bool "TI J721E WIZ (SERDES Wrapper) support"
depends on ARCH_K3
help
This option enables support for WIZ module present in TI's J721E
SoC at SPL stage. WIZ is a serdes wrapper used to configure some
of the input signals to the SERDES (Sierra/Torrent). This driver
configures three clock selects (pll0, pll1, dig) and resets for
each of the lanes.