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4267b414dc
Add a driver for the power regulators of the MediaTek MT6357 PMIC chip. Signed-off-by: Julien Masson <jmasson@baylibre.com> Co-developed-by: Macpaul Lin <macpaul.lin@mediatek.com> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Signed-off-by: David Lechner <dlechner@baylibre.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
160 lines
5.2 KiB
C
160 lines
5.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2026 BayLibre, SAS.
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* Author: Julien Masson <jmasson@baylibre.com>
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*/
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#ifndef _REGULATOR_MT6357_H_
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#define _REGULATOR_MT6357_H_
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#define MT6357_REGULATOR_DRIVER "mt6357_regulator"
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enum {
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/* Bucks */
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MT6357_ID_VCORE,
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MT6357_ID_VMODEM,
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MT6357_ID_VPA,
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MT6357_ID_VPROC,
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MT6357_ID_VS1,
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/* LDOs */
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MT6357_ID_VAUX18,
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MT6357_ID_VAUD28,
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MT6357_ID_VCAMA,
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MT6357_ID_VCAMD,
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MT6357_ID_VCAMIO,
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MT6357_ID_VCN18,
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MT6357_ID_VCN28,
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MT6357_ID_VCN33_BT,
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MT6357_ID_VCN33_WIFI,
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MT6357_ID_VDRAM,
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MT6357_ID_VEFUSE,
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MT6357_ID_VEMC,
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MT6357_ID_VFE28,
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MT6357_ID_VIBR,
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MT6357_ID_VIO18,
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MT6357_ID_VIO28,
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MT6357_ID_VLDO28,
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MT6357_ID_VMC,
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MT6357_ID_VMCH,
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MT6357_ID_VRF12,
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MT6357_ID_VRF18,
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MT6357_ID_VSIM1,
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MT6357_ID_VSIM2,
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MT6357_ID_VSRAM_OTHERS,
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MT6357_ID_VSRAM_PROC,
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MT6357_ID_VUSB33,
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MT6357_ID_VXO22,
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};
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/* PMIC Registers */
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#define MT6357_BUCK_TOP_CLK_CON0 0x140c
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#define MT6357_BUCK_TOP_CLK_HWEN_CON0 0x1412
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#define MT6357_BUCK_TOP_CLK_MISC_CON0 0x1418
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#define MT6357_BUCK_TOP_INT_CON0 0x141a
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#define MT6357_BUCK_TOP_INT_MASK_CON0 0x1420
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#define MT6357_BUCK_TOP_SLP_CON0 0x142c
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#define MT6357_BUCK_TOP_OC_CON0 0x1434
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#define MT6357_BUCK_TOP_K_CON0 0x1436
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#define MT6357_BUCK_VPROC_CON0 0x1488
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#define MT6357_BUCK_VPROC_DBG0 0x14a2
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#define MT6357_BUCK_VPROC_ELR0 0x14aa
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#define MT6357_BUCK_VCORE_CON0 0x1508
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#define MT6357_BUCK_VCORE_DBG0 0x1522
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#define MT6357_BUCK_VCORE_ELR0 0x152a
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#define MT6357_BUCK_VMODEM_CON0 0x1588
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#define MT6357_BUCK_VMODEM_DBG0 0x15a2
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#define MT6357_BUCK_VMODEM_ELR0 0x15aa
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#define MT6357_BUCK_VS1_CON0 0x1608
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#define MT6357_BUCK_VS1_DBG0 0x1622
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#define MT6357_BUCK_VS1_ELR0 0x1632
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#define MT6357_BUCK_VPA_CON0 0x1688
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#define MT6357_BUCK_VPA_CON1 0x168a
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#define MT6357_BUCK_VPA_DBG0 0x1692
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#define MT6357_BUCK_VPA_DLC_CON0 0x1698
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#define MT6357_BUCK_VPA_MSFG_CON0 0x169e
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#define MT6357_LDO_TOP_CLK_DCM_CON0 0x188c
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#define MT6357_LDO_TOP_CLK_VIO28_CON0 0x188e
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#define MT6357_LDO_TOP_CLK_VIO18_CON0 0x1890
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#define MT6357_LDO_TOP_CLK_VAUD28_CON0 0x1892
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#define MT6357_LDO_TOP_CLK_VDRAM_CON0 0x1894
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#define MT6357_LDO_TOP_CLK_VSRAM_PROC_CON0 0x1896
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#define MT6357_LDO_TOP_CLK_VSRAM_OTHERS_CON0 0x1898
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#define MT6357_LDO_TOP_CLK_VAUX18_CON0 0x189a
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#define MT6357_LDO_TOP_CLK_VUSB33_CON0 0x189c
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#define MT6357_LDO_TOP_CLK_VEMC_CON0 0x189e
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#define MT6357_LDO_TOP_CLK_VXO22_CON0 0x18a0
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#define MT6357_LDO_TOP_CLK_VSIM1_CON0 0x18a2
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#define MT6357_LDO_TOP_CLK_VSIM2_CON0 0x18a4
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#define MT6357_LDO_TOP_CLK_VCAMD_CON0 0x18a6
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#define MT6357_LDO_TOP_CLK_VCAMIO_CON0 0x18a8
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#define MT6357_LDO_TOP_CLK_VEFUSE_CON0 0x18aa
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#define MT6357_LDO_TOP_CLK_VCN33_CON0 0x18ac
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#define MT6357_LDO_TOP_CLK_VCN18_CON0 0x18ae
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#define MT6357_LDO_TOP_CLK_VCN28_CON0 0x18b0
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#define MT6357_LDO_TOP_CLK_VIBR_CON0 0x18b2
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#define MT6357_LDO_TOP_CLK_VFE28_CON0 0x18b4
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#define MT6357_LDO_TOP_CLK_VMCH_CON0 0x18b6
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#define MT6357_LDO_TOP_CLK_VMC_CON0 0x18b8
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#define MT6357_LDO_TOP_CLK_VRF18_CON0 0x18ba
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#define MT6357_LDO_TOP_CLK_VLDO28_CON0 0x18bc
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#define MT6357_LDO_TOP_CLK_VRF12_CON0 0x18be
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#define MT6357_LDO_TOP_CLK_VCAMA_CON0 0x18c0
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#define MT6357_LDO_TOP_CLK_TREF_CON0 0x18c2
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#define MT6357_LDO_TOP_INT_CON0 0x18c4
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#define MT6357_LDO_TOP_INT_MASK_CON0 0x18d0
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#define MT6357_LDO_TEST_CON0 0x18e4
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#define MT6357_LDO_TOP_WDT_CON0 0x18e6
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#define MT6357_LDO_TOP_RSV_CON0 0x18e8
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#define MT6357_LDO_VXO22_CON0 0x1908
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#define MT6357_LDO_VAUX18_CON0 0x191c
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#define MT6357_LDO_VAUD28_CON0 0x1930
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#define MT6357_LDO_VIO28_CON0 0x1944
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#define MT6357_LDO_VIO18_CON0 0x1958
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#define MT6357_LDO_VDRAM_CON0 0x196c
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#define MT6357_LDO_VEMC_CON0 0x1988
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#define MT6357_LDO_VUSB33_CON0_0 0x199c
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#define MT6357_LDO_VSRAM_PROC_CON0 0x19b2
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#define MT6357_LDO_VSRAM_PROC_DBG0 0x19cc
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#define MT6357_LDO_VSRAM_OTHERS_CON0 0x19d0
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#define MT6357_LDO_VSRAM_OTHERS_DBG0 0x19ea
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#define MT6357_LDO_VSRAM_WDT_DBG0 0x19f6
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#define MT6357_LDO_VSRAM_CON0 0x19fa
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#define MT6357_LDO_VSRAM_CON1 0x19fc
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#define MT6357_LDO_VFE28_CON0 0x1a08
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#define MT6357_LDO_VRF18_CON0 0x1a1c
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#define MT6357_LDO_VRF12_CON0 0x1a30
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#define MT6357_LDO_VEFUSE_CON0 0x1a44
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#define MT6357_LDO_VCN18_CON0 0x1a58
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#define MT6357_LDO_VCAMA_CON0 0x1a6c
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#define MT6357_LDO_VCAMD_CON0 0x1a88
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#define MT6357_LDO_VCAMIO_CON0 0x1a9c
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#define MT6357_LDO_VMC_CON0 0x1ab0
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#define MT6357_LDO_VMCH_CON0 0x1ac4
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#define MT6357_LDO_VSIM1_CON0 0x1ad8
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#define MT6357_LDO_VSIM2_CON0 0x1aec
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#define MT6357_LDO_VIBR_CON0 0x1b08
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#define MT6357_LDO_VCN33_CON0_0 0x1b1c
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#define MT6357_LDO_VCN33_CON0_1 0x1b2a
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#define MT6357_LDO_VLDO28_CON0_0 0x1b32
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#define MT6357_LDO_GOFF2_RSV_CON0 0x1b48
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#define MT6357_LDO_VCN28_CON0 0x1b88
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#define MT6357_LDO_TREF_CON0 0x1b9e
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#define MT6357_LDO_GOFF3_RSV_CON0 0x1bae
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#define MT6357_VXO22_ANA_CON0 0x1c18
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#define MT6357_VCN33_ANA_CON0 0x1c1c
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#define MT6357_VEMC_ANA_CON0 0x1c20
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#define MT6357_VLDO28_ANA_CON0 0x1c24
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#define MT6357_VIBR_ANA_CON0 0x1c2c
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#define MT6357_VSIM1_ANA_CON0 0x1c30
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#define MT6357_VSIM2_ANA_CON0 0x1c34
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#define MT6357_VMCH_ANA_CON0 0x1c38
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#define MT6357_VMC_ANA_CON0 0x1c3c
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#define MT6357_VUSB33_ANA_CON0 0x1c88
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#define MT6357_VCAMA_ANA_CON0 0x1c8c
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#define MT6357_VEFUSE_ANA_CON0 0x1c90
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#define MT6357_VCAMD_ANA_CON0 0x1c94
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#define MT6357_VDRAM_ELR_2 0x1cac
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#endif
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