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c5d685b899
This patch merges flush and reset logic for both host and gadget code into a common set of functions, reducing duplication. It also adds support for the updated reset logic to compatible with core version since v4.20a. This patch mainly refers to the patch in the kernel. link: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=65dc2e725286106f99c6f6b78e3d9c52c15f3a9c Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Tested-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Reviewed-by: Marek Vasut <marex@denx.de> Link: https://lore.kernel.org/r/20250110-dwc2-dev-v4-7-987f4fd6f8b2@pigmoral.tech Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
132 lines
3.5 KiB
C
132 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2024-2025, Kongyang Liu <seashell11234455@gmail.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <wait_bit.h>
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#include "dwc2_core.h"
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int dwc2_core_reset(struct dwc2_core_regs *regs)
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{
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u32 snpsid;
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int ret;
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bool host_mode = false;
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if (!(readl(®s->global_regs.gotgctl) & GOTGCTL_CONID_B) ||
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(readl(®s->global_regs.gusbcfg) & GUSBCFG_FORCEDEVMODE))
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host_mode = true;
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/* Core Soft Reset */
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snpsid = readl(®s->global_regs.gsnpsid);
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writel(GRSTCTL_CSFTRST, ®s->global_regs.grstctl);
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if (FIELD_GET(GSNPSID_VER_MASK, snpsid) < 0x420a) {
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ret = wait_for_bit_le32(®s->global_regs.grstctl, GRSTCTL_CSFTRST,
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false, 1000, false);
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if (ret) {
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log_warning("%s: Waiting for GRSTCTL_CSFTRST timeout\n", __func__);
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return ret;
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}
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} else {
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ret = wait_for_bit_le32(®s->global_regs.grstctl, GRSTCTL_CSFTRST_DONE,
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true, 1000, false);
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if (ret) {
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log_warning("%s: Waiting for GRSTCTL_CSFTRST_DONE timeout\n", __func__);
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return ret;
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}
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clrsetbits_le32(®s->global_regs.grstctl, GRSTCTL_CSFTRST, GRSTCTL_CSFTRST_DONE);
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}
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/* Wait for AHB master IDLE state. */
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ret = wait_for_bit_le32(®s->global_regs.grstctl, GRSTCTL_AHBIDLE,
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true, 1000, false);
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if (ret) {
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log_warning("%s: Waiting for GRSTCTL_AHBIDLE timeout\n", __func__);
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return ret;
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}
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if (host_mode) {
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ret = wait_for_bit_le32(®s->global_regs.gintsts, GINTSTS_CURMODE_HOST,
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host_mode, 1000, false);
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if (ret) {
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log_warning("%s: Waiting for GINTSTS_CURMODE_HOST timeout\n", __func__);
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return ret;
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}
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}
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return 0;
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}
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int dwc2_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
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{
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int ret;
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log_debug("Flush Tx FIFO %d\n", num);
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/* Wait for AHB master IDLE state */
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ret = wait_for_bit_le32(®s->global_regs.grstctl, GRSTCTL_AHBIDLE, true, 1000, false);
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if (ret) {
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log_warning("%s: Waiting for GRSTCTL_AHBIDLE timeout\n", __func__);
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return ret;
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}
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writel(GRSTCTL_TXFFLSH | FIELD_PREP(GRSTCTL_TXFNUM_MASK, num), ®s->global_regs.grstctl);
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ret = wait_for_bit_le32(®s->global_regs.grstctl, GRSTCTL_TXFFLSH, false, 1000, false);
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if (ret) {
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log_warning("%s: Waiting for GRSTCTL_TXFFLSH timeout\n", __func__);
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return ret;
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}
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/*
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* Wait for at least 3 PHY clocks.
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*
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* The PHY clock frequency can be configured to 6/30/48/60 MHz
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* based on the speed mode. A fixed delay of 1us ensures that the
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* wait time is sufficient even at the lowest PHY clock frequency
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* (6 MHz), where 1us corresponds to twice the duration of 3 PHY
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* clocks.
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*/
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udelay(1);
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return 0;
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}
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int dwc2_flush_rx_fifo(struct dwc2_core_regs *regs)
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{
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int ret;
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log_debug("Flush Rx FIFO\n");
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/* Wait for AHB master IDLE state */
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ret = wait_for_bit_le32(®s->global_regs.grstctl, GRSTCTL_AHBIDLE, true, 1000, false);
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if (ret) {
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log_warning("%s: Waiting for GRSTCTL_AHBIDLE timeout\n", __func__);
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return ret;
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}
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writel(GRSTCTL_RXFFLSH, ®s->global_regs.grstctl);
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ret = wait_for_bit_le32(®s->global_regs.grstctl, GRSTCTL_RXFFLSH, false, 1000, false);
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if (ret) {
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log_warning("%s: Waiting for GRSTCTL_RXFFLSH timeout\n", __func__);
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return ret;
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}
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/*
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* Wait for at least 3 PHY clocks.
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*
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* The PHY clock frequency can be configured to 6/30/48/60 MHz
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* based on the speed mode. A fixed delay of 1us ensures that the
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* wait time is sufficient even at the lowest PHY clock frequency
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* (6 MHz), where 1us corresponds to twice the duration of 3 PHY
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* clocks.
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*/
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udelay(1);
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return 0;
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}
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