This patch adds pwm support for MediaTek MT7987 SoC.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
The reserved-memory node 'wmcpu-reserved@50000000' only applies to
linux kernel and is useless in u-boot.
Remove it in *-u-boot.dtsi to make this memory region usable.
Fixes: 2d6962e0618 (arm: mediatek: add support for MediaTek MT7987 SoC)
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Assorted fixes, refactorings and additions that are ready, and shave
off some load from upcoming series'.
Improves MMC performance on D1/T113 (missed clock divider), enables
eMMC access on the H616 family (never worked, many thanks to Jernej for
the fix!), DRAM detection fixes for the H616 (now reportedly stable).
Some patches for the upcoming Allwinner A133 SoC support: a few
refactorings, plus the DM clock and pinctrl driver. The DRAM init
routines work, but need some more polishing, that also holds back the
actual enablement patch, which will hopefully follow for v2025.07 still.
Also some preparatory patches for the Allwinner A523 SoC support, for
now just to improve the FEL save/restore code. There will be more patches
coming up for this, ideally also in the coming cycle still.
Gitlab CI passed, and I booted that briefly on some boards.
Because the Allwinner BootROM always runs in AArch32, even on ARMv8 SoCs,
we need to switch to AArch64 first, but also need to save the CPU state,
when we later may need to return to the BootROM, for continuing with the
FEL USB protocol. This is done in 32-bit code, which we include into the
AArch64 boot assembly file as a series of .word directives, containing
the encoded AArch32 instructions. To be able to change and verify that
code, we also kept an assembly file with the respective 32-bit code, but
just for reference.
As this code is never compiled or assembled - it's just for
documentation - it became stale over time: we didn't really update this
along with the changes we made to the boot code. In particular the FEL
save code was completely missing.
Update that 32-bit assembly file, to match the current version used in
boot0.h, including the FEL save routine. Also update the build
instructions in the comments, to give people an actual chance to
assemble this code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
To be able to return to the BootROM when booting via the FEL USB
protocol, we need to save the CPU state very early, which we need to do
in the embedded AArch32 code. At the moment the pointer to the buffer for
that state is located *after* the code, which makes the PC relative
code fragile: adding or removing instructions will change the distance
to that pointer variable.
The "new" Allwinner A523 SoC requires more state to be saved (GICv3
system registers), but we must do that *only* on that SoC. Conditional
compilation sounds like the easiest solution, but would mean that the
distance to that pointer would change.
Solve this rather easily by moving the pointer to the *front* of the
code: we load that pointer in the first instructions, so the distance
would always stay the same. Later in the code we won't need PC relative
addressing anymore, so this code can grow or shrink easily, for instance
due to conditional compilation.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
To return a 64-bit Allwinner chip back to the 32-bit BootROM code, we
have some embedded AArch32 code that restores the CPU state, before
branching back to the BootROM. At the moment the pointer to the buffer
with that state is located *after* the code, which makes the PC relative
code fragile: adding or removing instructions will change the distance
to that pointer variable.
The "new" Allwinner A523 SoC requires more state to be restored (GICv3
system registers), but we must do that *only* on that SoC. Conditional
compilation sounds like the easiest solution, but would mean that the
distance to that pointer would change.
Solve this rather easily by moving the pointer to the *front* of the
code: we load that pointer in the first instruction, so the distance
would always stay the same. Later in the code we won't need PC relative
addressing anymore, so this code can grow or shrink easily, for instance
due to conditional compilation.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
It turns out that checking just one write is not enough. Due to
unexplained reasons scan procedure detected double the size. By making
16 dword writes and comparisons that never happens.
New procedure is also inverted. Instead of writing two different values
to base address and some offset and then reading both and comparing
values, simplify this by writing pattern at the base address and then
search for this pattern at some offset.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Ryan Walklin <ryan@testtoast.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Since there is quite a few possible DRAM configurations in terms of bus
width, rank and rows and columns count, size detection algorithm must be
very careful not to test combination which would be bigger than H616 is
actually capable of handling.
Ideally, we should always detect memory aliasing, even for 4 GB memory
size, which is the maximum amount of memory that H616 is capable of
handling. For this reason, we have to configure minimum amount of
supported rows when testing for columns and vice versa. This way test
code will never step out of 4 GB boundary.
While at it, check for 17 rows maximum. This aligns code with BSP DRAM
driver. There is probably no such configuration which would make sense
with 4 GB memory.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
The Allwinner A100 SoC has been around for a while, and has now seemingly
been replaced with its close sibling A133.
Add support for the CCU, as far as used by U-Boot proper. Linux has some
basic (clock and pinctrl) support for a while, so we can already use the
existing binding headers.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Most Allwinner SoCs (used on 107 out of 172 boards) use a default CPU
frequency of 1008 MHz during the initial setup in the SPL.
Make this the fallback default, in case nothing else is selected, to
simplify the Kconfig stanza and make future additions easier.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Some of the X-Power AXP PMICs can be ordered with an alternative I2C
address, for instance an AXP717 could be shipped with address 0x34 or
with address 0x35. Similarly the AXP803 lists two possible addresses.
For DM (DT) based drivers this is no problem, but the Allwinner SPL
code relies on exactly one hardcoded address per PMIC so far.
Add a Kconfig variable that holds the I2C address used by the PMIC
accessed in the SPL, and provide the (mostly only one) supported address
as its default, for the PMICs we use. Boards using the other address
can easily set this in their defconfig.
This effectively moves the hardcoding from C code to Kconfig.
That enables to use the AXP717 on some boards with the new Allwinner
A523 chip, which use the other I2C address there.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
On the Allwinner D1/R528/T113-s3 SoCs (NCAT2) the factors encoded in
the PLL register describe the doubled clock rate, as in the other SoCs.
Correct for that by always dividing the calculated rate by 2, except on
the H6, where we need a divisor of 4 (no change here).
This corrects the PERIPH0 clock rate as read by the MMC driver, and
actually doubles the MMC performance on those NCAT2 chips.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reported-by: Kuba Szczodrzyński <kuba@szczodrzynski.pl>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The CHIP_DIP_SCAN configuration option
is relevant only to ARCH_SUNXI.
Make CHIP_DIP_SCAN dependent
on ARCH_SUNXI so that it does not show up on other goals.
Signed-off-by: Liya Huang <1425075683@qq.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
The imx8_cpu driver is a CPU Driver that supports the i.MX9
family to display the CPU type, temperature grade and
current operating temperature. The older file,
arch/arm/mach-imx/cpu.c, does not support i.MX9, so this config
is enabled in various IMX9 boards. Instead of having this option
enabled in every IMX9, select this driver by default for the
platform.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The imx8_cpu driver is a CPU Driver that supports the i.MX8Q
family. When it is enabled, it acts as an alternative to
arch/arm/mach-imx/cpu.c, but the imx8_cpu supports the driver
model where cpu.c does not. Imply this newer driver by default.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The imx8_cpu driver is a CPU Driver that supports the i.MX8M
family, and when it is enabled, it acts as an alternative to
arch/arm/mach-imx/cpu.c, but the imx8_cpu supports the driver
model where cpu.c does not. Imply this newer driver by default.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
If the CPU Information is displayed from imx8_cpu, it displays the
cpu temperature grade and operating temperature if CONFIG_IMX9 is
defined. This behavior is similar to what happens mach-imx/cpu.c,
except that the latter checks for IMX_THERMAL or IMX_TMU.
In preparation to make imx8_cpu act like the previous implementation
for any CPU, make IMX8M imply IMX_TMU so it will be always displayed
unless a user decides to disable it.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
If the CPU Information is displayed from imx8_cpu, it displays
the cpu temperature grade and operating temperature if
CONFIG_IMX9 is defined. This behavior is similar to what
happens arch/arm/mach-imx/cpu.c except that the latter
checks for CONFIG_IMX_THERMAL or CONFIG_IMX_TMU.
In preparation to make imx8_cpu act like the previous
implementation for any CPU, make IMX9 imply IMX_TMU, so
it will be always displayed unless a user decides to
disable it.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
As binman already creates nodes based on CONFIG_OF_LIST we don't need to
add extra nodes.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # StarFIve VisionFive 2
Reviewed-by: E Shattow <e@freeshell.de>
JH7110 boards are currently the only use case for multi DTB FIT images
on RISC-V.
Booting JH7110 systems with a VisionFive 2 device-tree used to kind of
work without causing harm to the hardware. But there is no guarantee
that this will hold true in future. So we should not rely on it.
Before the current patch series booting failed on unsupported boards due
to the lack of a device-tree in the binman generated default configuration
when reaching main U-Boot.
By not setting a default configuration booting will now fail on
unsupported boards already in SPL. This allows SPL to
continue with the next boot source for a possible recovery.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: E Shattow <e@freeshell.de>
Binman can automatically generate device-tree and configuration entries in
the FIT image based on CONFIG_MULTI_DTB_FIT if the binman node includes the
right sub-nodes.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: E Shattow <e@freeshell.de>
Introduced in commit 5a4e0625ac77 ("riscv: dts: sophgo: Add ethernet
node"), eth_{csrclk,ptpclk} were used as placeholders for ethernet
controller. As the real clock controller has been added, drop them to
clean the devicetree up.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
take 2
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEtlGhRjxqvtBpDFXNBYMxKxlfZLYFAmfhkqIACgkQBYMxKxlf
ZLY5Ig/+J9R0ZC9qJxQXZHANfWRUsCwn9UDnc/cYgo6eD/E87Tgdr85vlH44JOh9
wka2ysn6H4IaN7Ca4435GUjntvuhJ85HLXhbBuQXOT27fHSIV0MJq94jvGwDzSps
IOy9JSYHhbs5tP33ekXfLYlL60BFqcTm22VXUfAXD9mMkDonbh4vq1LPxskVj8iq
85k5F2GyFm5cU4H5nQpgI+6+LQSJ/FlraOGNOYQj7MiQzTxPkWL6hC+p+9RuJAbt
NLJiDd3oQUgpo9/jQseteNXrUfQYsUmuzjrz71V2Z9saIHKw+AuVcnr/EanynjiJ
JjKdQ3Xmu3zwdTGP3/c/ZIxy1vKq4qoVnjzHo8x/am7euPNnj9lS7liq618/qhtv
AuCf6SSpXqKFMejXn/mF28sO0merI5oM3OB7AEL+BOH5HIaNr39PyAQ+8HKh5tmb
7lB1z/LjSPvpapQOZqj2XTBcNuxFT6rD4Nl5CFlJLjcGdMd6BRpCulE8z/53VSwH
FDEi0pqsN4No1anA8XMial7BEtCrM1e9NO3X+RRXCbxGZHa37fwlFmzTbpqUZcRA
iv0YmXvv2PT3+W/tuwS8d2ZgTSctFSAoKd5B9iuDiuNko/teUbKFREY7E/rB7Oky
AcNUT6ILmsqNg+BnkXu3Z+NP+Ms30FOxK/pEptek0vfLwJuAhg8=
=2n9a
-----END PGP SIGNATURE-----
Merge tag 'qcom-next-20250324' of https://gitlab.denx.de/u-boot/custodians/u-boot-snapdragon into next
qcom-next-20230324:
* msm8916 gets proper sysreset and spin-table support
* The first new IPQ platform is added - the IPQ9574. The IPQ series are
used in routers. The flashing process is also documented
* mach-snapdragon gains the ability to boot with an internal FDT and
still parse memory from an externally provided one
* SC7280 gets a pinctrl driver and various clock driver improvements.
* Qualcom clock drivers will now actually return an error when
attempting
to enable a clock which isn't described.
* Qualcomm pinctrl drivers will now return an error when attempting to
configure an invalid function mux
The Ouya microconsole is build on Nvidia Tegra 3 (T33) SoC, featuring a
quad-core 1.7 GHz ARM Cortex-A9 CPU and a ULP GeForce GPU, paired with 1GB
of DDR3 RAM and 8GB of internal flash storage. Running a modified Android
4.1 (Jelly Bean) OS with a custom launcher, it aimed for open-source gaming
via a digital storefront.
This implementation is mostly based on upstream Linux device tree and
fragments of work done by previous developers.
Co-developed-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
The names used for displaya, displayb and i2c1 do not align with their
corresponding Linux counterparts. This inconsistency can cause pins to be
configured incorrectly, potentially breaking existing functionality.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Modify the pin state lists for lock, io-reset, rcv-sel, and e-io-hv
properties by repositioning the default value to the end. This change
addresses conflicts with device tree representations of TEGRA_PIN_DISABLE
and TEGRA_PIN_ENABLE.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Align TF700T bindings with existing upstream device trees. OF_UPSTREAM
migration is possible already but resulting size of binary exceeds maximum
allowed size with full size trees.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Upgrade HTC One X device tree to comply possible upstream Linux device
tree. Once Linux catches up, HTC One X can be switched to OF_UPSTREAM.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Upgrade LG P895 and P880 device tree bindings according to preliminary
upstream Linux tree. Once Linux catches up, LG X3 can be switched to
OF_UPSTREAM without regressions.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Simon Glass <sjg@chromium.org> says:
This series includes some patches related to allowing read_all() to be
used with the extlinux / PXE bootmeths.
These patches were split out from the stb4 series, since it will need to
have additional patches for LWIP, to avoid breaking PXE booting when
LWIP is used.
Link: https://lore.kernel.org/r/20250306002533.2380866-1-sjg@chromium.org
Adjust the remaining call in this function to use the bootm API. This
will allow PXE to work without the command line.
Signed-off-by: Simon Glass <sjg@chromium.org>
Arm invented a new format for arm64 and something similar is also used
with RISC-V. Add this to the list of supported formats and provide a way
for the format to be detected on both architectures.
Update the genimg_get_format() function to support this.
Fix up switch() statements which don't currently mention this format.
Booti does not support a ramdisk, so this can be ignored.
Signed-off-by: Simon Glass <sjg@chromium.org>
The address of the bzImage is not recorded in the bootflow, so we cannot
actually locate the version at present. Handle this case, to avoid
showing invalid data.
Signed-off-by: Simon Glass <sjg@chromium.org>
Rather than holding the state in the implementation code, move it to the
command code. The state is now passed to the implementation functions
and can there (with future work) be pass in from bootstd, without going
through the commands.
Signed-off-by: Simon Glass <sjg@chromium.org>
This structure is supposed to handle any type of booting
programmatically, i.e. without needing a command to be executed. Move
the x86-specific members into it and use it instead of
struct zboot_state. Provide a macro so access is possible without adding
lots of #ifdefs to the code.
This will allow the struct to be used for all four types of booting
(bootm, bootz, booti and zboot).
Call bootm_init() to init the state, to match other boot methods.
Note that some rationalisation could be performed on this. But this
is tricky since addresses are stored as strings in several places. Also
some strings combine multiple arguments into one. So to keep this task
somewhat manageable, we content ourselves with just getting everything
into the same struct
Signed-off-by: Simon Glass <sjg@chromium.org>
