This pull request delivers a broad set of improvements across the
SoCFPGA family, including Agilex5, Cyclone V, SoC64, and common code.
Key updates include refined boot flows, new driver enablement, handoff
tooling enhancements, and several stability fixes.
Highlights:
* Agilex5:
- Enable FAT-based environment storage
- MMC driver restores legacy clkmgr-based clock lookup
- Cleanup of MMC raw mode enablement logic
* Cyclone V:
- SPL FAT boot support and updated bootcmd sequence
- Disable SPL SPI to prevent contention with FAT-based boot
- New board handoff script and BSP generator tooling
- Optimized Makefile support for SoCFPGA handoff workflows* New drivers:
- Cadence xSPI driver with full protocol and command support
- SPL enablement for DW APB GPIO controller
* Networking:
- xgmac MDIO now supports Clause 45 read/write operations
* NAND / SoC64:
- Enable ONFI detection in Denali NAND controller for SoC64 devices
* DTS and board updates:
- Sync common SoCFPGA U-Boot DTS with kernel sources
- Fixes for FPGA2SDRAM configuration and SoCFPGA boot stall behavior
- Vining_FPGA migrated to the modern LED framework
- Device tree relocation no longer forced off for Vining FPGA
* Tooling:
- Introduces a new Python-based Cyclone V BSP generator
covering EMIF, IOCSR, HPS, XML parsing, rendering, and documentation
to simplify board enablement and handoff regeneration workflows
Overall, this series improves boot robustness, enhances xSPI and MDIO
capabilities, modernizes board support, and introduces new tooling to
streamline SoCFPGA handoff generation.
Pipelines test passing
https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/28569
bcm54210e_config() configures the RGMII delays and then calls
bcm5461_config(). But the latter will do a PHY soft reset and thus
resets the delay settings again. Call bcm5461_config() first to fix it.
Fixes: cba79a1b2e11 ("net: phy: broadcom: add support for BCM54210E")
Signed-off-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Rafał Miłecki <rafal@milecki.pl>
According to the TI DP83869HM datasheet Revision D (June 2025), section
7.6.1.41 STRAP_STS Register, the STRAP_OPMODE bitmask is bit [11:9].
Fix this.
In case the PHY is auto-detected via PHY ID registers, or not described
in DT, or, in case the PHY is described in DT but the optional DT property
"ti,op-mode" is not present, then the driver reads out the PHY functional
mode (RGMII, SGMII, ...) from hardware straps.
Currently, all upstream users of this PHY specify both DT compatible string
"ethernet-phy-id2000.a0f1" and ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>
property, therefore it seems no upstream users are affected by this bug.
The driver currently interprets bits [2:0] of STRAP_STS register as PHY
functional mode. Those bits are controlled by ANEG_DIS, ANEGSEL_0 straps
and an always-zero reserved bit. Systems that use RGMII-to-Copper functional
mode are unlikely to disable auto-negotiation via ANEG_DIS strap, or change
auto-negotiation behavior via ANEGSEL_0 strap. Therefore, even with this bug
in place, the STRAP_STS register content is likely going to be interpreted
by the driver as RGMII-to-Copper mode.
However, for a system with PHY functional mode strapping set to other mode
than RGMII-to-Copper, the driver is likely to misinterpret the strapping
as RGMII-to-Copper and misconfigure the PHY.
For example, on a system with SGMII-to-Copper strapping, the STRAP_STS
register reads as 0x0c20, but the PHY ends up being configured for
incompatible RGMII-to-Copper mode.
Fixes: f3e22eea815d ("net: phy: add TI DP83869HM ethernet driver")
Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Use FIELD_GET()
Currently, clause-22 format is supported. This change adds
support for clause-45 format.
Signed-off-by: Nikunj Kela <nikunj.kela@sima.ai>
Reviewed-by: Boon Khai Ng <boon.khai.ng@altera.com>
Tested-by: Boon Khai Ng <boon.khai.ng@altera.com>
Reviewed-by: Boon Khai Ng <boon.khai.ng@altera.com>
Tested-by: Boon Khai Ng <boon.khai.ng@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Currently, the bind callback of the driver namely am65_cpsw_nuss_bind()
registers all ethernet ports including the ones that have been disabled
in the device-tree. Since the ports that have been disabled are ought to
be ignored, fix the implementation to register only the enabled ports as
indicated by their 'status' in their respective device-tree node.
Fixes: 3943531a5468 ("net: ti: am65-cpsw-nuss: Define bind method for CPSW driver")
Reported-by: Wadim Egorov <w.egorov@phytec.de>
Closes: https://patch.msgid.link/8b4ac072-125c-493b-b12a-f0a4e9d56e7e@phytec.de
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Fix compiler warnings about casting integers to pointers of different
sizes by using uintptr_t as intermediate type. This ensures proper
type conversion across 32-bit and 64-bit architectures.
Signed-off-by: Sai Varun Venkatapuram <saivarun.venkatapuram@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/11b1d9b1a5589d06cff724e807832f366794c075.1762510401.git.michal.simek@amd.com
Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> says:
This patch series adds basic support for the boards based on Airoha
EN7523/EN7529/EN7562 SoCs. Due to ATF restrictions these boards are
able to run 32-bit OS only.
This patch series adds support for the following hardware:
* console UART
* ethernet controller/switch
* spinand flash (in non-dma mode)
The following issues may be expected:
* Extra slow UBI attaching in U-Boot (up to 20 sec with fastmap enabled).
This is caused by the lack of DMA support in the U-Boot airoha-snfi driver.
* Linux airoha-snfi driver in some cases might damage you flash data
(see: https://lore.kernel.org/lkml/20251012121707.2296160-15-mikhail.kshevetskiy@iopsys.eu/)
* Latest linux kernel is recommended to properly support flashes
with more than one plane per lun
(see: https://lore.kernel.org/lkml/20251012121707.2296160-7-mikhail.kshevetskiy@iopsys.eu/)
* It's NOT recommended to use flashes working in continuous mode because
U-Boot airoha-snfi driver does not support such flashes properly.
The patches was tested on the board:
- SoC: Airoha EN7562
- RAM: 512 MB
- SPI NAND: 4 Gbit, made by Toshiba
- Linux boot: was NOT tested
The U-Boot was chain-loaded from the running U-Boot. Airoha ATF-2.3 does
not allow easily chain-loading of U-Boot from U-Boot, so a special FIT
image (mimic linux kernel) was created
1) Create u-boot.its file with the following contents:
=== cut here ===
/dts-v1/;
/ {
description = "ARM OpenWrt FIT (Flattened Image Tree)";
#address-cells = <1>;
images {
u-boot-ram {
description = "OpenWrt U-Boot RAM image";
data = /incbin/("u-boot.bin.lzma");
type = "kernel";
arch = "arm";
os = "linux";
compression = "lzma";
load = <0x81e00000>;
entry = <0x81e00000>;
hash@1 {
algo = "crc32";
};
hash@2 {
algo = "sha1";
};
};
fdt-1 {
description = "OpenWrt device tree blob";
data = /incbin/("dts/upstream/src/arm/airoha/en7523-evb.dtb");
type = "flat_dt";
arch = "arm";
compression = "none";
hash@1 {
algo = "crc32";
};
hash@2 {
algo = "sha1";
};
};
};
configurations {
default = "config-ram-uboot";
config-ram-uboot {
description = "OpenWrt RAM U-Boot";
kernel = "u-boot-ram";
fdt = "fdt-1";
};
};
};
==================
2) Create u-boot.itb image to chain-load new u-boot from the old one
lzma_alone e u-boot.bin u-boot.bin.lzma
mkimage -f u-boot.its u-boot.itb
3) Load new u-boot from the old one
U-Boot> tftpboot u-boot.itb && bootm
Link: https://lore.kernel.org/r/20251101004503.2379529-1-mikhail.kshevetskiy@iopsys.eu
This allow us remove some an7581/an7583 specific code and use a common
code instead.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Add support for the Renesas Ethernet Switch3 (RSW3) controller,
present in R-Car Gen5 SoCs such as R-Car X5H (R8A78000). The
hardware offset differences are handled via driver match data.
The driver newly detects whether the switch prot is connected
to xPCS or not, and if so, turns on MIOC bit 3. This is new on
R-Car X5H. GWCKSC register is also programmed only on X5H. The
rest of the operation is identical to RSwitch2.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
The MPIC_MDC_CLK clock setting value differs between R-Car S4
and R-Car X5H. Parametrize the value in preparation for R-Car
X5H addition into this driver. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The GWDCBAC0, GWDCBAC1, FWPBFCSDC, CABPIRM register offsets changed
between R-Car S4 and R-Car X5H. Parametrize their offsets in preparation
for R-Car X5H addition into this driver. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Inline FWRO, CARO, GWRO, TARO, RMRO macros directly into the
follow up register macros. FWRO, CARO, GWRO, TARO are already
zero, drop them. RMRO is 0x1000, increment all registers which
add RMRO by 0x1000 directly. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The forwarding engine CSD register offset changed between the
R-Car S4 and R-Car X5H. Parametrize this offset in preparation
for R-Car X5H addition into this driver. Clean up the macro
parameter names and make them more obvious. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The total port counts differ across variants of this IP in
R-Car S4 and R-Car X5H. Parametrize port count in preparation
for R-Car X5H addition into this driver. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The COMA, ETHA, GWCA offsets differ across variants of this IP in
R-Car S4 and R-Car X5H. Parametrize these offsets in preparation
for R-Car X5H addition into this driver. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This IP does support operating MII and SerDes via different ports.
Currently, the driver assumes that MII and SerDes are always bound
together on the same port, but this may not be the case. Implement
support for controlling MII and SerDes separately.
While the change is extensive, the gist of the change is to pass
pointer to the selected port registers to MII or SerDes functions,
depending on which port and operations should be done on that port.
Each combined ETHA instance contains both MII and SerDes register
pointers, which may not point to the same port, and passes those
registers to MII and SerDes functions respectively to control the
MII or SerDes of each port.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The new version of RSwitch3 in Renesas R-Car Gen5 uses multiple
clock to supply the IP. Convert the driver to bulk clock API to
cater for both single clock of R-Car S4 and multiple clock of
R-Car Gen5. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Empty RX DMA descriptor must contain .die_dt field set to DT_FEMPTY,
because hardware DMA overwrites this field to non-DT_FEMPTY when data
are received, and the .recv callback tests the content of RX descriptor
.die_dt field to determine whether hardware did receive any data and
updated the .die_dt field, and based on that information, receives a
packet or not. Fix the incorrect RX DMA descriptor initialization to
assure the .recv callback always works correctly.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Fix indent from multiple spaces to tabs, to be consistent with
coding style and the rest of the driver. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add support for the optional 'phy-supply' property in the ENETC MDIO
driver. This allows the driver to enable and manage the PHY's power
supply via the regulator framework when specified in device tree.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Extend the NETC block control driver to support the i.MX94 SoC.
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
A device-tree property is already defined to indicate that the internal
PHY should be used with active-low leds, which corresponds to a
specific bit in the dedicated syscon register.
Add support for setting this bit when the property is present.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
We know about all the relevant fields in the syscon register so there
is no reason to read it first and modify it.
Build the register from scratch instead, with all relevant fields set.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
The Synchronous Abort and reset errors occurred due
to incorrect parameter passing during initialization.
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
[jf: add missing #if IS_ENABLED(CONFIG_BITBANGMII)]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
With commit 597fe041a85f ("net/phy: enable get_phy_id redefinable") we
made get_phy_id a public but weak function, so that PHY drivers that had
required non-standard ways of getting the PHY ID could be supported.
However, overloading a weak function multiple times is (rightly) a link
error. At this point, we have two PHYs which make use of this feature,
so make both of them only available when COMPILE_TEST is unset, as part
of being able to support "allyesconfig" in the future.
Signed-off-by: Tom Rini <trini@konsulko.com>
Synchronize paged PHY helpers with Linux v6.17.
Add support for PHY devices that use paged register access by
implementing the following functions:
- phy_save_page(): Save current page number
- phy_select_page(): Switch to a specific page and return previous page
- phy_restore_page(): Restore previously saved page
Also adds read_page and write_page callbacks to the phy_driver
structure to enable driver-specific page handling.
These helpers allow safe access to paged PHY registers by ensuring
proper page selection and restoration,
even in error conditions, which will be used by the Airoha PHY driver.
Signed-off-by: Lucien.Jheng <lucienzx159@gmail.com>
The commit 997786bbf473 ("drivers/net/airoha_eth: fix stalling in package
receiving") can be improved. Instead of returning previous descriptor
it's possible:
* do nothing in even descriptor case
* return 2 descriptor to the queue (current and previous) in the odd
descriptor case.
This patch:
* implements above approach
* remove logic not required within new approach
* adds note that PKTBUFSRX must be even and larger than 7
for reliable driver operations
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
In preparation for support of MDIO on AN7581, move the MT7531 MMIO logic
to a dedicated driver and permit usage of the mdio read/write function
to the mtk_eth driver.
This only affect MT7988 that can use MMIO operation to access the Switch
register. The MT7988 code is updated to make use of the external driver.
This permits Airoha driver to make use of DM_MDIO to bind for the MT7531
driver that have the same exact register.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Correctly free the MDIO Bus on calling cleanup function. While at it
also fix a copy-paste error and rename the cleanup function name to the
more specific name.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
On exiting the phy_setting function for MT7988, the PHY page is never
restored to Page 0. This can cause all kind of problem with reading the
status of the PHY at runtime.
Correctly restore PHY page on exiting the PHY setting function.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The PHY for MT7531/MT7988 are never actully turned ON/OFF for the
affected PHY as we are read/writing to the wrong PHY address.
This is caused by the fact that we use the MT753X_PHY_ADDR macro 2
times offsetting the address multiple times.
One in the _setup() function and one in the mt7531_mii_read/write.
Drop the additional usage of MT753X_PHY_ADDR in setup() to correctly
set the PHY.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
In this case, the mediatek network drivers cannot build outside of
ARCH_MEDIATEK or ARCH_MTMIPS, and so express this requirement in Kconfig
as well. In the case of DWC_ETH_XGMAC / DWC_ETH_XGMAC_SOCFPGA, the file
controlled by the DWC_ETH_XGMAC option references a socfpga-specific
array defined in the file controlled by DWC_ETH_XGMAC_SOCFPGA. Rework
these options in Kconfig to handle this dependency.
Signed-off-by: Tom Rini <trini@konsulko.com>
Some drivers which depend on SoCFPGA specific headers had not had
appropriate dependencies list in Kconfig. Add ARCH_SOCFPGA or
TARGET_SOCFPGA_SOC64 where appropriate.
Signed-off-by: Tom Rini <trini@konsulko.com>
The am65-cpsw driver currently sets the SEL_RGMII_IDMODE flag in a MAC's
mode register to enable or disable the TX delay. While this was supported
for earlier generations of the CPSW controller, the datasheets of all
modern TI SoCs using the am65-cpsw MAC state that the TX delay is fixed,
and the SEL_RGMII_IDMODE bit is documented as reserved in most of them.
Furthermore, while it was found that this bit does in fact disable the TX
delay, [1] states that this setting is truly unsupported by TI and not
just undocumented.
Following the clarification of the rgmii* phy-mode values in the Linux
DT bindings in [2], the Linux am65-cpsw driver was changed in [3] to
account for the fixed TX delay by fixing up the mode passed to the PHY
driver; a similar fixup already existed in the TI icssg-prueth driver.
[4] followed up on this by explicitly clearing the SEL_RGMII_IDMODE flag
to handle the case where it is set by the bootloader or other firmware
before Linux.
With the above changes, Device Trees that set the recommended "rgmii-id"
mode are now appearing in Linux 6.17+. Avoid setting the unsupported
SEL_RGMII_IDMODE flag for such Device Trees, and instead fix up the PHY
interface mode, thus aligning the U-Boot driver with the Linux kernel.
[1] https://www.spinics.net/lists/netdev/msg1112647.html
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c360eb0c3ccb95306704fd221442283ee82f1f58
[3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ca13b249f291f4920466638d1adbfb3f9c8db6e9
[4] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=a22d3b0d49d411e64ed07e30c2095035ecb30ed2
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
The script based firmware loader does not use anything from the
fs_loader implementation. Separate it into its own library source
file and convert the mediatek PHY to use this separate code. This
should reduce the amount of code that is pulled in alongside the
firmware loader, as the FS loader is no longer included.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add 10GBE high-speed Mac support, it supports 10G, 5G, 2.5G and 1G speeds.
10GBE high speed Mac is an extension of the current 1G Mac in versal,
inheriting all its current features.
MMI 10GBE ip has two internal PCS's.
1)10GBASER PCS is used for higher speeds 10G and 5G.
2)1000BASEX PCS is used for slower speeds 1G and 2.5G.
Both PCS's speed and rate configuration is done with same
usx registers. ENABLE_HS_MAC bit in NCR is the toggle switch
between the PCS's.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250828045807.426542-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Use plain buffer pointer in request_firmware_into_buf_via_script()
instead of a pointer to pointer. The later is not necessary as the
request_firmware_into_buf_via_script() does not modify the buffer
pointer. Update the mediatek driver to match.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
This bit is necessary to receive packets from the internal PHY.
Without this bit set, no activity occurs on the interface.
Normally u-boot sets this bit, but if u-boot is compiled without
net support, the interface will be up but without any activity.
The vendor SDK sets this bit along with the PHY_ID bits.
Ported from the Linux change at [1] from Da Xu merged in
commit [2].
[1] https://lore.kernel.org/all/20250425192009.1439508-1-da@libre.computer/
[2] b23285e93bef ("net: mdio: mux-meson-gxl: set reversed bit when using internal phy")
Suggested-by: Da Xue <da@libre.computer>
Link: https://lore.kernel.org/r/20250502-u-boot-topic-mdio-mux-gxl-bit28-v1-1-399f6c3db154@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Use regulator_set_enable_if_allowed() to avoid failure if regulator is
shared between multiple devices.
Signed-off-by: Ben Wolsieffer <ben.wolsieffer@hefring.com>
Replace MII with RMII as it is a Reduced Media-Independent Interface.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
The MediaTek MT7987/MT7988 SoCs features a built-in 2.5Gb PHY
connected to GMAC1. The PHY supports 10/100/1000/2500 Mbps
full-duplex only.
The PHY requires one or two firmware files. Firmware for MT7988 has
already been added to upstream: mediatek/mt7988/i2p5ge-phy-pmb.bin.
MT7987 has two firmware files which will be add to upstream later:
i2p5ge-phy-pmb.bin and i2p5ge-phy-DSPBitTb.bin.
Environment variable can be set for firmware data loading:
mt7987_i2p5ge_load_pmb_firmware for i2p5ge-phy-pmb.bin
mt7987_i2p5ge_load_dspbit_firmware for i2p5ge-phy-DSPBitTb.bin
mt7988_i2p5ge_load_pmb_firmware for i2p5ge-phy-pmb.bin
This driver allows dedicated weak functions to be overridden by
board to provide the firmware data:
mt7987_i2p5ge_get_fw() for MT7987
mt7988_i2p5ge_get_fw() for MT7988
To enable the PHY, add the following not to device tree:
ð1 {
status = "okay";
phy-mode = "xgmii";
phy-handle = <&phy15>;
phy15: ethernet-phy@15 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <15>;
phy-mode = "xgmii";
};
};
Signed-off-by: Sky Huang <SkyLake.Huang@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Associate PHY device with its device node specified by phy-handle
property. This makes it possible for PHY drivers to read dedicated
information to configure the PHY device.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Greg Malysa <malysagreg@gmail.com> says:
Between 2025.07 and 2025.10 many header dependency chains were improved,
but this exposed implicit header usage in several of our drivers. This
wasn't discovered before or included in the original fixes because our
drivers are not yet used by any mainline-supported boards, so build
tests did not find them. This series addresses the two build failures
I've encountered while rebasing our work onto 2025.10 and continuing to
prepare the next submission of our board files.
Link: https://lore.kernel.org/r/20250903234205.26787-1-malysagreg@gmail.com
