The init function does nothing, the bb_miiphy_init() already checks
whether the .init callback is assigned, and if not, skips calling it.
Remove the empty init function. The entire init callback will be
removed in follow up patches.
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The init function does nothing, the bb_miiphy_init() already checks
whether the .init callback is assigned, and if not, skips calling it.
Remove the empty init function. The entire init callback will be
removed in follow up patches.
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
When rgmii-rxid/txid/id phy-mode is used the MAC should not add RX
and/or TX delay. Currently RX/TX delay is configured as enabled using
zero as delay value for the rgmii-rxid/txid/id modes.
Change to disable RX and/or TX delay and using zero as delay value.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
When rgmii-rxid/txid/id phy-mode is used the MAC should not add RX
and/or TX delay. Currently RX/TX delay is configured as enabled using
zero as delay value for the rgmii-rxid/txid/id modes.
Change to disable RX and/or TX delay and using zero as delay value.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The PCS exists only in GMAC1 and relates to SGMII interface and
is used to control the SGMII PHY.
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
[trini: Adjust slightly for white space and to move 'start' to within if
block]
Update the debug() print, use __func__ to always print matching
function name, and also print bus name in case there are multiple
busses.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Replace ifdeffery with plain debug() function call. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
This patch fixed the following coding style suggested by checkpatch.pl:
1. Use tab instead of space
2. Use BIT() instead of <<
3. Use mdelay for long time delay
4. Remove useless parenthesises
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
The TI DP83822 does have support for configurable RGMII RX/TX clock
shift, add support for parsing DT properties which describe the RX/TX
clock shift configuration and configuration of the matching bits in
RCSR register.
The shift is only configurable on DP83822, the other PHYs supported
by this PHY driver, namely DP83825/DP83826 variants, do not implement
this functionality and the RCSR bits used to configure the clock shift
are missing from those PHYs.
The shift is configurable separately for RX and TX path. Each path can
either enable the shift or disable the shift using single bit. In case
the shift is disabled, a delay of 0ns is added to the path, otherwise
a delay of 3.5ns is added to the path.
Note that the two RCSR bits 11 and 12 have inverted logic, RCSR bit 12
enables RX internal shift when SET, while RCSR bit 11 enables TX shift
when UNSET.
Signed-off-by: Marek Vasut <marex@denx.de>
These functions can be static as they are referenced only in this file.
Make them static. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
It seems that every remaining system which enables BITBANGMII also
enables BITBANGMII_MULTI . Remove the BITBANGMII_MULTI symbol and
assume it is always enabled. This allows removal of a bit of legacy
code. No functional change intended.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
The ENETCv4 port DT nodes on i.MX95 may contain optional clock phandle
to IMX95_CLK_ENETREF "ref" clock. These "ref" clock must be enabled for
the ethernet to work. These "ref" clock are enabled after cold boot, but
when the system booted Linux and rebooted, those "ref" clock might have
been disabled in the process, which would make ethernet inoperable after
reboot. Make sure those "ref" clock are always correctly enabled.
Signed-off-by: Marek Vasut <marex@denx.de>
1. Bug fixed for doorbell in secure device manager mailbox driver
2. Enhancement on SoCFPGA dwc_eth_xgmac driver
3. Enhancement on DW MAC driver
4. Improved the error message and status for SoC64 device FPGA
configuration driver
5. Updated existing watchdog in system manager to support new SM device
This patch adds support for configuring the ethernet MAC mode independently
from the PHY mode on our SoC FPGA board. Specifically, this is necessary
for a scenario where the ethernet controller MAC is connected to the
FPGA HVIO with a different GMII interface, and the FPGA output is routed
to the PHY using a RGMII interface.
To support this configuration, a mechanism is introduced to handle
separate MAC mode settings, ensuring that the MAC controller and PHY
can operate correctly with their respective interface modes.
If mac-mode is not defined, the MAC mode will default to the PHY mode,
ensuring compatibility and proper operation between the MAC and PHY.
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
Agilex5 having several ethernet instance, adding the device
name at the error message to differentiate between which
instance is having issue.
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
An issue was identified where selecting the phy-mode as
rgmii-id in the device tree source (DTS) would cause the
`dwc_eth_xgmac_socfpga` driver to raise an unsupported phy mode error.
From the MAC controller's perspective, the rgmii and rgmii-id
phy modes are effectively identical. To address this, both
modes will now be configured to rgmii in the MAC controller.
This change ensures that the rgmii-id phy mode is properly
supported without error.
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
This patch adds support for the "rgmii-id", "rgmii-rxid", and
"rgmii-txid" modes for the dwmac_socfpga driver.
Signed-off-by: Rufus Segar <rhs@riseup.net>
Michael Chang <zhang971090220@gmail.com> says:
I am resubmitting the patch titled "Add bitbang feature for npcm8xx
and driver" for review and inclusion in the upstream project.
Driver didn't support bitbang feature.
Add bb_miiphy_bus function for driver and open feature for npcm8xx
the log is as below:
-------------------------------------------------
U-Boot 2024.10-g30b9cdaf2df5-dirty (Jan 09 2025 - 00:57:37 +0000)
CPU-0: NPCM845 A1 @ Model: Nuvoton npcm845 Development Board (Device Tree)
DRAM: 1 GiB
RNG: NPCM RNG module bind OK
OTP: NPCM OTP module bind OK
AES: NPCM AES module bind OK
SHA: NPCM SHA module bind OK
I/TC: Reserved shared memory is enabled
I/TC: Dynamic shared memory is enabled
I/TC: Normal World virtualization support is disabled
I/TC: Asynchronous notifications are disabled
Core: 649 devices, 28 uclasses, devicetree: separate
WDT: Not starting watchdog@901c
MMC: sdhci@f0842000: 0
Loading Environment from SPIFlash... SF:
Detected w25q512jvq with page size 256 Bytes, erase size 64 KiB,
total 64 MiB
OK
In: serial@0
Out: serial@0
Err: serial@0
Net: eth0: eth@f0802000, eth1: eth@f0804000, eth3: eth@f0808000
Hit any key to stop autoboot: 0
U-Boot>
U-Boot>
U-Boot>setenv ipaddr 192.168.16.3
U-Boot>ping 192.168.16.12
eth@f0802000 Waiting for PHY auto negotiation to complete
......... TIMEOUT !
Could not initialize PHY eth@f0802000
eth@f0804000 Waiting for PHY auto negotiation to complete
......... TIMEOUT !
Could not initialize PHY eth@f0804000
Speed: 100, full duplex
Using eth@f0808000 device
host 192.168.16.12 is alive
Link: https://lore.kernel.org/r/20250117104540.1580343-1-zhang971090220@gmail.com
Add bb_miiphy_bus function for designware bitbang feature.
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Signed-off-by: Michael Chang <zhang971090220@gmail.com>
This patch adds support for MediaTek MT7987.
MT7987 features MediaTek NETSYS v3, similar to MT7988, features three GMACs
which support 2.5Gb HSGMII. One 2.5Gb PHY is also embedded an can be
connected to a dedicated GMAC.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
mtk_eth.c contains not only the ethernet GMAC/DMA driver, but also
some ethernet switch initialization code. As we may add more switch
support in the future, it's better to move them out of mtk_eth.c to
avoid increasing the code complexity.
Since not all switches are supported for a particular board, Kconfig
options are added to allow user to select which switch should be
built into u-boot. If multiple switches are selected, auto-detecting
can also be enabled.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
i.MX95 uses enetc version 4.1 controller. Update the enetc for i.MX95.
Add ARM-specific cache handling and i.MX95 specific register layout
handling.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de> # Clean up
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
The verdor ID and device ID of i.MX95 EMDIO are different from LS1028A
EMDIO, so add new vendor ID and device ID to pci_device_id table to
support i.MX95 EMDIO.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de> # Clean up
Signed-off-by: Ye Li <ye.li@nxp.com>
The netc-blk-ctrl driver is used to configure Integrated Endpoint
Register Block (IERB) and Privileged Register Block (PRB) of NETC.
For i.MX platforms, it is also used to configure the NETCMIX block.
The IERB contains registers that are used for pre-boot initialization,
debug, and non-customer configuration. The PRB controls global reset
and global error handling for NETC. The NETCMIX block is mainly used
to set MII protocol and PCS protocol of the links, it also contains
settings for some other functions.
Note the IERB configuration registers can only be written after being
unlocked by PRB, otherwise, all write operations are inhibited. A warm
reset is performed when the IERB is unlocked, and it results in an FLR
to all NETC devices. Therefore, all NETC device drivers must be probed
or initialized after the warm reset is finished.
Ported from Linux 6.13-rc as of commit
fe5ba6bf91b3 ("net: enetc: add initial netc-blk-ctrl driver support")
Signed-off-by: Marek Vasut <marex@denx.de>
Pass struct udevice * into the register accessors, so the accessors can reach
driver data, which contain device specific register offsets.
Signed-off-by: Marek Vasut <marex@denx.de>
Introduce driver data for each PCI device. The driver data carry
offsets of registers which differ between different SoCs.
Signed-off-by: Marek Vasut <marex@denx.de>
Split register accessors to the port base/station interface/port/mac
registers as those are at different offsets on different SoCs. This
is a preparatory patch which will allow addition of adjusted offsets
for new SoCs easily.
Signed-off-by: Marek Vasut <marex@denx.de>
Move register accessors from header files and turn them into proper
inline functions, so typechecking can be done on them. Drop no longer
enetc_port_regs() and unused enetc_read() and enetc_bdr_read().
Signed-off-by: Marek Vasut <marex@denx.de>
Introduce mapping function enetc_dev_id(), which converts PCIe BDF of
the ENETC into linear incrementing index usable e.g. as interface index.
This replaces the current ad-hoc calculation used in the code with a
dedicated function. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Rename the current driver structure and matching ops and PCI IDs
and add _ls suffix to indicate this content is LS specific. This
is done in preparation for addition of i.MX95 ENETCv4 which will
require slightly different structure content.
Signed-off-by: Marek Vasut <marex@denx.de>
Pass udevice pointer into enetc_enable_si_port() so tests like
enetc_is_ls1028a() an be used in the function. No functional
change.
Signed-off-by: Marek Vasut <marex@denx.de>
The entire content of the loop can be folded into enetc_set_ierb_primary_mac(),
do it. This changes the behavior slightly such that the DT is only updated in
case of a LS1028A, which is the only SoC with ethernet MAC path in DT matching
"/soc/pcie@1f0000000/ethernet@%x,%x" anyway, so this slight change should have
no impact.
Signed-off-by: Marek Vasut <marex@denx.de>
Use enetc_is_ls1028() instead of ifdef around enetc_set_ierb_primary_mac()
and clean up the function. No functional change intended.
Signed-off-by: Marek Vasut <marex@denx.de>
Introduce accurate test for LS1028A compatibility based both on
IS_ENABLED(CONFIG_ARCH_LS1028A) and PCI vendor ID. This is done
in preparation for adding ENETCv4 support, which has a different
PCI vendor ID.
Signed-off-by: Marek Vasut <marex@denx.de>
Linux DTS compatible MDIO bitbanging driver.
Both clause 22 and clause 45 MDIO supported and validated.
Heavily based on the Linux drivers (more or less the same code base).
Signed-off-by: Markus Gothe <markus.gothe@genexis.eu>
This reverts commit 431be621c6.
Section 3.3 of Reduced Gigabit Media Independent Interface (RGMII)
Version 2.0 (4/1/2002) details that a PHYs using a ~2ns internal delay
are referred to as RGMII-ID. This internal delay is optional.
Page 147-148 of the Marvell Doc. No. MV-S107146-U0 Rev. F details
timings of the RX/TX delays. We see that with the TX/RX_CLK delay
enabled, our RX/TX_CTL signal is shifted w.r.t CLK to reflect the delay
added.
In 431be62 there is no timing difference between RGMII and RGMII-ID, and
so programmers wanting to explicitly set their PHY to RGMII will find
that delay added anyway. This could throw off timing if that internal
delay is undesired.
We should be handling all 4 possible RGMII cases of PHY_INTERFACE_MODE:
RGMII, RGMII_ID, RGMII_TXID, and RGMII_RXID. Reverting 431be62
implements this.
See also m88e1111_config_init_rgmii_delays in the equivalent driver in
Linux (drivers/net/phy/marvell.c), which does not set these delays in
RGMII mode.
68e6eca was tested out on an 88E1512 PHY in RGMII-ID mode. This
reversion has been tested by myself on an 88E1518 in RGMII-ID mode. This
patch affects boards using this driver in "rgmii" mode, as the internal
delay will no longer be enabled. Namely kikwood-nsa310s.
Signed-off-by: Rufus Segar <rhs@riseup.net>
The wget command currently cannot work correctly with mtk_eth driver.
This patch fixed this by increase DMA ring size and invalidate ring data
after use.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Enable GDMA cpu bridge only when 10Gb interface is enabled for GMAC other
than GMAC0, or when MT7988 internal switch is used.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Not all platforms supports sgmii and/or usxgmii. So we add Kconfig
options for these features and enable them only for supported
platforms.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
MT7629 need extra setting for gmac2 to work. So additional
capability is added for mt7629 to handle this case.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Unlike other platforms, mt7622 has only one SGMII and it can be
attached to either gmac1 or gmac2. So the register field of the
sgmii selection differs from other platforms as newer platforms can
control each sgmii individually.
This patch adds a new capability for mt7622 to handle this case.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
The register field for SGMII speed selection is a 2-bit field with
value 0 for 1Gbps and 1 for 2.5Gbps (2/3 are reserved).
So it's necessary to set both bits instead of just setting/clearing
only the lower bit.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Add support for mapping C22 register access to C45-only PHYs.
This is mainly useful for 'mii info' command, which performs
C22 only access to determine PHY ID and link state and does
not work well with this driver so far.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Implement C22 PHY access support in addition to C45 PHY access
support which is already present. This is used for PHYs which
do not support C45 access or which are C22 only.
The C22 access can be recognized when devad is set to -1 or
0xffffffff hex, which also matches MDIO_DEVAD_NONE macro. Test
for this special devad value and if it is set this way, perform
C22 access, otherwise perform C45 access.
Based on work by LUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The Set Station Management Mode : Clause 45 setting of MFF bit in MPSM
register can be done in rswitch_mii_access_c45() once, instead of this
being done before each rswitch_mii_access_c45() call. Deduplicate the
bit setting into rswitch_mii_access_c45(). No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Replace enum rswitch_reg with plain #define REGISTER OFFSET macros.
The enum rswitch_reg was not referenced anywhere, so there was no
benefit of keeping it around. Include register block labels. Turn
all register offsets into lowercase hex values. No functional change.
Rename EATDQDC to EATDQDCR, GWTRC to GWTRCR, GWDCC to GWDCCR, FWPC0
to FWPC, FWPBFC to FWPBFCR, FWPBFCSDC to FWPBFCSDCR because there
are both register names which used to be part of this enum and also
macros with the same name, each used for slightly different purpose.
Make sure there is no collission.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
When FEC network card works as the prime one in u-boot, and is in
active status, kernel might crash during booting up stage, especially
working with grub. Because the DMA of FEC is still in active status, and
copy data into memory if there is network data received. In this case, if
kernel allocated a part of memory that has overlay with the memory
used by DMA, kernel memory may be destroyed and cause kernel crashes.
Because before kernel boots up really, u-boot dm_remove_devices_flags()
can call the remove callback of FEC driver with DM_FLAG_ACTIVE_DMA
flag. In fecmxc_remove(), phy power is disabled, so there is no data
received. In this way, it makes sure that there is no DMA action, so
that avoid kernel crashing occurs.
Signed-off-by: Meng Li <Meng.Li@windriver.com>
In case an rswitch port is described as disabled in DT, do not
register it as ethernet device in U-Boot. This way, such ports
cannot be accessed from U-Boot command line.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
TFTP transfers of large files, for example 128 MiB, can sporadically
get stuck and the transfer slows down considerably.
This happens because the TX DMA descriptor in DRAM becomes out of sync
with the view of the TX DMA descriptor content from the CPU side, which
is viewed through the CPU caches. In order to guarantee these two views
are consistent, the cache over TX DMA descriptor that has possibly been
written by the rswitch hardware must first be invalidated, only then can
the descriptor be cleared and updated by the CPU, and finally the cache
over that area must be flushed back into DRAM to make sure the rswitch
hardware has consistent view of the updated descriptor content.
The very first invalidation operation was missing, which led to sporadic
corruption of the TX DMA descriptor. Fix it, add the missing invalidation
operation.
Reported-by: Enric Balletbo i Serra <eballetb@redhat.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Tested-by: Enric Balletbo i Serra <eballetb@redhat.com>
Currently if a gigabit-capable PHY is connected to FEC via RMII or MII, it
will advertise 1000FULL and 1000HALF to a link partner.
Different problems may arise here:
- usually with (R)MII between MAC and PHY the PHY's connection to magnetics
would have only 2 pairs routed as well, otherwise a PHY can negotiate 1000
speed and there will be no traffic possible;
- but even if there is no way to negotiate 1000 speed in HW (only 2 signal
pairs routed), it may take a lot of time for PHY to figure this out; in
case of AD1300 it takes 17-20 seconds, which is waay longer than default
4s PHY_ANEG_TIMEOUT.
Use phy_set_supported() in such cases to disable gigabit advertised
options.
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
We can call dev_read_u32_default() instead of calling fdt_getprop() then
fdt32_to_cpu().
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
probing on capricorn board (imx8qxp based) brings:
Can't find FEC0 clk rate: -19
Cause is that when probing fec_mxc driver, fec_mii_setspeed()
is called which calls fec_get_clk_rate().
fec_mii_setspeed() calls fec_get_clk_rate with NULL pointer
for udev and so as in IMX8QXP case CLK_CCF is enabled
udev gets searched with:
uclass_get_device_by_seq(UCLASS_ETH, idx, &dev);
but we do not have yet a UCLASS_ETH ! as we just probing it!
Prevent this by passing udev to fec_get_clk_rate()
Signed-off-by: Heiko Schocher <hs@denx.de>
They were added with commit 0e9d23945c ("net: eqos: implement callbaks
to get interface and set txclk rate") but were not removed with
commit 5fc783b5d9 ("net: dwc_eth_qos: move i.MX code out") when i.MX
specific code was moved to a separate file.
Signed-off-by: Erik Schumacher <erik.schumacher@iris-sensing.com>
The EQOS on i.MX93 fails to finish the reset procedure in RMII mode.
This is described in errata ERR051683. This patch implements the
provided workaround which sets the PS and FES bits after the SWR is set
by using the eqos_fix_soc_reset function.
Adapted from linux-kernel commit b536f32b5b03 ("net: stmmac: dwmac-imx:
use platform specific reset for imx93 SoCs")
Signed-off-by: Erik Schumacher <erik.schumacher@iris-sensing.com>
This patch adds support for optional platform specific reset logic in
the dwc_eth_qos driver. This new function 'eqos_fix_soc_reset' is called
after the EQOS_DMA_MODE_SWR is set and before the driver waits for this
bit to clear.
Signed-off-by: Erik Schumacher <erik.schumacher@iris-sensing.com>
Romain Naour <romain.naour@smile.fr> says:
We are using a custom board where an ethernet switch device KSZ9896 is
available. This family of devices can use several types of serial bus
as management interface: mdio, i2c or SPI. Due to board design
constraints and because we initially planned to use this device only
from Linux, the SPI bus was used.
Luckily we are using a recent enough u-boot release where KSZ9477
driver is available... but only for the i2c interface. Indeed, unlike
the kernel driver, the KSZ9477 driver doesn't use the regmap API to
access the underlying bus since the regmap API is limited to direct
memory access [1].
Until regmap API with bus support is available in U-boot, we introduced
struct ksz_phy_ops to store low-level ksz bus operations (I2C or SPI).
This series has been tested on the current master branch (after v2024.10
release).
[1] https://source.denx.de/u-boot/u-boot/-/blob/v2024.10-rc5/drivers/core/Kconfig?ref_type=tags#L188
Link: https://lore.kernel.org/r/20241008075435.1572727-1-romain.naour@smile.fr
Some drivers do not behave properly when free_pkt() is called with a
length of zero. It is an issue I observed when developing the lwIP
series [1] (see "QEMU CI tests for r2dplus_i82557c, r2dplus_rtl8139"
in the change log) and which I fixed incorrectly by not calling
free_pkt() when recv() returns 0. That turned out to be wrong for two
reasons:
1. The DM documentation [2] clearly requires it:
"The **recv** function polls for availability of a new packet. [...]
If there is an error [...], return 0 if you require the packet to
be cleaned up normally, or a negative error code otherwise (cleanup
not necessary or already done).
If **free_pkt** is defined, U-Boot will call it after a received
packet has been processed [...]. free_pkt() will be called after
recv(), for the same packet [...]"
2. The imx8mp_evk platform will fail with OOM errors if free_pkt() is
not called after recv() returns 0:
u-boot=> tftp 192.168.0.16:50M
Using ethernet@30be0000 device
TFTP from server 192.168.0.16; our IP address is 192.168.0.48
Filename '50M'.
Load address: 0x40480000
Loading: #######################fecmxc_recv: error allocating packetp
fecmxc_recv: error allocating packetp
fecmxc_recv: error allocating packetp
...
Therefore, make recv() return -EAGAIN instead of 0 when no packet is
available and the driver doesn't expect free_pkt() to be called
subsequently.
[1] https://lists.denx.de/pipermail/u-boot/2024-August/562861.html
[2] doc/develop/driver-model/ethernet.rst
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The Microchip KSZ Gigabit Ethernet Switches support
SGMII/RGMII/MII/RMII with register access via SPI, I2C, or MDIO.
Since this driver is now able to check the underlying bus type,
handle the case when the SPI bus is used.
The SPI bus is only used for 8/16/32 wide access of registers.
Reword Kconfig option to include SPI bus support.
Signed-off-by: Romain Naour <romain.naour@smile.fr>
With the upcoming ksz9477 SPI support added, the I2C support
will be optional. Either the I2C or the SPI bus will be used.
For now, DM_I2C is still mandatory.
Signed-off-by: Romain Naour <romain.naour@smile.fr>
In order to support management bus other than the I2C, rename
ksz_i2c_probe() to ksz_probe() since this function is no longer
specific to the I2C bus.
Signed-off-by: Romain Naour <romain.naour@smile.fr>
The ksz9477 Linux kernel driver is based on regmap API to seamlessly
communicate to switch devices connected via different buses like SPI
or I2C. The current regmap implementation in U-Boot only supports
memory-mapped registers access [1].
Until regmap API with bus support is available in U-boot, introduce
struct ksz_phy_ops to store low-level ksz bus operations (I2C for now).
[1] https://lists.denx.de/pipermail/u-boot/2018-May/329392.html
Signed-off-by: Romain Naour <romain.naour@smile.fr>
In order to add ksz9477 SPI bus support, check parent bus
is an I2C bus before calling i2c_set_offset_len().
Doing so, ksz_i2c_probe() will now return an error (-EINVAL) if
the parent bus is not the one expected by the ksz-switch u-boot
driver.
Indeed, the DSA KSZ devicetree binding doesn't specify anything
about the underlying bus between the SoC and the DSA switch, so
the same "compatible" string can be used wathever the management
interface used (SPI or I2C).
The ksz-switch u-boot driver currently only support I2C interface
but will match a compatible "microchip,ksz9xxx" located under
under an SPI bus node.
Signed-off-by: Romain Naour <romain.naour@smile.fr>
The DSA KSZ devicetree binding doesn't specify anything about the
underlying bus between the SoC and the DSA switch, so the same
"compatible" string can be used wathever the management interface
used. The driver must be able to access the underlying bus without
any help from the compatible string (like for TPM2 TIS devices).
So, rename udevice_id tab to ksz_ids since it's not specific to i2c
bus.
Signed-off-by: Romain Naour <romain.naour@smile.fr>
Add support for the KSZ9896 6-port Gigabit Ethernet Switch to the
ksz9477 driver.
The KSZ9896 is similar to KSZ9897 but has only one configurable
MII/RMII/RGMII/GMII cpu port.
Signed-off-by: Romain Naour <romain.naour@smile.fr>
The ksz9477 is currently the only driver using dev_set_parent_priv()
outside of the driver model. Also, there was no explanation in the
commit adding ksz9477 driver and why dev_set_parent_priv() is
required.
Actually there is a typo in ksz_mdio_probe() while retrieving
the parent (switch@0) private data:
- priv->ksz = dev_get_parent_priv(dev->parent);
+ priv->ksz = dev_get_priv(dev->parent);
Printing the address of struct ksz_dsa_priv *priv allows
to notice the slight difference:
ksz_i2c_probe: ksz_dsa_priv *priv 0xfdf45768 // address of the saved priv
ksz_mdio_bind: ksz_dsa_priv *priv 0xfdf45798 // address returned by dev_get_parent_priv(dev->parent)
ksz_mdio_bind: ksz_dsa_priv *priv 0xfdf45768 // address returned by dev_get_priv(dev->parent)
The ksz_mdio driver get the wrong data and without
dev_set_parent_priv() the mdio driver fail to access the underlying
bus.
While it doesn't cause any issue with I2C bus, it override the
per-child data used by the SPI bus (struct spi_slave) and prevent
further bus access (even with sspi command).
Signed-off-by: Romain Naour <romain.naour@smile.fr>
Add a driver for the motorcomm YT8821 2.5G ethernet phy which works in
2500base-x mode.
Verify the driver on BPI-R3(with MediaTek MT7986(Filogic 830) SoC) evb.
Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com>
Remove the OMR_PM flag and choose 16 perfect filtering mode since in
modern networks there're plenty of multicasts and set ORM_PM flag will
increase the dc2114x's workload and ask the U-Boot to handle packets
not related to itself. And most of the time, U-Boot does not need this
feature.
Signed-off-by: Hanyuan Zhao <zhaohy22@mails.tsinghua.edu.cn>
Some IP cores of dc2114x or its variants do not comply so well with
the behaviors described by the official document. Originally this
driver uses only one tx descriptor and organizes it as a ring buffer,
which would lead to a problem that one packet would be sent twice.
This commit adds support to prevent this bug if you are using IP
cores with this issue, by using multiple tx descriptors and
organizing them as a real well-defined ring buffer.
Signed-off-by: Hanyuan Zhao <zhaohy22@mails.tsinghua.edu.cn>
Some IP cores of dc2114x or its variants do not comply so well with
the behaviors described by the official document. A packet could be
sent successfully but reported with No Carrier error. Latest drivers
of this IP core have not detect this error anymore.
Signed-off-by: Hanyuan Zhao <zhaohy22@mails.tsinghua.edu.cn>
This commit fixes a problem that even though the network card does not report
any issues in transmitting a setup frame, the driver prints the error status
every time. Let's set it for debug use.
Signed-off-by: Hanyuan Zhao <zhaohy22@mails.tsinghua.edu.cn>
This commit adds support for the MIPS and LoongArch CPUs, which would use cache
after they jump into U-Boot. This commit requests the CPU to return the
addresses in uncached windows and flushes the cache in need, to make sure the
memory between the CPU and the network card is in consistency.
Signed-off-by: Hanyuan Zhao <zhaohy22@mails.tsinghua.edu.cn>
Let this old driver work like the other newer network card drivers, loading the
MAC address from environment, which could be more flexible to set.
Signed-off-by: Hanyuan Zhao <zhaohy22@mails.tsinghua.edu.cn>
There're a few ethernet IP cores which have the same functions with dc2114x,
and can be connected to CPU by AXI or other buses. This commit adds support
for the platforms that do not have PCI controllers, using MMIO to communicate
with the dc2114x IP core.
Signed-off-by: Hanyuan Zhao <zhaohy22@mails.tsinghua.edu.cn>
Add what it takes to enable NETDEVICES with NET_LWIP and enable DHCP as
well as the dhcp command. CMD_TFTPBOOT is selected by BOOTMETH_EFI due
to this code having an implicit dependency on do_tftpb().
Note that PXE is likely non-fonctional with NET_LWIP (or at least not
100% functional) because DHCP option 209 is not supported by the lwIP
library. Therefore, BOOTP_PXE_DHCP_OPTION cannot be enabled.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Prepare the introduction of the lwIP (lightweight IP) TCP/IP stack by
adding a new net/lwip/ directory and the NET_LWIP symbol. Network
support is either NO_NET, NET (legacy stack) or NET_LWIP. Subsequent
commits will introduce the lwIP code, re-work the NETDEVICE integration
and port some of the NET commands and features to lwIP.
SPL_NET cannot be enabled when NET_LWIP=y. SPL_NET pulls some symbols
that are part of NET (such as arp_init(), arp_timeout_check(),
arp_receive(), net_arp_wait_packet_ip()). lwIP support in SPL may be
added later.
Similarly, DFU_TFTP and FASTBOOT are not compatible with NET_LWIP
because of dependencies on net_loop(), tftp_timeout_ms,
tftp_timeout_count_max and other NET things. Let's add a dependency on
!NET_LWIP for now.
SANDBOX can select NET_LWIP but doing so will currently disable the eth
dm tests as well as the wget tests which have strong dependencies on the
NET code.
Other adjustments to Kconfig files are made to fix "unmet direct
dependencies detected" for USB_FUNCTION_SDP and CMD_FASTBOOT when
the default networking stack is set to NET_LWIP ("default NET_LWIP"
instead of "default NET" in Kconfig).
The networking stack is now a choice between NO_NET,
NET and NET_LWIP. Therefore '# CONFIG_NET is not set' should be
'CONFIG_NO_NET=y'. Adjust the defconfigs accordingly.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Introduce ETH_SANDBOX_LWIP which enables a mock driver similar to
ETH_SANDOX but without the dependencies on the legacy network stack
(NET) so that it may be enabled when the lwIP stack (NET_LWIP) is
introduced. The driver does nothing at this stage but its presence
will allow dm_test_iommu_noiommu [1] to pass.
[1] ./u-boot -T -c "ut dm dm_test_iommu_noiommu"
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Simon Glass <sjg@chromium.org> says:
When the SPL build-phase was first created it was designed to solve a
particular problem (the need to init SDRAM so that U-Boot proper could
be loaded). It has since expanded to become an important part of U-Boot,
with three phases now present: TPL, VPL and SPL
Due to this history, the term 'SPL' is used to mean both a particular
phase (the one before U-Boot proper) and all the non-proper phases.
This has become confusing.
For a similar reason CONFIG_SPL_BUILD is set to 'y' for all 'SPL'
phases, not just SPL. So code which can only be compiled for actual SPL,
for example, must use something like this:
#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
In Makefiles we have similar issues. SPL_ has been used as a variable
which expands to either SPL_ or nothing, to chose between options like
CONFIG_BLK and CONFIG_SPL_BLK. When TPL appeared, a new SPL_TPL variable
was created which expanded to 'SPL_', 'TPL_' or nothing. Later it was
updated to support 'VPL_' as well.
This series starts a change in terminology and usage to resolve the
above issues:
- The word 'xPL' is used instead of 'SPL' to mean a non-proper build
- A new CONFIG_XPL_BUILD define indicates that the current build is an
'xPL' build
- The existing CONFIG_SPL_BUILD is changed to mean SPL; it is not now
defined for TPL and VPL phases
- The existing SPL_ Makefile variable is renamed to SPL_
- The existing SPL_TPL Makefile variable is renamed to PHASE_
It should be noted that xpl_phase() can generally be used instead of
the above CONFIGs without a code-space or run-time penalty.
This series does not attempt to convert all of U-Boot to use this new
terminology but it makes a start. In particular, renaming spl.h and
common/spl seems like a bridge too far at this point.
The series is fully bisectable. It has also been checked to ensure there
are no code-size changes on any commit.
SPL_BUILD is not a Kconfig symbol. Perhaps the intent here is to use
SPL instead. However, this causes build errors, e.g. with T1024RDB_NAND
So drop the dependency on !SPL_BUILD since it does nothing.
Signed-off-by: Simon Glass <sjg@chromium.org>
After FEC is halted by calling fec_halt callback, we should not continue
receiving packet. Otherwise it will process previous pending interrupts
on EIR register and uses wrong rbd index as this has been reset to 0.
The GRA interrupt which is triggered by issuing graceful stop command to
FEC transmitter in fec_halt is processed in this case. It causes wrong
receive buffer descriptors be used by FEC in next time.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
i.MX93 FEC ENET port supports two mode: RGMII and RMII. For RGMII,
there is an internal /2 divider, so the freq needs to set with (*2),
otherwise the speed will not reach 1G and cause communication error
in some network environments. For RMII, the clk path is
ccm -> enet tx_clk pin -> pad loop back to enet, no /2 divider.
So fix for RGMII mode with freq multiplied by 2.
Fixes: 09de565f76 ("net: fec_mxc: support i.MX93")
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
