When running the bootstage tests currently we get a warning like:
tests/test_bootstage.py::test_bootstage_stash
...PytestReturnNotNoneWarning: Expected None, but tests/test_bootstage.py::test_bootstage_stash returned (37748736, 4096), which will be an error in a future version of pytest. Did you mean to use `assert` in stead of `return`?
This is because the unstash test will run the stash test and fetch the
addr / size from that. Rework the test to be stash and unstash and then
run the unstash command at the end of the current stash test.
Acked-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Love Kumar <love.kumar@amd.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Make SPL_RAM_SUPPORT a hidden Kconfig symbol, automatically selected
by SPL_RAM_DEVICE or SPL_DFU. Avoids the situation where SPL_RAM_SUPPORT
may be enabled without the other two being enabled, which results in the
following build warning:
common/spl/spl_ram.c:19:14: warning: ‘spl_ram_load_read’ defined but not used [-Wunused-function]
19 | static ulong spl_ram_load_read(struct spl_load_info *load, ulong sector,
| ^~~~~~~~~~~~~~~~~
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
In case the cyclic framework is enabled, poll the card detect of already
initialized cards and deinitialize them in case they are removed. Since
the card initialization is a longer process and card initialization is
done on first access to an uninitialized card anyway, avoid initializing
newly detected uninitialized cards in the cyclic callback.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added LMB API to prevent SF command from overwriting reserved
memory areas. The current SPI code does not use LMB APIs for
loading data into memory addresses. To resolve this, LMB APIs
were added to check the load address of an SF command and ensure it
does not overwrite reserved memory addresses. Similar checks are
used in TFTP, serial load, and boot code to prevent overwriting
reserved memory.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Suggested-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Use the lmb_read_check() function to verify if it is safe to use a
region of memory to load data from the wget command. The current logic
checks the amount of free memory available, starting from the 'load
address'. This call fails if the same region of memory has been used
earlier. This used to work earlier as the LMB memory map had a local
scope and was not persistent. Fix this issue by using the
lmb_read_check() call instead which only returns an error in case the
memory region has been marked for not allowing re-use.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Tested-by: Vaishnav Achath <vaishnav.a@ti.com>
Use the lmb_read_check() function to verify if it is safe to use a
region of memory to load data from a tftp command. The current logic
checks the amount of free memory available, starting from the 'load
address'. This call fails if the same region of memory has been used
earlier. This used to work earlier as the LMB memory map had a local
scope and was not persistent. Fix this issue by using the
lmb_read_check() call instead which only returns an error in case the
memory region has been marked for not allowing re-use.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Tested-by: Vaishnav Achath <vaishnav.a@ti.com>
Popup the bootmenu for 5 sec with default boot options to CC on AMD CCs and
default to SOM on others.
Users can anytime disable the bootmenu by setting the variable
enable_bootmenu=0 in zynqmp_kria.env or setup it up at run time and save
variables to NV memory.
The patch is also fixing issue created by commit 4c7363068651 ("cmd:
setexpr: fix no matching string in gsub return empty value") which has
changed return value from setexpr command (Before this commit when
matching string wasn't found command return 1 that's why was possible to
use with if).
Signed-off-by: John Vicky Vykuntapu <johnvicky.vykuntapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6193d95a9c0f3ae319a900b46d6212f7ab16aba4.1726041851.git.michal.simek@amd.com
fixed-clock can't be described on the bus because it is missing reg
property. Also remove additional compatible string for flash. Mini qspi
configuration is used with multiple different flashes that's why describing
only one is not correct but also not required based on DT schema.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/0e4721eda8d0f23a9d9f0c15cf887f0bba639cd4.1726219714.git.michal.simek@amd.com
amba is not approved node name for simple-bus that's why use axi instead to
be aligned with other xilinx boards. Node reference is not changed that's
why there is no impact but also mini configuration will never gets to OS
that's why nothing should be affected from OS perspective (paths in /proc/
for example).
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1b18a69ae47bdcb1a0795af7621d13bfecfc9861.1726219714.git.michal.simek@amd.com
Generic understanding/consideration is that phy-mode as sgmi means that the
internal PCS(Physical Coding Sublayer) should be enabled by default.
Xilinx GEM implementation allows configuration GEM (gmii mode) + PL PCS PMA
(sgmii mode, Physical Medum Attachment) but in this case phy-mode should be
setup as gmii.
The reason for this assumption is that phy-mode should be described based
on GEM configuration not based on mode coming out of PHY.
Also Linux kernel automatically setting up PCSSEL bit when phy mode is
sgmii without a need to specified additional DT propety.
All our DTSes with sgmii phy mode have this flag enabled that's why there
is no need/reason to just duplicate information.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2ecdbcc4ce692e2f8b3e7054a2abab35f6c03a69.1726213052.git.michal.simek@amd.com
U-Boot is not picking boot.scr script address from device tree
rather it's using default address for Microblaze platform,
and it's picking for other platforms. Remove conditional check
for Microblaze platform, so that u-boot pick up boot.scr script
address for all platforms from device tree.
Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Link: https://lore.kernel.org/r/20240913093231.2343528-1-padmarao.begari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
There are lot of device_is_compatible() present in the driver.
Remove them and replace with a variables "SDHCI_COMPATIBLE_SDHCI_89A"
and "SDHCI_COMPATIBLE_VERSAL_NET_EMMC" with match data.
This change saves the space and reduce the execution time.
Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Link: https://lore.kernel.org/r/20240913093157.2343476-1-padmarao.begari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Remove device tree overlay (DTBO) entries for the ZynqMP target
from the Makefile. Add new device tree binaries (DTBs) for the
zynqmp-sm-k24-revA and zynqmp-smk-k24-revA configurations.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20240906070808.1045991-3-prasad.kummari@amd.com
Linux commits:
15d16d6dadf6 kbuild: Add generic rule to apply fdtoverlay
44f87191d105 kbuild: parameterize the .o part of suffix-search
The Linux commit 15d16d6dadf6 adds a generic rule in Makefile.lib
to automatically apply fdtoverlay, so that each platform doesn't
need to include a complex rule. This also automatically appends
DTC_FLAGS_foo_base += -@ to all base files
The platform's Makefile only needs to have this now:
foo-dtbs := foo_base.dtb foo_overlay1.dtbo foo_overlay2.dtbo
dtb-y := foo.dtb
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20240906070808.1045991-2-prasad.kummari@amd.com
Set NIDEN, enabling non-invasive debug for the CCI-400 PMU. Otherwise,
the PMU is effectively disabled.
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20240905171833.325548-3-sean.anderson@linux.dev
Signed-off-by: Michal Simek <michal.simek@amd.com>
To boot into the firmware recovery tool, the user currently
needs to press a button on the board while powering the
system up. To simplify this process, a U-Boot command
was added to allow booting directly into the recovery tool.
For example:
ZynqMP> zynqmp reboot <multiboot offset in hex>
Co-develop-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Co-develop-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20240827115529.2931334-1-prasad.kummari@amd.com
Included the SPI header to resolve the no previous prototypes
for function. Removed unused mode variable.
sparse warnings
warning: no previous prototype for 'spi_get_env_dev'
[-Wmissing-prototypes]
warning: variable 'mode' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Link: https://lore.kernel.org/r/20240905115758.999936-1-prasad.kummari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
This patch fixes timeout issues seen on large NOR flash.
For full-chip erase, where we use the SPINOR_OP_CHIP_ERASE (0xc7)
opcode. Use a different timeout for full-chip erase than for other
commands.
[Ported from Linux kernel commit
09b6a377687b ("mtd: spi-nor: scale up timeout for
full-chip erase") ]
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/22363
- Several updates to i.MX9 SOC and i.MX93 EVK.
- Power domain fixes.
- TRDC cleanup and update.
- MAC address layout update.
- Add support for the i.MX9301/9302 variants.
- Add runtime detection of voltage mode.
- Generalize some code for i.MX8M and i.MX9.
- Add support for Comvetia imx6q-lxr board.
- Read both copies of metadata, in case one of the is corrupted
- Check the metadata version against the running firmware to make sure it's
allowed
- Limit the use of a revert capsule if the board is on a trial state and
make sure it's not applied if the max counter has expired
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Merge tag 'fwu-next-19092024' of https://source.denx.de/u-boot/custodians/u-boot-tpm into next
This PR contains various improvements in the A/B update logic for EFI
- Read both copies of metadata, in case one of the is corrupted
- Check the metadata version against the running firmware to make sure it's
allowed
- Limit the use of a revert capsule if the board is on a trial state and
make sure it's not applied if the max counter has expired
When dealing with processing of the empty capsule, the capsule gets
applied only when the checks for the empty capsule pass. Print a
message to highlight if empty capsule checks fail, and return an error
value, similar to the normal capsules.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Tested-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
When in Trial State, the platform keeps a count of the number of times
it has booted in the Trial State. Once the threshold of the maximum
allowed count exceeds, the platform reverts to boot from a different
bank on subsequent boot, thus coming out of the Trial State. It is
expected that all the updated images would be accepted or rejected
while the platform is in Trial State. Put in checks so that it is not
possible to apply an empty capsule once the max Trial Count exceeds.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Tested-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
The FWU code supports both versions of the FWU metadata, i.e. v1 and
v2. A platform can then select one of the two versions through a
config symbol. Put a dependency in the FWU metadata version selection
config symbol to ensure that both versions of the metadata cannot be
enabled.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
The platform transitions out of Trial State into the Regular State
only when all the images in the update bank have been accepted. Check
for this condition before transitioning out of Trial State.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Tested-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Do a sanity check that the version of the FWU metadata that has been
read aligns with the version enabled in the image. This allows to
indicate an early failure as part of the FWU module initialisation.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Tested-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
In the version 2 of the FWU metadata, the metadata is broken into two
parts, a top-level structure, which provides information on the total
size of the structure among other things. Try reading the primary
partition first, and if that fails, try reading the secondary
partition. This will help in the scenario where the primary metadata
partition has been corrupted, but the secondary partition is intact.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Tested-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Add support for the Comvetia i.MX6Q LXR2 board, which is
uses the Phytec PFLA02 SoM.
Based on the original work from Stefano Babic <sbabic@denx.de>.
The Phytec PFLA02 devicetrees are taken from kernel 6.11-rc7.
The imx6q-lxr.dts has been submitted upstream:
https://lore.kernel.org/linux-devicetree/20240913200906.1753458-3-festevam@gmail.com/
After it gets accepted in mainline (most likely in kernel 6.13),
the lxr2 board can then be switched to OF_UPSTREAM and these device trees
can be removed from U-Boot.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Add back low drive mode 1866mts ddr timing file, no need
CONFIG_IMX9_LOW_DRIVE_MODE anymore, using runtime selection.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Remove unused CONFIG_IMX9_LOW_DRIVE_MODE kconfig and
imx93_11x11_evk_ld_defconfig.
Remove the ld timing file.
The LD mode support will be added back with runtime detection later.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
1. Use runtime voltage selection for LD/OD/ND mode.
2. According to latest PE/TE report, the voltages of VDD_SOC for
LD and ND mode need add 50mv margin, so LD voltage is 0.75v->0.8v,
ND voltage is 0.8v->0.85v.
3. Use TOFF_DEB to differentiate new trimmed pmic and old pmic
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add trdc_mbc_blk_num to get num blks in a MBC mem slot, then drop
the hardcoded value '40' for NIC OCRAM configuration.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
i.MX8M and i.MX9 have duplicated fixup_thermal_trips, so move it
to arch/arm/mach-imx/fdt.c to avoid duplicated code.
The critial temperature point for i.MX9 set to "maxc - 5" back to give
some margin.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add support for iMX93 low performance parts 9302 and 9301 which
restrict to low drive voltage only.
The parts run A55 max speed at 900Mhz and M33 at 133Mhz, have NPU
and A55 core1 (9301) disabled.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
disable_cpu_nodes could be reused by i.MX9, so move disable_cpu_nodes
out from mach-imx/imx8m/soc.c to mach-imx/fdt.c and update
disable_cpu_nodes to make it easy to support different socs.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
