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3 Commits

Author SHA1 Message Date
Jit Loon Lim
386fca6896 arch: arm: Agilex5 enablement 
This patch is to enable Agilex5 platform for Intel
product. Changes, modification and new files are
created for board, dts, configs and makefile to
create the base for Agilex5.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
 2024-03-18 14:45:47 +08:00
Siew Chin Lim
0fbf31f966 arm: socfpga: Add base address for Intel N5X device 
Reuse base_addr_soc64.h for Intel N5X device, the address is the
same as Agilex.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
 2021-08-24 15:14:23 +08:00
Siew Chin Lim
bdba67ba87 arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h 
Rename to common file name to used by all SOC64 devices and change
"_S10_" to "_SOC64_" in base_addr_soc64.h.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
 2021-08-24 15:11:34 +08:00