Rather than doing autoprobe within the driver model code, move it out to
the board-init code. This makes it clear that it is a separate step from
binding devices.
For now this is always done twice, before and after relocation, but we
should discuss whether it might be possible to drop the post-relocation
probe.
For boards with SPL, the autoprobe is still done there as well.
Note that with this change, autoprobe happens after the
EVT_DM_POST_INIT_R/F events are sent, rather than before.
Link: https://lore.kernel.org/u-boot/20240626235717.272219-1-marex@denx.de/
Signed-off-by: Simon Glass <sjg@chromium.org>
There is no point in checking the pre_reloc flag, since devices not
marked as pre-reloc will not have been bound, so won't exist yet.
There doesn't seem to be any point in checking if the device has a
valid devicetree node either, so drop that too.
Signed-off-by: Simon Glass <sjg@chromium.org>
Allow the ZyncMP RTC driver to be enabled on Versal architectures.
Also, require DM_RTC since the driver uses the RTC driver model.
Signed-off-by: Vincent Fazio <vfazio@xes-inc.com>
Link: https://lore.kernel.org/r/20250114135812.2605618-1-vfazio@xes-inc.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Update recent parallel memory support code to move to log_debug instead
of debug as per logging in U-Boot documentation
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
Link: https://lore.kernel.org/r/20250107145110.2855213-1-ibai.erkiaga-elorza@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Enable the SPI_STACKED_PARALLEL config option for
all AMD/xilinx platforms, as this is required for parallel and
stacked memories.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250103044812.18828-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
This releases the DP configuration from reset early on during the boot process
for K26 SOM. It will also avoid the boot hang situation should any attempt be
made to configure the DP registers while it is still in reset.
Fixes the same issue as described by the commit 8b81010a2f ("video:
zynqmp: Add support for reset").
Signed-off-by: Neal Frager <neal.frager@amd.com>
Link: https://lore.kernel.org/r/20241218130129.687650-1-neal.frager@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
USB hub initialization is done by driver introduced by commit 09f557e106
("usb: onboard-hub: Add i2c initialization for usb5744 hub") that's why
there is no need to do initialization via variables.
Reported-by: Love Kumar <love.kumar@amd.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/96e9c80aeeed4e9664858bf236476997d17a9914.1734522042.git.michal.simek@amd.com
Replace underscores with hyphens in the clock node names as per
dt-schema rule.
Also, add clock-output-names property to all clock nodes, so that the
resulting clock name do not change when clock node name is changed.
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>
Acked-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1080e31393c3e1b49735b77e7ddc14d570b83222.1733991159.git.michal.simek@amd.com
The main reason for this change is that upstream QEMU has no multiboot
register implemented that's why access to it fails which ends up in CI
failure for our target.
That's why in JTAG bootmode returns 0 which is correct behaviour because
multiboot register is not used in this mode and value should be ignored and
as a side effect it is also fixing CI/Qemu issue.
Also move versal_get_bootmode() to avoid function declaration.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/484b9cafc45e72308a1a29a3ab772020f96784cc.1736155238.git.michal.simek@amd.com
Fix compatiable name for TPS65224 PMIC as defined in
dts/upstream/Bindings/mfd/ti,tps6594.yaml bindings.
Fixes: 1468fbba6d55("power: pmic: tps65941: Add TI TPS65224 PMIC")
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Replace magic numbers in buckval2votl() & buckvolt2val() with macros to
help with clarity and correlate what the numbers correspond to in the
TPS65219 datasheet.
Signed-off-by: Shree Ramamoorthy <s-ramamoorthy@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Replace printf() with pr_err() because pr_err() has a uniform print format
and takes into consideration the log levels supported.
Signed-off-by: Shree Ramamoorthy <s-ramamoorthy@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
i.MX95 uses the same USB IP as i.MX8MM. It can then reuse the ehci-mx6
driver.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Use generic is_cortex_a() functions instead of open-coded midr_el1 read.
No functional change.
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add MIDR entries for Cortex-A57 and Cortex-A76 cores.
Those are used on R-Car Gen3 and Gen4 SoCs respectively.
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Turn the core type check macros into inline functions to perform
better type checking on them. The inline functions get optimized
out in case they are not used. Indent the MIDR_PARTNUM_CORTEX_An
macros in preparation for addition of future three-digit cores
and use MIDR_PARTNUM_SHIFT in MIDR_PARTNUM_MASK to be consistent.
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Implement checkboard() to print current SoC variant used by a board,
e.g. one of:
SoC: RK3308
SoC: RK3308B
SoC: RK3308B-S
when U-Boot proper is running.
U-Boot 2025.01-rc1 (Nov 02 2024 - 20:26:25 +0000)
Model: Radxa ROCK Pi S
SoC: RK3308B
DRAM: 512 MiB (effective 510 MiB)
Information about the SoC variant is read from GRF.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Implement checkboard() to print current SoC model used by a board,
e.g. one of:
SoC: RK3582
SoC: RK3588
SoC: RK3588J
SoC: RK3588S
SoC: RK3588S2
when U-Boot proper is running.
U-Boot 2025.01-rc1 (Nov 10 2024 - 00:31:29 +0000)
Model: Generic RK3588S/RK3588
SoC: RK3588S2
DRAM: 8 GiB
Information about the SoC model and variant is read from OTP.
Also update rk3588s-u-boot.dtsi to include OTP in U-Boot pre-reloc phase,
where checkboard() is called.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Implement checkboard() to print current SoC model used by a board,
e.g. one of:
SoC: RK3566
SoC: RK3566T
SoC: RK3568
SoC: RK3568B2
SoC: RK3568J
when U-Boot proper is running.
U-Boot 2025.01-rc1 (Nov 10 2024 - 00:39:37 +0000)
Model: Generic RK3566/RK3568
SoC: RK3568J
DRAM: 8 GiB (effective 7.7 GiB)
Information about the SoC model and variant is read from OTP.
Also update rk356x-u-boot.dtsi to include OTP in U-Boot pre-reloc phase,
where checkboard() is called.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The mask for aclk_vop_root is 3-bit wide, not 2-bit wide according
to the TRM, so set the mask accordingly.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The commit 7cec3e7019 ("rockchip: rk3588-nanopc-t6: Add support for
NanoPC-T6 LTS") added support for the LTS variant of NanoPC T6. However,
a board specific -u-boot.dtsi file was never added.
Due to the missing -u-boot.dtsi file the LTS fdt included in the FIT is
never tagged with bootph props.
When ENV_IS_IN_SPI_FLASH is enabled, not enabled in defconfig, the env
can successfully load from SPI flash on the non-LTS variant, something
that does not work on the LTS variant due to missing bootph-some-ram
props in the LTS fdt.
Fix this by adding a LTS -u-boot.dtsi file that just include the non-LTS
-u-boot.dtsi file.
Reported-by: Ricardo Pardini <ricardo@pardini.net>
Fixes: 7cec3e7019 ("rockchip: rk3588-nanopc-t6: Add support for NanoPC-T6 LTS")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The IO-domain driver will configure io_vsel and always-on/boot-on
regulators will be enabled based on the board device tree now that
required nodes and Kconfig options is enabled for SPL.
Remove the bob and kevin board specific code from the common rk3399.c,
the IO-domain and regulator driver provide similar functionality.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Add bootph props and enable related Kconfig options to include vital
regulators in SPL.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable use of SDMA mode when reading from eMMC to speed up boot.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
With TPL being used to init DRAM, SPL being used to load FIT and the
adjusted FIT payload offset it is now possible to increase the size
limit of SPL to 256 KB and enable uses of dcache and FIT signature
validation.
Drop SPL_SYS_DCACHE_OFF=y to enable use of dcache in SPL.
Drop SPL_FIT_SIGNATURE=n to enable signature validation of FIT in SPL.
Change SPL_MAX_SIZE to 256 KB now that payload offset has moved in SPI
and TF-A may be loaded to 0x40000 in DRAM.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The eMMC PHY and SPI flash is not used in all xPL phases.
Change to no longer include emmc_phy and spi_flash in all xPL phases.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The last two RK3399 boards, chromebook bob and kevin, have now migraded
to use common bss and stack addresses.
Cleanup and remove Kconfig options no longer needed in rk3399/Kconfig
when all boards now use common bss and stack addresses.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The u-boot.rom image contain u-boot.img FIT instead of the FIT generated
by binman for the u-boot-rockchip.bin image.
Change to include the binman generated FIT for the u-boot.rom image.
This change result in TF-A being included and the use sha256 instead of
crc32 checksum in the u-boot.rom FIT.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Migrate to use TPL, common bss, stack and malloc heap size and addresses
to unify memory use in TPL, SPL and pre-reloc with other RK3399 boards.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(Disable TPL_BLOBLIST)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The chromebook specific u-boot.rom image does not include TPL when
building with TPL=y or ROCKCHIP_EXTERNAL_TPL=y.
Fix this by adding rockchip-tpl and u-boot-tpl nodes to the mkimage node
for the u-boot.rom binman image.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The BootROM on RK3399 only read the first 2 KB of each 4 KB page from
SPI flash. With current FIT payload offset of 0x40000 this limits the
supported TPL+SPL size to only 128 KB.
Change to use 0xE0000 as FIT payload offset, similar to other RK3399
boards, to allow a maximum size for TPL of 192 KB and SPL of 256 KB.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Use the offset configured with SYS_SPI_U_BOOT_OFFS Kconfig option
instead of a hardcoded 0x40000 for the FIT payload offset.
This has no intended impact as SYS_SPI_U_BOOT_OFFS=0x40000.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Building chromebook_bob/kevin with TPL=y ends with a linking error:
arch/arm/mach-rockchip/rk3399/rk3399.o: in function `board_debug_uart_init':
arch/arm/mach-rockchip/rk3399/rk3399.c:148:(.text.board_debug_uart_init+0x34):
undefined reference to `spl_gpio_output'
arch/arm/mach-rockchip/rk3399/rk3399.c:148:(.text.board_debug_uart_init+0x34):
relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `spl_gpio_output'
make[2]: *** [scripts/Makefile.xpl:542: tpl/u-boot-tpl] Error 1
make[1]: *** [Makefile:2134: tpl/u-boot-tpl] Error 2
make: *** [Makefile:568: __build_one_by_one] Error 2
Change to only use spl_gpio functions in SPL to fix this.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
ddrbin_tool interface has been changed. Additional chip_name argument
is now required to modify ddr binary file. Update documentation
to be consistent with the new interface.
Update BL31 and ROCKCHIP_TPL file paths to match current version
of binaries available in the rkbin repository.
Signed-off-by: Daniel Semkowicz <dse@thaumatec.com>
Acked-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
