104104 Commits

Author SHA1 Message Date
Patrice Chotard
5af044da9b ARM: dts: stm32: Add bootph-all in stm32mp215f-dk-u-boot.dtsi
Add temporarily bootph-all property in usart2 and syscfg nodes
to allows stm32mp215f-dk board to boot.
When DT kernel series [1] will be merged and synchronized in U-Boot
this patch will be reverted.

[1] https://lore.kernel.org/linux-arm-kernel/20260203-upstream_uboot_properties-v6-0-0a2280e84d31@foss.st.com/

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:41:48 +01:00
Patrice Chotard
ec3fc57da4 ARM: dts: stm32: Add stm32mp215f-dk-u-boot
Add U-Boot specific file for stm32mp215f-dk board

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:41:48 +01:00
Patrice Chotard
d557099fb0 ARM: stm32mp: Add STM32MP21 support
STM32MP21 application processors (STM32 MPUs) based on a single
Arm Cortex®-A35 core running up to 1.5 GHz and Cortex®-M33 core
running at 300 MHz.

It is pin-compatible with the STM32MP2 series in the VFBGA361
10×10 mm package: the STM32MP21 uses a subset of the STM32MP23
pinout, which itself is a subset of the STM32MP25.

More details available here :
https://www.st.com/en/microcontrollers-microprocessors/stm32mp2-series.html

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:41:48 +01:00
Patrice Chotard
42fa38b925 stm32mp: cmd_stm32key: add support of STM32MP21x
Add cmd_stm32key support for STM32MP21x SoCs family.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:39:34 +01:00
Patrice Chotard
0ec3b31310 stm32mp: syscon: Add STM32MP21 support
Add "st,stm32mp21-syscfg" compatible.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:39:34 +01:00
Patrice Chotard
5635627833 reset: stm32mp21: add stm32mp21 reset driver
Implement STM32MP21 reset drivers using stm32-core-reset API.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:39:34 +01:00
Patrice Chotard
a44b36a044 clk: stm32mp21: Add clock driver support
Add clock driver support for STM32MP21 SoCs.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:39:34 +01:00
Patrice Chotard
6a6f2eb3e6 board: st: common: add uclass_get_device_by_driver()'s return value check
class_get_device_by_driver()'s return value is not checked, in case of BSEC
driver is not probed, dev is not set and used just after as parameter of
misc_read() which leads to a Synchronous Abort.

Add uclass_get_device_by_driver()'s return value check to fix it.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 14:14:15 +01:00
Patrice Chotard
32912d0908 board: st: common: Add support of stm32mp21xx-dk board
Add board identifier for STM32MP21 discovery board = MB2059.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 14:14:15 +01:00
Patrice Chotard
d5cedabe8b stm32mp2: Update size of DDR entry in MMU table
On 1GB board, in particular cases, a prefetch operation is done just above
the 1GB boundary. The DDR size is 1GB (0x80000000 to 0xc0000000), there is
an access on 0xc00017c0 (ie 0x800017c0).

As beginning of DDR is protected by MMU until CONFIG_TEXT_BASE
(0x80000000 to 0x84000000), it triggers the following IAC:

E/TC:0   stm32_iac_itr:192 IAC exceptions [159:128]: 0x200
E/TC:0   stm32_iac_itr:197 IAC exception ID: 137
I/TC:

DUMPING DATA FOR risaf@420d0000
I/TC: =====================================================
I/TC: Status register (IAESR0): 0x11
I/TC: -----------------------------------------------------
I/TC: Faulty address (IADDR0): 0xc00017c0
I/TC: =====================================================
E/TC:0   Panic at /usr/src/debug/optee-os-stm32mp/4.0.0-gitvalid.8>
E/TC:0   TEE load address @ 0x82000000
E/TC:0   Call stack:
E/TC:0    0x82007f30
E/TC:0    0x820444b4
E/TC:0    0x8202dc54
E/TC:0    0x82041fe0
E/TC:0    0x820143b8

By default, in MMU table, the DDR size is set to 4GB, but not all
STM32MP2 based board embeds 4GB, some has only 1 or 2GB of DDR.

The MMU table entry dedicated to DDR need to be updated with the real
DDR size previously read from DT.
After relocation, in enable_caches(), update the MMU table between the
dcache_disable() / dcache_enable() with the real DDR size.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 14:13:08 +01:00
Patrice Chotard
5d5195073c stm32mp: fix array bounds checks
Fix index check against array size. If that index is equal
to the array size, we'll access one-past-the-end of the array.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 14:12:34 +01:00
Patrice Chotard
71433d2771 stm32mp: stm32prog: Remove fsbl_nor_detected from stm32prog_data struct
No more need to test if a fsbl partition is present on NOR when booting
from serial or USB. Now MTD devices are automatically populated with
partition information found in DT. Remove fsbl_nor_detected boolean from
stm32prog_data struct and all code using it.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 14:11:59 +01:00
Fabien Dessenne
04dcaadd43 pinctrl: pinctrl_stm32: prevent the use of the secure protected pins
The hardware denies any access from the U-Boot non-secure world to the
secure-protected pins. Hence, prevent any driver to configure such a pin.
Identify the secure pins with "NO ACCESS" through the 'pinmux status -a'
command.
Use a driver data structure to identify which hardware versions support
this feature.

Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 14:09:45 +01:00
Fabien Dessenne
7accb716c1 gpio: stm32-gpio: prevent the use of the secure protected pins
The hardware denies any access from the U-Boot non-secure world to the
secure-protected pins. Hence, prevent any driver to request such a pin.

Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 14:09:45 +01:00
Tom Rini
4f70106bea Prepare v2026.04-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
v2026.04-rc3
2026-02-23 13:17:02 -06:00
Eric Kilmer
e365a269df fs/squashfs: fix heap buffer overflow in sqfs_frag_lookup()
sqfs_frag_lookup() reads a 16-bit metadata block header whose lower
15 bits encode the data size. Unlike sqfs_read_metablock() in
sqfs_inode.c, this function does not validate that the decoded size is
within SQFS_METADATA_BLOCK_SIZE (8192). A malformed SquashFS image can
set the size field to any value up to 32767, causing memcpy to write
past the 8192-byte 'entries' heap buffer.

Add the same bounds check used by sqfs_read_metablock(): reject any
metadata block header with SQFS_METADATA_SIZE(header) exceeding
SQFS_METADATA_BLOCK_SIZE.

Found by fuzzing with libFuzzer + AddressSanitizer.

Signed-off-by: Eric Kilmer <eric.kilmer@trailofbits.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
2026-02-23 12:45:50 -06:00
Anshul Dalal
30b8c03d8c board: ti: am64,j721*: use correct fdt if eeprom detection fails
We currently provide default board names for each board in their
respective evm.c file. However for custom boards, this behaviour
overwrites the default DT as set in the defconfig
(CONFIG_DEFAULT_FDT_FILE or CONFIG_DEFAULT_DEVICE_TREE).

This patch changes the default name to be NULL which prevents this
overwrite and allows ti_set_fdt_env to instead fallback to the correct
DT as set in Kconfig.

Signed-off-by: Anshul Dalal <anshuld@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2026-02-20 08:46:56 -06:00
Chintan Vankar
ebe62142fc arm: mach-k3: j722s: Update SoC data to add wake-up I2C device
Update dev-data and clk-data to include wake-up I2C device for J722s.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
Tested-by: Richard Genoud <richard.genoud@bootlin.com>
2026-02-20 08:46:51 -06:00
Tom Rini
7dca54ef4c Merge patch series "test: cmd: Add test for zip/unzip/gzwrite commands"
Marek Vasut <marek.vasut+renesas@mailbox.org> says:

Enable zip command in sandbox so it is always build tested.
Add simple test for zip/unzip/gzwrite commands so they are
unit tested.

Link: https://lore.kernel.org/r/20260205014153.218621-1-marek.vasut+renesas@mailbox.org
2026-02-18 15:02:58 -06:00
Marek Vasut
6be3db6c1a test: cmd: Add test for zip/unzip/gzwrite commands
Add simple test for zip/unzip/gzwrite commands. The test works as
follows. First, create three buffers with a bit of space between
each of them, fill them with random data, then compress data in
buffer 1 into buffer 2, decompress data in buffer 2 either directly
into buffer 3 or into MMC 1 and then read them back into buffer 3,
and finally compare buffer 1 and buffer 3, they have to be identical.

The buffers are filled with random data to detect out of bounds writes.
Test for various sizes, both small and large and unaligned.

The test uses ut_assert_skip_to_line() to skip over gzwrite progress
bar. Since the progress bar updates fill up the console record buffer,
increase the size of it to compensate.

Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-02-18 15:02:58 -06:00
Marek Vasut
8a056a1058 configs: sandbox: Enable zip command
What is not being built and tested in CI, breaks. Enable the 'zip'
command in sandbox to get it build tested in preparation for an
actual unit test.

Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-02-18 15:02:58 -06:00
Wadim Egorov
73823d1c58 arm: dts: k3-am64-phycore-som-ddr4: Update DDR timings
Update DDR timings to increase stability in higher temperature ranges.

Update DDR settings:
  - SysConfig DDR tool v0.09.05
  - Package: ALV
  - Extended temperature range -40C to 105C
  - Lower tREFI (ns) to 3900

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Tested-by: Daniel Schultz <d.schultz@phytec.de>
2026-02-18 14:57:31 -06:00
Jeremy Compostella
8666b16015 x86/coreboot: Exclude memory regions starting above 4GB
This commit updates the RAM region filtering logic in
board_get_usable_ram_top() to skip any memory regions whose start address
is above 4GB. Previously, only the end address was capped at 4GB, but
regions entirely above this threshold were still considered.

Typically, the following memory map entries would cause
board_get_usable_ram_top() to return 0x100000000, which is incorrect.

    start=00000000, end=00001000, type=16
    start=00001000, end=000a0000, type=1
    start=000a0000, end=000f6000, type=2
    start=000f6000, end=000f7000, type=16
    start=000f7000, end=00100000, type=2
    start=00100000, end=6f170000, type=1
    start=6f170000, end=70000000, type=16
    start=70000000, end=80800000, type=2
    start=e0000000, end=f8000000, type=2
    start=fa000000, end=fc000000, type=2
    start=fc800000, end=fc880000, type=2
    start=fd800000, end=fe800000, type=2
    start=feb00000, end=feb80000, type=2
    start=fec00000, end=fed00000, type=2
    start=fed20000, end=fed80000, type=2
    start=feda1000, end=feda2000, type=2
    start=fedc0000, end=fede0000, type=2
    start=100000000, end=102400000, type=2
    start=102400000, end=47f800000, type=1
    start=4000000000, end=4020000000, type=2

By adding a check to continue the loop if the region's start address
exceeds 0xffffffffULL, the function now properly ignores regions that are
not usable in 32-bit address space.

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
2026-02-16 12:00:42 -06:00
Siddharth Vadapalli
e7ef80f670 board: ti: j721e,j7200: fix do_main_cpsw0_qsgmii_phyinit
Since commit 27cc5951c862 ("include: env: ti: add default for
do_main_cpsw0_qsgmii_phyinit"), the value of the environment variable
do_main_cpsw0_qsgmii_phyinit happened to remain '0' and couldn't be
changed without user intervention. This behavior is due to the following
cyclic dependency:
A) ti_common.env sets do_main_cpsw0_qsgmii_phyinit to '0' and its value
   can only be updated automatically by main_cpsw0_qsgmii_phyinit.
B) main_cpsw0_qsgmii_phyinit is defined in j721e.env and it can run only
   if 'do_main_cpsw0_qsgmii_phyinit' is already '1' which isn't possible
   unless the user manually assigns the value.

Fix the aforementioned cyclic dependency by using board_late_init() to
detect the QSGMII Daughtercard and set do_main_cpsw0_qsgmii_phyinit.

Additionally, to address the issue of do_main_cpsw0_qsgmii_phyinit being
'undefined' for other platforms, replace:
	if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1;
with:
	if env exists do_main_cpsw0_qsgmii_phyinit;
in ti_common.env.

Fixes: 27cc5951c862 ("include: env: ti: add default for do_main_cpsw0_qsgmii_phyinit")
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Anshul Dalal <anshuld@ti.com>
2026-02-16 11:52:02 -06:00
Martin Schwan
c3538f788d bootstd: rauc: Fix null pointer access while checking root part
Fix a segmentation fault caused by a null pointer access during root
partition checking. The function part_get_info() was falsely given null
for the disk_partition struct, which later resulted in accessing a null
pointer and thus undefined behavior.

Fixes: 5d7c080ae5dc ("bootstd: rauc: Don't check root part filesystem")
Signed-off-by: Martin Schwan <m.schwan@phytec.de>
2026-02-16 11:52:01 -06:00
Hugo Villeneuve
2ac30d21e4 cmd: pxe_utils: fix syntax error in comments
Add missing "to" so that the sentence makes sense.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
2026-02-16 11:52:01 -06:00
James Hilliard
5ebf0c55a2 image: fit: Apply overlays using aligned writable FDT copies
libfdt expects FDT/DTO blobs to be 8-byte aligned. When loading the
base FDT or overlays from a FIT, the mapped buffer may be unaligned,
which can break fdt_open_into() on strict-alignment architectures.

boot_get_fdt_fit() relocates the base FDT with boot_relocate_fdt()
before applying overlays. That uses the bootm memory map and can
overlap with the FIT buffer when the FIT is loaded into RAM,
corrupting data needed to load the kernel and ramdisk.

Allocate writable, 8-byte aligned copies of the base FDT and overlays
with memalign() and fdt_open_into(). Grow the base buffer as needed,
apply overlays to it and pack the final tree. Free each temporary
overlay copy after application and check fdt_pack() errors.

Fixes: 8fbcc0e0e839 ("boot: Assure FDT is always 8-byte aligned")
Fixes: 881f0b77dc8c ("image: apply FDTOs on FDT image node")
Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
Cc: Jamie Gibbons <Jamie.Gibbons@microchip.com>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
2026-02-16 11:52:01 -06:00
Tom Rini
a79edd52a8 MAINTAINERS: Remove a few inactive people
It has been a long while since Jagan Teki, Joe Hershberger or Ramon
Fried have been active in the community. We thank them for their time
over the years. Remove them from the active maintainer list and mark a
few things as Orphaned for now.

Signed-off-by: Tom Rini <trini@konsulko.com>
2026-02-16 11:52:01 -06:00
David Lechner
6f96026b1e test/py: Fix spelling of source_dir in docstring
Fix a typo in the docstring for run_build() where source_dir was
misspelled.

Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-02-16 11:52:01 -06:00
Tom Rini
fec27316cf Merge branch 'master' of git://source.denx.de/u-boot-usb
- A fix for CDNS3 in correctly determining dr_mode for OTG.
2026-02-16 11:52:01 -06:00
Siddharth Vadapalli
bfb530e06c usb: cdns3: use VBUS Valid to determine role for dr_mode OTG
The cdns3_bind() function is responsible for identifying the appropriate
driver to bind to the USB Controller's device-tree node. If the device-tree
node has the 'dr_mode' property set to 'otg', the existing approach fails
to bind a driver, leading to loss of functionality.

To address this, use the VBUS Valid field of the OTG Status register to
determine the role as follows:
- If VBUS Valid field is set, it indicates that a USB Host is supplying
  power and the Controller should assume the Peripheral role.
- If VBUS Valid field is clear, it indicates the absence of a USB Host and
  the Controller should assume the Host role.

Additionally, when 'dr_mode' happens to be 'otg' and the STRAP settings
are not specified, use VBUS Valid to determine the role in cdns3_drd_init()
and assign it to cdns->dr_mode.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
2026-02-16 15:08:43 +01:00
Tom Rini
6274e400fc Pull request efi-2026-04-rc3
UEFI:
 
 * add missing EFI_CALL around tcg2 read_blocks calls
 * fix ECPT table size computation
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Merge tag 'efi-2026-04-rc3' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request efi-2026-04-rc3

CI: https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/29293

UEFI:

* add missing EFI_CALL around tcg2 read_blocks calls
* fix ECPT table size computation
2026-02-15 15:08:14 -06:00
Vincent Stehlé
ca4eda24c6 efi_loader: fix ecpt size computation
The size of the memory allocated for the EFI Conformance Profiles Table is
computed with `num_entries' always equal to zero, which is incorrect when
CONFIG_EFI_EBBR_2_1_CONFORMANCE is enabled.

This can be verified by allocating the ECPT memory with malloc() instead of
efi_allocate_pool(), building u-boot with sandbox_defconfig and
CONFIG_VALGRIND=y, and by finally running the following command:

  valgrind --suppressions=scripts/u-boot.supp \
    ./u-boot -T -c 'efidebug tables'

Fix this by using an array of the supported profiles GUIDs instead, which
should also be easier to extend in the future as U-Boot should publish the
GUIDs for all supported EBBR revisions.

Fixes: 6b92c1735205 ("efi: Create ECPT table")
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Jose Marinho <jose.marinho@arm.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2026-02-15 08:30:57 +01:00
Vincent Stehlé
05b13c0589 efi_loader: add missing EFI_CALL around tcg2 read_blocks calls
The read_blocks() function from the Block IO protocol is a UEFI function;
make sure to call it from within U-Boot using the EFI_CALL() macro.

To demonstrate the issue on an AArch64 machine, define the DEBUG macro in
include/efi_loader.h and build u-boot with sandbox_defconfig, then download
and uncompress the ACS-DT image [1], and finally execute the following
command:

  $ ./u-boot -T -c " \
      host bind 0 systemready-dt_acs_live_image.wic; \
      setenv loadaddr 0x10000; \
      load host 0 \${loadaddr} EFI/BOOT/Shell.efi; \
      bootefi \${loadaddr} \${fdtcontroladdr}"

The following assertion should fail:

  lib/efi_loader/efi_net.c:858: efi_network_timer_notify: Assertion `__efi_entry_check()' failed.

This happens due to the following EFIAPI functions call chain:

  efi_start_image()
    efi_disk_read_blocks()
      (due to the missing EFI_CALL, entry_count == 2)
      efi_network_timer_notify()

Link: https://github.com/ARM-software/arm-systemready/releases/download/v25.12_DT_3.1.1/systemready-dt_acs_live_image.wic.xz [1]
Fixes: ce3dbc5d080d ("efi_loader: add UEFI GPT measurement")
Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Masahisa Kojima <kojima.masahisa@socionext.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Masahisa Kojima <kojima.masahisa@socionext.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2026-02-15 08:26:33 +01:00
Suhaas Joshi
f9ffeec4bd board: toradex: Make A53 get RAM size from DT in K3 boards
`dram_init()` is called by R5 SPL and U-Boot, both. It starts by
computing the size of the RAM. In verdin-am62(p), it does so by calling
`get_ram_size()`. This function computes the size of the RAM by writing
over the RAM.

When R5 computes the size of the RAM, it does not update the DT with
this size. As a result, when A53 invokes `dram_init()` again, it has to
compute the size through `get_ram_size()` again.

Commit 13c54cf588d82 and 0c3a6f748c9 add firewall over ATF's and OPTEE's
regions. This firewall is added during the R5 SPL stage of boot. So when
A53 attempts to write over RAM in `get_ram_size()`, it writes over the
protected region. Since A53 is a non-secure core, this is blocked by the
firewall.

To fix this, do the following:
    * Implement `spl_perform_board_fixups()` function for verdin-am62
      and verdin-am62p. Make this function call `fixup_memory_node()`,
      which updates the DT.
    * Add an if-block in `dram_init()`, to ensure that only R5 is able
      to call `get_ram_size()`, and that A53 reads this size from the
      DT.

Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2026-02-12 08:12:09 -06:00
Tom Rini
f71ae39529 AMD/Xilinx/FPGA changes for v2026.04-rc3
clk:
 - zynqmp clk fixes
 
 phy:
 - sync vsc8541 config
 
 versal2:
 - fix GIC configuration
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Merge tag 'xilinx-for-v2026.04-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

AMD/Xilinx/FPGA changes for v2026.04-rc3

clk:
- zynqmp clk fixes

phy:
- sync vsc8541 config

versal2:
- fix GIC configuration
2026-02-12 08:05:44 -06:00
Tom Rini
dffccda75c u-boot-dfu-20260211
USB Gadget:
 * dwc3: Support ip and version type
 * dwc3: Increase controller halt timeout
 * dwc3: Don't send unintended link state change
 * dwc3: Improve reset sequence
 * dwc2: Move dr_mode check to bind to support RK3288/RK3506 with
   2 DWC2 controllers
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Merge tag 'u-boot-dfu-20260211' of https://source.denx.de/u-boot/custodians/u-boot-dfu

u-boot-dfu-20260211

USB Gadget:
* dwc3: Support ip and version type
* dwc3: Increase controller halt timeout
* dwc3: Don't send unintended link state change
* dwc3: Improve reset sequence
* dwc2: Move dr_mode check to bind to support RK3288/RK3506 with
  2 DWC2 controllers
2026-02-11 08:38:19 -06:00
Tom Rini
0e4baa3291 A coverity fix and documentation update from Heiko on SM3 support
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Merge tag 'tpm-master-11022026' of https://source.denx.de/u-boot/custodians/u-boot-tpm

A coverity fix and documentation update from Heiko on SM3 support
2026-02-11 08:37:44 -06:00
Heiko Schocher
1e79d9c763 doc: cmd: add documentation for sm3sum
add documentation for sm3sum command.

Signed-off-by: Heiko Schocher <hs@nabladev.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2026-02-11 11:13:47 +02:00
Heiko Schocher
546687c8dc lib: sm3: fix coverity error
Coverity scan reported:

CID 449815:         Memory - illegal accesses  (OVERRUN)
Overrunning array of 64 bytes at byte offset 64 by dereferencing pointer
"sctx->buffer + partial". [Note: The source code implementation of the
function has been overridden by a builtin model.]

In line: 252
   memset(sctx->buffer + partial, 0, SM3_BLOCK_SIZE - partial);

The respective line should be:

memset(sctx->buffer + partial, 0, SM3_BLOCK_SIZE - partial - 1);

as partial gets incremented by one before.

Signed-off-by: Heiko Schocher <hs@nabladev.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2026-02-11 11:13:47 +02:00
Pranav Tilak
ce6fc049b7 net: phy: mscc: Enable RMII clock output for VSC8541 PHY
Set RMII reference clock output to enabled (1) by default for VSC8541
PHY in RMII mode. The RMII specification requires a 50MHz reference
clock, and many board designs expect the PHY to provide this clock to
the MAC controller.

Previously, the driver defaulted rmii_clk_out to 0 (disabled) for all
interface modes, which caused the PHY to not output the required 50MHz
clock. This resulted in MAC-PHY communication failures and prevented
network operations like DHCP from working on RMII-configured boards.

This change alligns with the hardware power-up default behavior and
aligns with both the generic PHY driver and Linux MSCC PHY driver
implementations.

Signed-off-by: Pranav Tilak <pranav.vinaytilak@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20260129081054.1703479-1-pranav.vinaytilak@amd.com
2026-02-11 09:41:26 +01:00
Maheedhar Bollapalli
85bbd16750 arm64: versal2: fix GICD/GICR base addresses for Versal Gen 2
Versal2 was using wrong GIC base mappings, causing GICR_TYPER reads to
not match EL1 MPIDR. This led U-Boot to walk beyond the per-CPU GICR
frames, access out-of-range addresses, and hit a synchronous exception
during early gic init percpu while booting up on alternate core
i.e., non cpu0.

Update Versal Gen 2 headers to the correct Versal Gen 2 bases.

Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d0bc3fe1af8409fcfe505e55fb7042a33b845a4e.1770721325.git.michal.simek@amd.com
2026-02-11 09:26:17 +01:00
Tom Rini
712765339a Merge patch series "Update DDR Configurations"
Santhosh Kumar K <s-k6@ti.com> says:

This series updates the DDR Configurations according to the SysConfig DDR
Configuration tool v0.10.32 for the following devices [1]
 - AM64x EVM
 - AM62x SK
 - AM62x LP SK
 - AM62Ax SK
 - AM62Px SK

Testing:
memtester - 50% of memory for 10 loops - PASSED

[1] https://dev.ti.com/tirex/content/Processor_DDR_Config_0.10.32.0000/docs/REVISION_HISTORY.html

Link: https://lore.kernel.org/r/20260203063529.1551907-1-s-k6@ti.com
2026-02-10 12:57:02 -06:00
Santhosh Kumar K
3391e5ff15 arm: dts: k3-am62p: Update DDR Configurations
Update the DDR Configurations for AM62Px SK according to the SysConfig
DDR Configuration tool v0.10.32. [1]

[1] https://dev.ti.com/tirex/content/Processor_DDR_Config_0.10.32.0000/docs/REVISION_HISTORY.html

Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2026-02-10 12:56:54 -06:00
Santhosh Kumar K
4f5fcfcea7 arm: dts: k3-am62a: Update DDR Configurations
Update the DDR Configurations for AM62Ax SK according to the SysConfig
DDR Configuration tool v0.10.32. [1]

[1] https://dev.ti.com/tirex/content/Processor_DDR_Config_0.10.32.0000/docs/REVISION_HISTORY.html

Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2026-02-10 12:56:54 -06:00
Santhosh Kumar K
92f1f586c2 arm: dts: k3-am62-lp: Update DDR Configurations
Update the DDR Configurations for AM62x LP SK according to the SysConfig
DDR Configuration tool v0.10.32. [1]

[1] https://dev.ti.com/tirex/content/Processor_DDR_Config_0.10.32.0000/docs/REVISION_HISTORY.html

Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2026-02-10 12:56:54 -06:00
Santhosh Kumar K
9ce3b50b8d arm: dts: k3-am62x: Update DDR Configurations
Update the DDR Configurations for AM62x SK according to the SysConfig
DDR Configuration tool v0.10.32. [1]

[1] https://dev.ti.com/tirex/content/Processor_DDR_Config_0.10.32.0000/docs/REVISION_HISTORY.html

Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2026-02-10 12:56:54 -06:00
Santhosh Kumar K
f5ef79fe65 arm: dts: k3-am64: Update DDR Configurations
Update the DDR Configurations for AM64x EVM according to the SysConfig
DDR Configuration tool v0.10.32. [1]

[1] https://dev.ti.com/tirex/content/Processor_DDR_Config_0.10.32.0000/docs/REVISION_HISTORY.html

Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2026-02-10 12:56:54 -06:00
Peter Korsgaard
6d865c1ee6 drivers/clk/clk_zynqmp.c: get rid of compiler warning for !CONFIG_CMD_CLK builds
When built without CONFIG_CMD_CLK, we get a warning about the unused
clk_names variable:

../drivers/clk/clk_zynqmp.c:153:27: warning: ‘clk_names’ defined but not used [-Wunused-const-variable=]
  153 | static const char * const clk_names[clk_max] = {

So also guard it with CONFIG_CMD_CLK to get rid of that.

Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20260119095437.2775081-2-peter@korsgaard.com
2026-02-10 09:27:48 +01:00
Peter Korsgaard
00ea1fc21a drivers/clk/Kconfig: fix "related" typo in help text
It looks like the original zynqmp typo was copied to versal as well.  Fix
both.

Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20260119095437.2775081-1-peter@korsgaard.com
2026-02-10 09:27:48 +01:00