As of commit dc8754e8e4 ("clk/qcom: apq8016: improve clk_enable logging")
there are now warnings in the U-Boot console on DragonBoard 410c:
apq8016_clk_enable: unknown clk id 122
apq8016_clk_enable: unknown clk id 123
apq8016_clk_enable: unknown clk id 124
apq8016_clk_enable: unknown clk id 125
This is because we don't implement enable() properly for the SDCC clocks.
Currently they are being enabled as part of set_rate().
Fix this by moving the enable calls out of the apq8016_clk_init_sdc()
function and convert them to the equivalent GATE_CLK_POLLED() definitions.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-6-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Convert the usages of GATE_CLK() in clock-apq8016 to GATE_CLK_POLLED() to
make sure that we poll the status when enabling clocks:
- PRNG_AHB_CLK is a vote clock, so we poll a different register address.
- The USB clocks are simple branches, so enable/poll is the same register.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-5-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
GATE_CLK() in its current state is unsafe: A simple write to the clock
enable register does not guarantee that the clock is immediately running.
Without polling the clock status, we may issue writes to registers before
the necessary clocks start running. This doesn't seem to cause issues in
U-Boot at the moment, but for example removing the CLK_OFF polling in TF-A
for the SMMU clocks on DB410c reliably triggers an exception during boot.
Make it possible to poll the branch clock status register, by adding a new
GATE_CLK_POLLED() macro that takes the extra register address. Existing
usages work just as before, without polling the clock status. Ideally all
usages should be updated to specify the correct poll address in the future.
The Qualcomm naming for these clocks is "branch" and not "gate", but let's
keep the existing naming for now to avoid confusion until all others
drivers have been converted.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-4-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
The other clock enable functions in clock-qcom.c use setbits_le32() to
read/modify/write the enable registers. Use the same for qcom_gate_clk_en()
to simplify the code a bit.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-3-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
This avoids having to inline it separately into every single clock driver,
when U-Boot is built with support for multiple SoCs.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-2-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
The SDCC_...(n) macros in clock-apq8016.c result in the wrong addresses:
- SDCC1: SDCC_APPS_CBCR(0) = ((0 * 0x1000) + 0x41018) = 0x41018
Should be 0x42018, this is an invalid register close to the USB clocks.
- SDCC2: SDCC_APPS_CBCR(1) = ((1 * 0x1000) + 0x41018) = 0x42018
Should be 0x43018, this is the SDCC1 clock.
When we try to enable SDCC2, we actually end up enabling SDCC1. When we try
to enable SDCC1, we just issue some broken register writes.
This hasn't caused any trouble so far, because the boot firmware is keeping
both SDCC clocks running. However, if these clocks are disabled when
entering U-Boot, MMC initialization is failing.
Fix this by using the proper offset for the macros. The SDCC_CMD_RCGR() was
already correct, but change it the same way for consistency.
Fixes: 085921368b ("arm: Add support for Qualcomm Snapdragon family")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-1-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
The device name is always clk_qcom... Not very useful.
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
These are all usually enabled, hence we don't (yet) bother configuring
their RCG src clocks.
Add them to remove the errors about missing clocks when the UFS and MMC
drivers probe.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250317-sc7280-mmc-ufs-clocks-v1-2-38e05c16511b@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
These are necessary for USB gadget to come up properly, now that
qcom_gate_clk_en fails on unknown clocks.
Signed-off-by: Sam Day <me@samcday.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250319-sdm845-usb-clocks-v1-1-ddea854f62ec@samcday.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Add support for a bunch of new clocks, including PCIe, GENI (for all
peripherals used on the RB3 Gen 2), and some missing USB clocks.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250314-sc7280-more-clocks-v1-3-ead54487c38e@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
If we try to enable a gate clock that doesn't exist, we used to just
fail silently. This may make sense for early bringup of some core
peripherals that we know are already enabled, but it only makes
debugging missing clocks more difficult.
Bubble up errors now that qcom_gate_clk_en() can return an error code to
catch any still-missing clocks and make it easier to find missing ones
as more complicated peripherals are enabled.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250314-sc7280-more-clocks-v1-1-ead54487c38e@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
This clock needs to be enabled for the msm-rng driver to work on
MSM8916, otherwise accessing the PRNG register block causes a data
abort.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Sam Day <me@samcday.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250212-msm-rng-fixes-v2-2-645cf8d3fd3c@samcday.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
This reads a little bit nicer (IMO), and is consistent with the kernel.
Signed-off-by: Sam Day <me@samcday.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250212-msm-rng-fixes-v2-1-645cf8d3fd3c@samcday.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Add initial set of clocks and resets for enabling U-Boot on ipq9574
based RDP platforms.
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20250226064505.1178054-4-quic_varada@quicinc.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
The PCIe PIPE clock requires a special setup function to
mux & enable the clock from the PCIe PHY before the PHY
has enabled the clock.
Import the clk_phy_mux_enable() from the Linux driver to
use the same implementation regarding the PIPE clock.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241125-topic-pcie-clk-v1-1-4315d1e4e164@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Add initial set of clocks and resets for enabling U-Boot on QCS9100
based Ride platforms.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20250110050817.3819282-4-quic_varada@quicinc.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Add support for dumping a few of the clocks used on Qualcomm platforms.
Naming the Global PLL's, Root Clock Generators, and gate clocks.
This helps a lot with platform bringup and feature enablement by making
it easy to sanity check that the clocks are programmed correctly.
== Usage ==
Enable CONFIG_CMD_CLK and "#define LOG_DEBUG" at the top of
qcom-<soc>.c.
The "clk dump" command should print the states of all the gates, GPLLs
and RCGs for your SoC.
== Glossary ==
RCG: Root Clock Generator
* Takes in some fairly arbitrary high freq clock (configurable clock
source and options for taking just even pulses and other things)
* Output frequency = input_freq * (m/n) * (1/d) where m/n are arbitrary
8 or 16-bit values (depending on the RCG), and d is a number (with
support for .5 offsets).
GPLL: Global Phase Locked Loop
* Crystal as input
* integer multiplier + exponent part (2^-40)
Gate: Simple on/off clock
* Put between RCGs and the peripherals they power
* Required to allow for correct power sequencing
If you do the maths manually using the equations from "clk dump", the
numbers should roughly line up by they're likely to be out by a handful
of MHz. They output is formatted so that it can be pasted directly into
the python interpreter.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Add clock, reset and power domain driver for SM8150. Driver code is
based on the similar U-Boot drivers. All constants are taken from the
corresponding Linux driver.
This driver supports clock rate setting only debug UART,
RGMII/Ethernet modules and USB controller.
Co-authored-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Julius Lehmann <lehmanju@devpi.de>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
We don't actually need any clocks to get UFS up and running, resets are
useful though.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
IPQ4019 has more networking related resets that will be required for future
wired networking support, so lets add them.
This syncs the driver with Linux.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
ESS clock is the Ethernet Subsystem clock, so lets add it as its
already configured by SBL1.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Various minor fixes and improvements:
* Fix Qualcomm SPMI v5 support
* Move default environment to a file
* Add support for special pins (e.g ufs/mmc reset/data pins)
* IPQ moves to OF_UPSTREAM and receives some cleanup and MAINTAINERS
changes
* Add a reset driver for devices without PSCI
* msm8916 USB clock improvements for mobile devices
I2C clocks are not initialized by the SBL, so lets add support for clocks
required by both of the QUP I2C controllers.
BLSP1 AHB clock is already initialized by SBL, but QUP I2C driver is
requesting it so we have to add it to the enable list.
Based off QCS404 clock driver.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
The newer "register map for simple gate clocks" support added for qcom
clocks is used. As a result gcc_apq8016 now has a mixture of the old and
new styles. I didn't (and still don't!) feel comfortable enough in this
area to update the existing code.
Signed-off-by: Sam Day <me@samcday.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.
Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.
This reverts commit c8ffd1356d, reversing
changes made to 2ee6f3a5f7.
Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
SE HMIBSC board uses UART1 as the main debug console, so add
corresponding clocks and pinmux support. Along with that update
instructions to enable clocks for debug UART support.
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
clk_set_rate() should return the clock rate that was set. The IPQ4019
clock driver doesn't set any rates yet but it should still return the
expected value so that drivers can work properly.
For a baud rate of 115200 with an expected bit clock divisor of 16, the
clock rate should be 1843200 so return that frequency.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
The clk_init_uart() helper always returns 0, but we're meant to return a
real clock rate. Given that we hardcode 115200 baud, just return the
clock rate that we set.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Add the GCC and TCSRCC clock driver for the SM8650 SoC.
The GCC driver uses the clk-qcom infrastructure to support GDSCs,
Resets and gates. While the TCSRCC is a simpler clock driver which
only supports gates.
The GCC enable and set_rate callbacks contains some tweaks to
setup clocks for Debug UART, SDCard controller and USB.
The TCSRCC gates returns the XO frequency, which is used by the
Synopsys eUSB2 driver to determine the PHY configuration.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Add the GCC and TCSRCC clock driver for the SM8550 SoC.
The GCC driver uses the clk-qcom infrastructure to support GDSCs,
Resets and gates. While the TCSRCC is a simpler clock driver which
only supports gates.
The GCC enable and set_rate callbacks contains some tweaks to
setup clocks for Debug UART, SDCard controller and USB.
The TCSRCC gates returns the XO frequency, which is used by the
Synopsys eUSB2 driver to determine the PHY configuration.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Allow setting the clock rate for the SD card core clock. This is
required for SD card support on SDM845 devices.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Add a clock driver for the SM8250 SoC. This driver can enable necessary
clocks for UART, UFS, USB, and MMC.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Add a driver for the clock controller in the SM6115 SoC, this is used in
the QRB4210 RB2 board.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Most devices only initialise the USB clocks for us if we boot via
"fastboot boot", add the missing clock configuration to get both USB
ports working regardless of the bootloader state.
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
