Various Qualcomm additions this cycle:
* USB superspeed support for 1 platform
* Initial support for the Milos platform and the Fairphone Gen 6
(chainloaded from ABL)
* Improved support for booting with OP-TEE on supported platforms
* Initial basic power domain support
Notably there is a generic change to the device core, missing power
domains will no longer cause a device to fail probe and instead will
just print a warning. This shouldn't affect any existing platforms.
- do not fail when setting SD_EMMC_x_CLK0 on GX/G12
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Merge tag 'u-boot-amlogic-next-20260427' of https://source.denx.de/u-boot/custodians/u-boot-amlogic
- enable EFI Capsule on Disk (+ sysreset fixup/cleanup)
- do not fail when setting SD_EMMC_x_CLK0 on GX/G12
Add Clock driver for the GCC block found in the Milos SoC.
The qcom-snps-eusb2-hsphy driver requires the TCXO frequency ("ref"
clock), so we need to pass that as well.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://patch.msgid.link/20260318-milos-bringup-v2-2-650b91dd75d8@fairphone.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Add support for GCC_USB3_PRIM_PHY_PIPE_CLK which is required by
the USB3 PHY on SC7280/QCM6490 platforms.
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20251203110735.1959862-2-balaji.selvanathan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
When a clock parent entry is DUMMY_PARENT (0xFFFFFFFE), masking it
with CLK_PARENTS_ID_MASK (0xFFFF) produces the value 0xFFFE (65534).
This value is stored in parent->id and later used as a clock array
index in versal_clock_get_parentid(). Since clock_max_idx is
typically 228, accessing clock[65534] is out-of-bounds, and the
garbage value read is used as a clock ID in subsequent clock rate
calculations, eventually causing U-Boot to crash. This is observed
as a crash during "clk dump" on AMD Versal Gen 2.
Fix this by setting parent->id = 0 for DUMMY_PARENT entries.
Fixes: 95105089afe2 ("clk: versal: Add clock driver support")
Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20260327101053.900154-1-padmarao.begari@amd.com
Since Linux v7.0, the MMC controllers has the following properties:
assigned-clocks = <&clkc CLKID_SD_EMMC_x_CLK0>;
assigned-clock-rates = <24000000>;
Which causes mmc controllers to fail in probe.
Make sure we do not fail until we properly implement rate setup.
Tested-by: Ferass El Hafidi <funderscore@postmarketos.org> # on lepotato
Link: https://patch.msgid.link/20260422-u-boot-amlogic-test-v1-1-b5790d3c04e0@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
The clk_ops structures (mtk_clk_apmixedsys_ops, mtk_clk_topckgen_ops,
mtk_clk_infrasys_ops) are already declared with extern in clk-mtk.h,
which is included by this file. The forward declarations in clk-mtk.c
are therefore redundant and can be removed.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Link: https://patch.msgid.link/e9c95470374cb78254dacfe1d657a26f2f908981.1776326933.git.weijie.gao@mediatek.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Add grandparent device variable in mtk_find_parent_rate() to allow
the grandparent device being reused instead of calling
dev_get_parent(priv->parent) multiple times.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Link: https://patch.msgid.link/726ccc71593f6c224c13142a0bd4a9f6f0f81445.1776326933.git.weijie.gao@mediatek.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
The refactoring in commit 00d0ff7f81bf ("clk: mediatek: refactor parent
rate lookup functions") introduced a regression where fixed PLL clocks
using mtk_clk_fixed_pll_ops are not properly recognized as valid parents
in the CLK_PARENT_APMIXED case.
Fixed PLL clocks are implemented using mtk_clk_fixed_pll_ops instead of
mtk_clk_apmixedsys_ops, but they can also serve as parent clocks in the
APMIXED domain. The parent lookup function needs to check for both
driver ops to properly resolve the parent clock device.
Add mtk_clk_fixed_pll_ops checks alongside mtk_clk_apmixedsys_ops checks
in mtk_find_parent_rate() to restore support for fixed PLL parent clocks.
Fixes: 00d0ff7f81bf ("clk: mediatek: refactor parent rate lookup functions")
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Link: https://patch.msgid.link/923e50db696d910803828cd26b0ca0fbbfe11570.1776326933.git.weijie.gao@mediatek.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
The SCMI clock protocol version was only being fetched when CLK_CCF
was enabled. On non-CCF platforms, the probe function returned early
without fetching the version, leaving priv->version as 0.
This caused issues because code paths like scmi_clk_gate() and
scmi_clk_get_permissions() depend on priv->version to determine
which protocol message format to use, even in non-CCF mode.
Fix this by moving the scmi_generic_protocol_version() call before
the CLK_CCF check, ensuring the version is fetched for both CCF and
non-CCF platforms.
Tested on am62lx_evm.
Fixes: ae7e0330ce22 ("clk: scmi: add compatibility with clock protocol 2.0")
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
* Some consistency cleanups of recently added Genio boards (510/700/1200).
* Some pinctrl improvements to support newer MediaTek SOCs (mt8189 compatible).
* New devicetree and config for Genio 520/720 EVK boards (can boot to eMMC or SD).
* New CPU-specific functions to read vendor-specific CPU info at runtime.
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Merge tag 'mediatek-for-master-2026-04-07' of https://source.denx.de/u-boot/custodians/u-boot-mediatek
This is the first wave of MediaTek changes for this merge window. We
also expect to be sending another decent-sized pull request later for
the backlog of patches that are currently waiting on dependencies or
need little more time for review.
* Fixes for cargo-culted issues in mach-mediatek init.c files.
* Some consistency cleanups of recently added Genio boards (510/700/1200).
* Some pinctrl improvements to support newer MediaTek SOCs (mt8189 compatible).
* New devicetree and config for Genio 520/720 EVK boards (can boot to eMMC or SD).
* New CPU-specific functions to read vendor-specific CPU info at runtime.
The U_BOOT_DRIVER macro creates a list of drivers used at link time, and
all entries here must be unique. This in turn means that all entries in
the code should also be unique in order to not lead to build failures
later with unexpected build combinations. Typically, the problem we have
here is when a driver is obviously based on another driver and didn't
update this particular field and so while the name field reflects
something unique the linker entry itself is not. In a few places this
provides a more suitable string name as well, however.
Reviewed-by: Marek Vasut <marek.vasut+usb@mailbox.org>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com> # Tegra
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Heiko Schocher <hs@nabladev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
In order to build SANDBOX_CLK_CCF we need for CLK_CCF to be enabled, add
that as a select similar to other drivers.
Signed-off-by: Tom Rini <trini@konsulko.com>
As exposed by "make randconfig", we have an issue with the dependencies
for REGMAP (and xPL variants). As this is a library function, it should
always be selected and not depended on by other functionality. This is
largely done correctly today, so just correct the few outliers.
Acked-by: Anshul Dalal <anshuld@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Replace all uses of CLK_XTAL with CLK_PAD_CLK26M.
This avoids declaring the same parent clock two different ways and will
eventually let us remove CLK_PARENT_XTAL completely.
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-15-66175ca8f637@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Replace all uses of CLK_XTAL with CLK_PAD_CLK26M.
This avoids declaring the same parent clock two different ways and will
eventually let us remove CLK_PARENT_XTAL completely.
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-14-66175ca8f637@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Replace all uses of CLK_XTAL with CLK_PAD_CLK26M.
This avoids declaring the same parent clock two different ways and will
eventually let us remove CLK_PARENT_XTAL completely.
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-13-66175ca8f637@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Replace all uses of CLK_XTAL with CLK_PAD_CLK26M.
This avoids declaring the same parent clock two different ways and will
eventually let us remove CLK_PARENT_XTAL completely.
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-12-66175ca8f637@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Replace all uses of CLK_XTAL with CLK_PAD_CLK26M.
This avoids declaring the same parent clock two different ways and will
eventually let us remove CLK_PARENT_XTAL completely.
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-11-66175ca8f637@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Replace all uses of CLK_XTAL with CLK_PAD_CLK26M.
This avoids declaring the same parent clock two different ways and will
eventually let us remove CLK_PARENT_XTAL completely.
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-10-66175ca8f637@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Replace all uses of CLK_XTAL with CLK_PAD_CLK26M.
This avoids declaring the same parent clock two different ways and will
eventually let us remove CLK_PARENT_XTAL completely.
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-9-66175ca8f637@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Replace all uses of CLK_XTAL with CLK_PAD_CLK26M.
This avoids declaring the same parent clock two different ways and will
eventually let us remove CLK_PARENT_XTAL completely.
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-3-66175ca8f637@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Replace all uses of CLK_XTAL with CLK_PAD_CLK25M.
This avoids declaring the same parent clock two different ways and will
eventually let us remove CLK_PARENT_XTAL completely.
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-2-66175ca8f637@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Replace the hard-coded xtal rate for PLL parents with struct mtk_parent.
This avoids declaring the same clock rate in multiple places and will
allow future drivers to use an arbitrary clock.
The variable is renamed to something that better indicate what the field
is actually used for.
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-1-66175ca8f637@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Convert the mt8195 clock driver to use ext_clock_rates.
Now that we have the ext_clock_rates feature and also mux clock parents
have been converted to struct mtk_parent, we can remove the hack of
adding "missing" topckgen clocks. Instead we can use the proper parents.
The topckgen ID map is still needed though because the upstream
dt-bindings didn't use the conventional number ordering by clock type
for these.
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260309-clk-mtk-mt8188-drop-extra-top-clocks-v1-2-6ee4743a8465@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Convert the mt8188 clock driver to use ext_clock_rates.
Now that we have the ext_clock_rates feature and also mux clock parents
have been converted to struct mtk_parent, we can remove the hack of
adding "missing" topckgen clocks. Instead we can use the proper parents.
The topckgen ID map is still needed though because the upstream
dt-bindings didn't use the conventional number ordering by clock type
for these.
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260309-clk-mtk-mt8188-drop-extra-top-clocks-v1-1-6ee4743a8465@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Drop the clock ID map for MT8365 TOPCKGEN clocks.
Previously, we didn't have the EXT clock feature, so we needed the map.
Now we can replace it with the new feature to avoid the map.
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260303-mtk-clk-8365-drop-map-v1-1-17f81c375290@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Refactor two identical functions for getting mux clock rates. The
functions are renamed and moved to the section of the code that contains
other common functions.
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-16-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Remove CLK_PARENT_MIXED and all dead code paths related to it.
All mux clocks have been converted to use struct mtk_parent (the
parent_flags field of the parent/parent_flags union). Use of this
struct was indicated by CLK_PARENT_MIXED. Now, this is always the case
and we can drop the flag and the union. All MUX_MIXED* macros are
change to use the equivalent MUX* macros since we no longer need to
set the flag.
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-15-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Remove the CLK_BYPASS_XTAL flag completely.
It was a bit of a hack that was meant to handle mux clocks that had
mixed parents (e.g. XTAL and TOPCKGEN). The idea was that if you didn't
have CLK_XTAL as a parent, then you were supposed to add the
CLK_BYPASS_XTAL flag to the clock tree. There are likely a number of
drivers missing this since it is not intuitive.
In the meantime, we have introduced the CLK_PARENT_MIXED flag which
handles this more robustly. All of the affected drivers (the ones
without CLK_BYPASS_XTAL) have been updated to use CLK_PARENT_MIXED, so
the CLK_BYPASS_XTAL flag is no longer needed on other drivers.
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-14-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Convert all parent clock arrays to use struct mtk_parent. This will
allow us to simplify core code later by having only one possible data
type for mux parent arrays.
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-13-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Convert all parent clock arrays to use struct mtk_parent. This will
allow us to simplify core code later by having only one possible data
type for mux parent arrays.
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-12-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Convert all parent clock arrays to use struct mtk_parent. This will
allow us to simplify core code later by having only one possible data
type for mux parent arrays.
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-11-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Convert all parent clock arrays to use struct mtk_parent. This will
allow us to simplify core code later by having only one possible data
type for mux parent arrays.
Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-10-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Convert all parent clock arrays to use struct mtk_parent. This will
allow us to simplify core code later by having only one possible data
type for mux parent arrays.
Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-9-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Convert all parent clock arrays to use struct mtk_parent. This will
allow us to simplify core code later by having only one possible data
type for mux parent arrays.
Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-8-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Convert all parent clock arrays to use struct mtk_parent. This will
allow us to simplify core code later by having only one possible data
type for mux parent arrays.
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-7-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Convert all parent clock arrays to use struct mtk_parent. This will
allow us to simplify core code later by having only one possible data
type for mux parent arrays.
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-6-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
