clk: mediatek: remove use of CLK_BYPASS_XTAL flag

Remove the CLK_BYPASS_XTAL flag completely.

It was a bit of a hack that was meant to handle mux clocks that had
mixed parents (e.g. XTAL and TOPCKGEN). The idea was that if you didn't
have CLK_XTAL as a parent, then you were supposed to add the
CLK_BYPASS_XTAL flag to the clock tree. There are likely a number of
drivers missing this since it is not intuitive.

In the meantime, we have introduced the CLK_PARENT_MIXED flag which
handles this more robustly. All of the affected drivers (the ones
without CLK_BYPASS_XTAL) have been updated to use CLK_PARENT_MIXED, so
the CLK_BYPASS_XTAL flag is no longer needed on other drivers.

Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-14-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>

drivers/clk/mediatek/clk-mt7981.c

@@ -623,7 +623,7 @@ static const struct mtk_clk_tree mt7981_topckgen_clk_tree = {
 	.num_fclks = ARRAY_SIZE(top_fixed_clks),
 	.num_fdivs = ARRAY_SIZE(top_fixed_divs),
 	.num_muxes = ARRAY_SIZE(top_muxes),
-	.flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN,
+	.flags = CLK_PARENT_TOPCKGEN,
 };
 
 static const struct mtk_clk_tree mt7981_infracfg_clk_tree = {

drivers/clk/mediatek/clk-mt7986.c

@@ -530,7 +530,7 @@ static const struct mtk_clk_tree mt7986_topckgen_clk_tree = {
 	.num_fclks = ARRAY_SIZE(top_fixed_clks),
 	.num_fdivs = ARRAY_SIZE(top_fixed_divs),
 	.num_muxes = ARRAY_SIZE(top_muxes),
-	.flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN,
+	.flags = CLK_PARENT_TOPCKGEN,
 };
 
 static const struct mtk_clk_tree mt7986_infracfg_clk_tree = {

drivers/clk/mediatek/clk-mt7987.c

@@ -446,7 +446,7 @@ static const struct mtk_clk_tree mt7987_topckgen_clk_tree = {
 	.muxes = topckgen_mtk_muxes,
 	.num_fdivs = ARRAY_SIZE(topckgen_mtk_fixed_factors),
 	.num_muxes = ARRAY_SIZE(topckgen_mtk_muxes),
-	.flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN,
+	.flags = CLK_PARENT_TOPCKGEN,
 	.xtal_rate = MT7987_XTAL_RATE,
 };
 
@@ -772,7 +772,6 @@ static const struct mtk_clk_tree mt7987_infracfg_clk_tree = {
 	.gates = infracfg_mtk_gates,
 	.num_muxes = ARRAY_SIZE(infracfg_mtk_mux),
 	.num_gates = ARRAY_SIZE(infracfg_mtk_gates),
-	.flags = CLK_BYPASS_XTAL,
 	.xtal_rate = MT7987_XTAL_RATE,
 };
 

drivers/clk/mediatek/clk-mt7988.c

@@ -812,7 +812,7 @@ static const struct mtk_clk_tree mt7988_topckgen_clk_tree = {
 	.num_fclks = ARRAY_SIZE(topckgen_mtk_fixed_clks),
 	.num_fdivs = ARRAY_SIZE(topckgen_mtk_fixed_factors),
 	.num_muxes = ARRAY_SIZE(topckgen_mtk_muxes),
-	.flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN,
+	.flags = CLK_PARENT_TOPCKGEN,
 	.xtal_rate = 40 * MHZ,
 };
 
@@ -823,7 +823,6 @@ static const struct mtk_clk_tree mt7988_infracfg_clk_tree = {
 	.gates = infracfg_mtk_gates,
 	.num_muxes = ARRAY_SIZE(infracfg_mtk_mux),
 	.num_gates = ARRAY_SIZE(infracfg_mtk_gates),
-	.flags = CLK_BYPASS_XTAL,
 	.xtal_rate = 40 * MHZ,
 };
 

drivers/clk/mediatek/clk-mtk.c

@@ -735,10 +735,6 @@ static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off)
 		return mtk_find_parent_rate(priv, clk, parent->id, parent->flags);
 	}
 
-	if (mux->parent[index] == CLK_XTAL &&
-	    !(priv->tree->flags & CLK_BYPASS_XTAL))
-		return priv->tree->xtal_rate;
-
 	return mtk_find_parent_rate(priv, clk, mux->parent[index], mux->flags);
 }
 
@@ -1005,10 +1001,6 @@ static ulong mtk_infrasys_get_mux_rate(struct clk *clk, u32 off)
 		return mtk_find_parent_rate(priv, clk, parent->id, parent->flags);
 	}
 
-	if (mux->parent[index] == CLK_XTAL &&
-	    !(priv->tree->flags & CLK_BYPASS_XTAL))
-		return priv->tree->xtal_rate;
-
 	return mtk_find_parent_rate(priv, clk, mux->parent[index], mux->flags);
 }
 

drivers/clk/mediatek/clk-mtk.h

@@ -13,13 +13,6 @@
 
 /* flags in struct mtk_clk_tree */
 
-/* clk id == 0 doesn't mean it's xtal clk
- * This doesn't apply when CLK_PARENT_MIXED is defined.
- * With CLK_PARENT_MIXED declare CLK_PARENT_XTAL for the
- * relevant parent.
- */
-#define CLK_BYPASS_XTAL			BIT(0)
-
 #define CLK_PLL_HAVE_RST_BAR		BIT(0)
 
 #define CLK_MUX_DOMAIN_SCPSYS		BIT(0)