Merge branch '2022-02-10-platform-updates'

- Assorted Apple M1 platform updates
- Drop CONFIG_SYS_RESET_ADDR, update k3-am64-sk memory values in dts
This commit is contained in:
Tom Rini 2022-02-10 17:38:04 -05:00
commit fe203a05fb
172 changed files with 1592 additions and 249 deletions

View File

@ -931,7 +931,10 @@ config ARCH_APPLE
select DM
select DM_GPIO
select DM_KEYBOARD
select DM_MAILBOX
select DM_RESET
select DM_SERIAL
select DM_SPI
select DM_USB
select DM_VIDEO
select IOMMU
@ -941,6 +944,7 @@ config ARCH_APPLE
select POSITION_INDEPENDENT
select POWER_DOMAIN
select REGMAP
select SPI
select SYSCON
select SYSRESET
select SYSRESET_WATCHDOG

View File

@ -2,8 +2,8 @@
/*
* Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
* This file was generated with the
* AM64x SysConfig DDR Subsystem Register Configuration Tool v0.06.00
* Mon Apr 26 2021 20:47:47 GMT-0500 (Central Daylight Time)
* AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.00
* Wed Oct 13 2021 10:08:29 GMT-0500 (Central Daylight Time)
* DDR Type: LPDDR4
* F0 = 50MHz F1 = 666.7MHz F2 = 666.7MHz
* Density (per channel): 16Gb
@ -268,8 +268,8 @@
#define DDRSS_CTL_251_DATA 0x00000000
#define DDRSS_CTL_252_DATA 0x00000000
#define DDRSS_CTL_253_DATA 0x00000000
#define DDRSS_CTL_254_DATA 0x66006666
#define DDRSS_CTL_255_DATA 0x00002766
#define DDRSS_CTL_254_DATA 0x46004646
#define DDRSS_CTL_255_DATA 0x00002746
#define DDRSS_CTL_256_DATA 0x00000027
#define DDRSS_CTL_257_DATA 0x00000027
#define DDRSS_CTL_258_DATA 0x00000027
@ -660,13 +660,13 @@
#define DDRSS_PI_220_DATA 0x000000A7
#define DDRSS_PI_221_DATA 0x00001900
#define DDRSS_PI_222_DATA 0x32000056
#define DDRSS_PI_223_DATA 0x06000301
#define DDRSS_PI_223_DATA 0x06000101
#define DDRSS_PI_224_DATA 0x001D0204
#define DDRSS_PI_225_DATA 0x32120059
#define DDRSS_PI_226_DATA 0x05000301
#define DDRSS_PI_226_DATA 0x05000101
#define DDRSS_PI_227_DATA 0x001D0409
#define DDRSS_PI_228_DATA 0x32120059
#define DDRSS_PI_229_DATA 0x05000301
#define DDRSS_PI_229_DATA 0x05000101
#define DDRSS_PI_230_DATA 0x00000409
#define DDRSS_PI_231_DATA 0x05030900
#define DDRSS_PI_232_DATA 0x00040900
@ -748,7 +748,7 @@
#define DDRSS_PI_308_DATA 0x00000031
#define DDRSS_PI_309_DATA 0x00000000
#define DDRSS_PI_310_DATA 0x00000000
#define DDRSS_PI_311_DATA 0x66000000
#define DDRSS_PI_311_DATA 0x46000000
#define DDRSS_PI_312_DATA 0x00150F27
#define DDRSS_PI_313_DATA 0x00000000
#define DDRSS_PI_314_DATA 0x00000024
@ -756,7 +756,7 @@
#define DDRSS_PI_316_DATA 0x00000031
#define DDRSS_PI_317_DATA 0x00000000
#define DDRSS_PI_318_DATA 0x00000000
#define DDRSS_PI_319_DATA 0x66000000
#define DDRSS_PI_319_DATA 0x46000000
#define DDRSS_PI_320_DATA 0x00150F27
#define DDRSS_PI_321_DATA 0x00000000
#define DDRSS_PI_322_DATA 0x00000004
@ -772,7 +772,7 @@
#define DDRSS_PI_332_DATA 0x00000031
#define DDRSS_PI_333_DATA 0x00000000
#define DDRSS_PI_334_DATA 0x00000000
#define DDRSS_PI_335_DATA 0x66000000
#define DDRSS_PI_335_DATA 0x46000000
#define DDRSS_PI_336_DATA 0x00150F27
#define DDRSS_PI_337_DATA 0x00000000
#define DDRSS_PI_338_DATA 0x00000024
@ -780,7 +780,7 @@
#define DDRSS_PI_340_DATA 0x00000031
#define DDRSS_PI_341_DATA 0x00000000
#define DDRSS_PI_342_DATA 0x00000000
#define DDRSS_PI_343_DATA 0x66000000
#define DDRSS_PI_343_DATA 0x46000000
#define DDRSS_PI_344_DATA 0x00150F27
#define DDRSS_PHY_0_DATA 0x04F00000
#define DDRSS_PHY_1_DATA 0x00000000
@ -873,7 +873,7 @@
#define DDRSS_PHY_88_DATA 0x51516041
#define DDRSS_PHY_89_DATA 0x31C06000
#define DDRSS_PHY_90_DATA 0x07AB0340
#define DDRSS_PHY_91_DATA 0x0100C0C0
#define DDRSS_PHY_91_DATA 0x0000C0C0
#define DDRSS_PHY_92_DATA 0x03040000
#define DDRSS_PHY_93_DATA 0x00000403
#define DDRSS_PHY_94_DATA 0x42100010
@ -1129,7 +1129,7 @@
#define DDRSS_PHY_344_DATA 0x51516041
#define DDRSS_PHY_345_DATA 0x31C06000
#define DDRSS_PHY_346_DATA 0x07AB0340
#define DDRSS_PHY_347_DATA 0x0100C0C0
#define DDRSS_PHY_347_DATA 0x0000C0C0
#define DDRSS_PHY_348_DATA 0x03040000
#define DDRSS_PHY_349_DATA 0x00000403
#define DDRSS_PHY_350_DATA 0x42100010
@ -2157,7 +2157,7 @@
#define DDRSS_PHY_1372_DATA 0x00000002
#define DDRSS_PHY_1373_DATA 0x00000000
#define DDRSS_PHY_1374_DATA 0x00001142
#define DDRSS_PHY_1375_DATA 0x030207AB
#define DDRSS_PHY_1375_DATA 0x03020000
#define DDRSS_PHY_1376_DATA 0x00000080
#define DDRSS_PHY_1377_DATA 0x03900390
#define DDRSS_PHY_1378_DATA 0x03900390

View File

@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2021 Mark Kettenis <kettenis@openbsd.org>
*/
#define APPLE_RTKIT_PWR_STATE_SLEEP 0x01
#define APPLE_RTKIT_PWR_STATE_QUIESCED 0x10
#define APPLE_RTKIT_PWR_STATE_ON 0x20
int apple_rtkit_init(struct mbox_chan *);
int apple_rtkit_shutdown(struct mbox_chan *, int);

View File

@ -7,7 +7,7 @@ config SYS_CONFIG_NAME
default "apple"
config SYS_SOC
default "m1"
default "apple"
config SYS_MALLOC_LEN
default 0x4000000

View File

@ -2,3 +2,4 @@
obj-y += board.o
obj-y += lowlevel_init.o
obj-y += rtkit.o

231
arch/arm/mach-apple/rtkit.c Normal file
View File

@ -0,0 +1,231 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2021 Mark Kettenis <kettenis@openbsd.org>
* (C) Copyright 2021 Copyright The Asahi Linux Contributors
*/
#include <common.h>
#include <mailbox.h>
#include <malloc.h>
#include <asm/arch/rtkit.h>
#include <linux/apple-mailbox.h>
#include <linux/bitfield.h>
#define APPLE_RTKIT_EP_MGMT 0
#define APPLE_RTKIT_EP_CRASHLOG 1
#define APPLE_RTKIT_EP_SYSLOG 2
#define APPLE_RTKIT_EP_DEBUG 3
#define APPLE_RTKIT_EP_IOREPORT 4
/* Messages for management endpoint. */
#define APPLE_RTKIT_MGMT_TYPE GENMASK(59, 52)
#define APPLE_RTKIT_MGMT_PWR_STATE GENMASK(15, 0)
#define APPLE_RTKIT_MGMT_HELLO 1
#define APPLE_RTKIT_MGMT_HELLO_REPLY 2
#define APPLE_RTKIT_MGMT_HELLO_MINVER GENMASK(15, 0)
#define APPLE_RTKIT_MGMT_HELLO_MAXVER GENMASK(31, 16)
#define APPLE_RTKIT_MGMT_STARTEP 5
#define APPLE_RTKIT_MGMT_STARTEP_EP GENMASK(39, 32)
#define APPLE_RTKIT_MGMT_STARTEP_FLAG BIT(1)
#define APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE 6
#define APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE_ACK 7
#define APPLE_RTKIT_MGMT_EPMAP 8
#define APPLE_RTKIT_MGMT_EPMAP_LAST BIT(51)
#define APPLE_RTKIT_MGMT_EPMAP_BASE GENMASK(34, 32)
#define APPLE_RTKIT_MGMT_EPMAP_BITMAP GENMASK(31, 0)
#define APPLE_RTKIT_MGMT_EPMAP_REPLY 8
#define APPLE_RTKIT_MGMT_EPMAP_REPLY_MORE BIT(0)
#define APPLE_RTKIT_MIN_SUPPORTED_VERSION 11
#define APPLE_RTKIT_MAX_SUPPORTED_VERSION 12
/* Messages for internal endpoints. */
#define APPLE_RTKIT_BUFFER_REQUEST 1
#define APPLE_RTKIT_BUFFER_REQUEST_SIZE GENMASK(51, 44)
#define APPLE_RTKIT_BUFFER_REQUEST_IOVA GENMASK(41, 0)
int apple_rtkit_init(struct mbox_chan *chan)
{
struct apple_mbox_msg msg;
int endpoints[256];
int nendpoints = 0;
int endpoint;
int min_ver, max_ver, want_ver;
int msgtype, pwrstate;
u64 reply;
u32 bitmap, base;
int i, ret;
/* Wakup the IOP. */
msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE) |
FIELD_PREP(APPLE_RTKIT_MGMT_PWR_STATE, APPLE_RTKIT_PWR_STATE_ON);
msg.msg1 = APPLE_RTKIT_EP_MGMT;
ret = mbox_send(chan, &msg);
if (ret < 0)
return ret;
/* Wait for protocol version negotiation message. */
ret = mbox_recv(chan, &msg, 10000);
if (ret < 0)
return ret;
endpoint = msg.msg1;
msgtype = FIELD_GET(APPLE_RTKIT_MGMT_TYPE, msg.msg0);
if (endpoint != APPLE_RTKIT_EP_MGMT) {
printf("%s: unexpected endpoint %d\n", __func__, endpoint);
return -EINVAL;
}
if (msgtype != APPLE_RTKIT_MGMT_HELLO) {
printf("%s: unexpected message type %d\n", __func__, msgtype);
return -EINVAL;
}
min_ver = FIELD_GET(APPLE_RTKIT_MGMT_HELLO_MINVER, msg.msg0);
max_ver = FIELD_GET(APPLE_RTKIT_MGMT_HELLO_MAXVER, msg.msg0);
want_ver = min(APPLE_RTKIT_MAX_SUPPORTED_VERSION, max_ver);
if (min_ver > APPLE_RTKIT_MAX_SUPPORTED_VERSION) {
printf("%s: firmware min version %d is too new\n",
__func__, min_ver);
return -ENOTSUPP;
}
if (max_ver < APPLE_RTKIT_MIN_SUPPORTED_VERSION) {
printf("%s: firmware max version %d is too old\n",
__func__, max_ver);
return -ENOTSUPP;
}
/* Ack version. */
msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_HELLO_REPLY) |
FIELD_PREP(APPLE_RTKIT_MGMT_HELLO_MINVER, want_ver) |
FIELD_PREP(APPLE_RTKIT_MGMT_HELLO_MAXVER, want_ver);
msg.msg1 = APPLE_RTKIT_EP_MGMT;
ret = mbox_send(chan, &msg);
if (ret < 0)
return ret;
wait_epmap:
/* Wait for endpoint map message. */
ret = mbox_recv(chan, &msg, 10000);
if (ret < 0)
return ret;
endpoint = msg.msg1;
msgtype = FIELD_GET(APPLE_RTKIT_MGMT_TYPE, msg.msg0);
if (endpoint != APPLE_RTKIT_EP_MGMT) {
printf("%s: unexpected endpoint %d\n", __func__, endpoint);
return -EINVAL;
}
if (msgtype != APPLE_RTKIT_MGMT_EPMAP) {
printf("%s: unexpected message type %d\n", __func__, msgtype);
return -EINVAL;
}
bitmap = FIELD_GET(APPLE_RTKIT_MGMT_EPMAP_BITMAP, msg.msg0);
base = FIELD_GET(APPLE_RTKIT_MGMT_EPMAP_BASE, msg.msg0);
for (i = 0; i < 32; i++) {
if (bitmap & (1U << i))
endpoints[nendpoints++] = base * 32 + i;
}
/* Ack endpoint map. */
reply = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_EPMAP_REPLY) |
FIELD_PREP(APPLE_RTKIT_MGMT_EPMAP_BASE, base);
if (msg.msg0 & APPLE_RTKIT_MGMT_EPMAP_LAST)
reply |= APPLE_RTKIT_MGMT_EPMAP_LAST;
else
reply |= APPLE_RTKIT_MGMT_EPMAP_REPLY_MORE;
msg.msg0 = reply;
msg.msg1 = APPLE_RTKIT_EP_MGMT;
ret = mbox_send(chan, &msg);
if (ret < 0)
return ret;
if (reply & APPLE_RTKIT_MGMT_EPMAP_REPLY_MORE)
goto wait_epmap;
for (i = 0; i < nendpoints; i++) {
/* Don't start the syslog endpoint since we can't
easily handle its messages in U-Boot. */
if (endpoints[i] == APPLE_RTKIT_EP_SYSLOG)
continue;
/* Request endpoint. */
msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_STARTEP) |
FIELD_PREP(APPLE_RTKIT_MGMT_STARTEP_EP, endpoints[i]) |
APPLE_RTKIT_MGMT_STARTEP_FLAG;
msg.msg1 = APPLE_RTKIT_EP_MGMT;
ret = mbox_send(chan, &msg);
if (ret < 0)
return ret;
}
pwrstate = APPLE_RTKIT_PWR_STATE_SLEEP;
while (pwrstate != APPLE_RTKIT_PWR_STATE_ON) {
ret = mbox_recv(chan, &msg, 100000);
if (ret < 0)
return ret;
endpoint = msg.msg1;
msgtype = FIELD_GET(APPLE_RTKIT_MGMT_TYPE, msg.msg0);
if (endpoint == APPLE_RTKIT_EP_CRASHLOG ||
endpoint == APPLE_RTKIT_EP_SYSLOG ||
endpoint == APPLE_RTKIT_EP_IOREPORT) {
u64 addr = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_IOVA, msg.msg0);
u64 size = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_SIZE, msg.msg0);
if (msgtype == APPLE_RTKIT_BUFFER_REQUEST && addr != 0)
continue;
msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_BUFFER_REQUEST) |
FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_SIZE, size) |
FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_IOVA, addr);
msg.msg1 = endpoint;
ret = mbox_send(chan, &msg);
if (ret < 0)
return ret;
continue;
}
if (endpoint != APPLE_RTKIT_EP_MGMT) {
printf("%s: unexpected endpoint %d\n", __func__, endpoint);
return -EINVAL;
}
if (msgtype != APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE_ACK) {
printf("%s: unexpected message type %d\n", __func__, msgtype);
return -EINVAL;
}
pwrstate = FIELD_GET(APPLE_RTKIT_MGMT_PWR_STATE, msg.msg0);
}
return 0;
}
int apple_rtkit_shutdown(struct mbox_chan *chan, int pwrstate)
{
struct apple_mbox_msg msg;
int ret;
msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE) |
FIELD_PREP(APPLE_RTKIT_MGMT_PWR_STATE, pwrstate);
msg.msg1 = APPLE_RTKIT_EP_MGMT;
ret = mbox_send(chan, &msg);
if (ret < 0)
return ret;
ret = mbox_recv(chan, &msg, 100000);
if (ret < 0)
return ret;
return 0;
}

View File

@ -215,19 +215,12 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
/*
* Trying to execute the next instruction at a non-existing address
* should cause a machine check, resulting in reset
*/
#ifdef CONFIG_SYS_RESET_ADDRESS
addr = CONFIG_SYS_RESET_ADDRESS;
#else
/*
*
* note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
* CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid address.
* Better pick an address known to be invalid on your system and assign
* it to CONFIG_SYS_RESET_ADDRESS.
* "(ulong)-1" used to be a good choice for many systems...
*/
addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong);
#endif
((void (*)(void)) addr)();
return 1;
}

View File

@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_APPLE=y
CONFIG_DEFAULT_DEVICE_TREE="t8103-j274"
CONFIG_DEBUG_UART_BASE=0x235200000
CONFIG_DEBUG_UART_CLOCK=240000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x880000000
CONFIG_USE_PREBOOT=y
@ -11,8 +11,10 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_NET is not set
# CONFIG_MMC is not set
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_NVME_APPLE=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_KEYBOARD=y
CONFIG_APPLE_SPI_KEYB=y
CONFIG_VIDEO_SIMPLE=y
# CONFIG_GENERATE_SMBIOS_TABLE is not set

View File

@ -56,7 +56,7 @@ CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MVPP2=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_DW_MVEBU=y
CONFIG_PHY=y

View File

@ -41,7 +41,7 @@ CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y

View File

@ -62,7 +62,7 @@ CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_DW_MESON=y
CONFIG_MESON_G12A_USB_PHY=y

View File

@ -60,7 +60,7 @@ CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_DW_MESON=y
CONFIG_MESON_G12A_USB_PHY=y

View File

@ -48,7 +48,7 @@ CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_DW_MESON=y
CONFIG_MESON_G12A_USB_PHY=y

View File

@ -62,7 +62,7 @@ CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_DW_MESON=y
CONFIG_MESON_G12A_USB_PHY=y

View File

@ -60,7 +60,7 @@ CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_DW_MESON=y
CONFIG_MESON_G12A_USB_PHY=y

View File

@ -48,7 +48,7 @@ CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_DW_MESON=y
CONFIG_MESON_G12A_USB_PHY=y

View File

@ -84,7 +84,7 @@ CONFIG_DM_DSA=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MSCC_FELIX_SWITCH=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_RTC_RV8803=y

View File

@ -50,7 +50,7 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y

View File

@ -50,7 +50,7 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y

View File

@ -50,7 +50,7 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y

View File

@ -54,7 +54,7 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y

View File

@ -50,7 +50,7 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y

View File

@ -54,7 +54,7 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y

View File

@ -72,7 +72,7 @@ CONFIG_SPI_FLASH_SST=y
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y

View File

@ -63,7 +63,7 @@ CONFIG_SPI_FLASH_SST=y
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y

View File

@ -73,7 +73,7 @@ CONFIG_SPI_FLASH_SST=y
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y

View File

@ -52,7 +52,7 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -57,7 +57,7 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y

View File

@ -54,7 +54,7 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y

View File

@ -56,7 +56,7 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y

View File

@ -54,7 +54,7 @@ CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -71,7 +71,7 @@ CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -76,7 +76,7 @@ CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -77,7 +77,7 @@ CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -99,7 +99,7 @@ CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -75,7 +75,7 @@ CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -77,7 +77,7 @@ CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -78,7 +78,7 @@ CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -68,7 +68,7 @@ CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -95,7 +95,7 @@ CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -85,7 +85,7 @@ CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -59,7 +59,7 @@ CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_SJA1105=y
CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SCSI_AHCI_PLAT=y

View File

@ -75,7 +75,7 @@ CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_SJA1105=y
CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SCSI_AHCI_PLAT=y

View File

@ -63,7 +63,7 @@ CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FW_ADDR=0x60940000

View File

@ -65,7 +65,7 @@ CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FW_ADDR=0x60940000

View File

@ -66,7 +66,7 @@ CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FW_ADDR=0x60940000

View File

@ -64,7 +64,7 @@ CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y

View File

@ -83,7 +83,7 @@ CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y

View File

@ -81,7 +81,7 @@ CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y

View File

@ -73,7 +73,7 @@ CONFIG_DM_DSA=y
CONFIG_E1000=y
CONFIG_MSCC_FELIX_SWITCH=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -79,7 +79,7 @@ CONFIG_DM_DSA=y
CONFIG_E1000=y
CONFIG_MSCC_FELIX_SWITCH=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -78,7 +78,7 @@ CONFIG_DM_MDIO_MUX=y
CONFIG_E1000=y
CONFIG_FSL_ENETC=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -68,7 +68,7 @@ CONFIG_DM_DSA=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MSCC_FELIX_SWITCH=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -74,7 +74,7 @@ CONFIG_DM_DSA=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MSCC_FELIX_SWITCH=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -81,7 +81,7 @@ CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x60900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -82,7 +82,7 @@ CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x60900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -102,7 +102,7 @@ CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -82,7 +82,7 @@ CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x60900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -76,7 +76,7 @@ CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x40900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -100,7 +100,7 @@ CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -93,7 +93,7 @@ CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -83,7 +83,7 @@ CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -92,7 +92,7 @@ CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -65,7 +65,7 @@ CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x60900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FW_ADDR=0x60940000

View File

@ -68,7 +68,7 @@ CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x60900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FW_ADDR=0x60940000

View File

@ -80,7 +80,7 @@ CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y

View File

@ -88,7 +88,7 @@ CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y

View File

@ -86,7 +86,7 @@ CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FW_ADDR=0x940000

View File

@ -66,7 +66,7 @@ CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FW_ADDR=0x940000

View File

@ -72,7 +72,7 @@ CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FW_ADDR=0x940000

View File

@ -60,7 +60,7 @@ CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -79,7 +79,7 @@ CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x60900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -82,7 +82,7 @@ CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x60900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -83,7 +83,7 @@ CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x60900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -102,7 +102,7 @@ CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -77,7 +77,7 @@ CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x40900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -102,7 +102,7 @@ CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -95,7 +95,7 @@ CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -83,7 +83,7 @@ CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -93,7 +93,7 @@ CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -85,7 +85,7 @@ CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y

View File

@ -68,7 +68,7 @@ CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x40900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y

View File

@ -72,7 +72,7 @@ CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x40900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y

View File

@ -90,7 +90,7 @@ CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x40900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y

View File

@ -84,7 +84,7 @@ CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y

View File

@ -64,7 +64,7 @@ CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y

View File

@ -70,7 +70,7 @@ CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y

View File

@ -81,7 +81,7 @@ CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -76,7 +76,7 @@ CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -79,7 +79,7 @@ CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -91,7 +91,7 @@ CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -89,7 +89,7 @@ CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

View File

@ -102,7 +102,7 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y

View File

@ -77,7 +77,7 @@ CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y

View File

@ -80,7 +80,7 @@ CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y

View File

@ -90,7 +90,7 @@ CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y

View File

@ -78,7 +78,7 @@ CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y

View File

@ -84,7 +84,7 @@ CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y

View File

@ -69,7 +69,7 @@ CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y

Some files were not shown because too many files have changed in this diff Show More