From 045474be5ebca9d4491572c134a8288b19f5e14a Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Sat, 22 Jan 2022 20:38:11 +0100 Subject: [PATCH 01/15] nvme: Split out PCI support Apple SoCs have an integrated NVMe controller that isn't connected over a PCIe bus. In preparation for adding support for this NVMe controller, split out the PCI support into its own file. This file is selected through a new CONFIG_NVME_PCI Kconfig option, so do a wholesale replacement of CONFIG_NVME with CONFIG_NVME_PCI. Signed-off-by: Mark Kettenis Reviewed-by: Simon Glass Tested on: Macbook Air M1 Tested-by: Simon Glass --- configs/clearfog_gt_8k_defconfig | 2 +- configs/firefly-rk3399_defconfig | 2 +- configs/khadas-vim3_android_ab_defconfig | 2 +- configs/khadas-vim3_android_defconfig | 2 +- configs/khadas-vim3_defconfig | 2 +- configs/khadas-vim3l_android_ab_defconfig | 2 +- configs/khadas-vim3l_android_defconfig | 2 +- configs/khadas-vim3l_defconfig | 2 +- configs/kontron_sl28_defconfig | 2 +- configs/ls1012afrdm_qspi_defconfig | 2 +- configs/ls1012afrdm_tfa_defconfig | 2 +- .../ls1012afrwy_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1012afrwy_qspi_defconfig | 2 +- configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1012afrwy_tfa_defconfig | 2 +- configs/ls1012aqds_qspi_defconfig | 2 +- configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1012aqds_tfa_defconfig | 2 +- configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1012ardb_qspi_defconfig | 2 +- configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1012ardb_tfa_defconfig | 2 +- configs/ls1021aiot_qspi_defconfig | 2 +- configs/ls1021aiot_sdcard_defconfig | 2 +- configs/ls1021aqds_ddr4_nor_defconfig | 2 +- configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 2 +- configs/ls1021aqds_nand_defconfig | 2 +- configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 2 +- configs/ls1021aqds_nor_defconfig | 2 +- configs/ls1021aqds_nor_lpuart_defconfig | 2 +- configs/ls1021aqds_qspi_defconfig | 2 +- configs/ls1021aqds_sdcard_ifc_defconfig | 2 +- configs/ls1021aqds_sdcard_qspi_defconfig | 2 +- configs/ls1021atsn_qspi_defconfig | 2 +- configs/ls1021atsn_sdcard_defconfig | 2 +- configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 2 +- configs/ls1021atwr_nor_defconfig | 2 +- configs/ls1021atwr_nor_lpuart_defconfig | 2 +- configs/ls1021atwr_qspi_defconfig | 2 +- configs/ls1021atwr_sdcard_ifc_defconfig | 2 +- configs/ls1021atwr_sdcard_qspi_defconfig | 2 +- configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1028aqds_tfa_defconfig | 2 +- configs/ls1028aqds_tfa_lpuart_defconfig | 2 +- configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1028ardb_tfa_defconfig | 2 +- configs/ls1043aqds_defconfig | 2 +- configs/ls1043aqds_lpuart_defconfig | 2 +- configs/ls1043aqds_nand_defconfig | 2 +- configs/ls1043aqds_nor_ddr3_defconfig | 2 +- configs/ls1043aqds_qspi_defconfig | 2 +- configs/ls1043aqds_sdcard_ifc_defconfig | 2 +- configs/ls1043aqds_sdcard_qspi_defconfig | 2 +- configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1043aqds_tfa_defconfig | 2 +- configs/ls1043ardb_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_defconfig | 2 +- configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_nand_defconfig | 2 +- configs/ls1043ardb_sdcard_defconfig | 2 +- configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_tfa_defconfig | 2 +- configs/ls1046afrwy_tfa_defconfig | 2 +- configs/ls1046aqds_SECURE_BOOT_defconfig | 2 +- configs/ls1046aqds_defconfig | 2 +- configs/ls1046aqds_lpuart_defconfig | 2 +- configs/ls1046aqds_nand_defconfig | 2 +- configs/ls1046aqds_qspi_defconfig | 2 +- configs/ls1046aqds_sdcard_ifc_defconfig | 2 +- configs/ls1046aqds_sdcard_qspi_defconfig | 2 +- configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1046aqds_tfa_defconfig | 2 +- configs/ls1046ardb_emmc_defconfig | 2 +- configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1046ardb_qspi_defconfig | 2 +- configs/ls1046ardb_qspi_spl_defconfig | 2 +- configs/ls1046ardb_sdcard_defconfig | 2 +- configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1046ardb_tfa_defconfig | 2 +- configs/ls1088aqds_defconfig | 2 +- configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1088aqds_qspi_defconfig | 2 +- configs/ls1088aqds_sdcard_ifc_defconfig | 2 +- configs/ls1088aqds_sdcard_qspi_defconfig | 2 +- configs/ls1088aqds_tfa_defconfig | 2 +- configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1088ardb_qspi_defconfig | 2 +- configs/ls1088ardb_sdcard_qspi_defconfig | 2 +- configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1088ardb_tfa_defconfig | 2 +- configs/ls2080aqds_SECURE_BOOT_defconfig | 2 +- configs/ls2080aqds_defconfig | 2 +- configs/ls2080aqds_nand_defconfig | 2 +- configs/ls2080aqds_qspi_defconfig | 2 +- configs/ls2080aqds_sdcard_defconfig | 2 +- configs/ls2080ardb_SECURE_BOOT_defconfig | 2 +- configs/ls2080ardb_defconfig | 2 +- configs/ls2080ardb_nand_defconfig | 2 +- configs/ls2081ardb_defconfig | 2 +- configs/ls2088aqds_tfa_defconfig | 2 +- configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls2088ardb_qspi_defconfig | 2 +- configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls2088ardb_tfa_defconfig | 2 +- configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/lx2160aqds_tfa_defconfig | 2 +- configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/lx2160ardb_tfa_defconfig | 2 +- configs/lx2160ardb_tfa_stmm_defconfig | 2 +- configs/mvebu_crb_cn9130_defconfig | 2 +- configs/mvebu_db_armada8k_defconfig | 2 +- configs/mvebu_db_cn9130_defconfig | 2 +- configs/mvebu_espressobin-88f3720_defconfig | 2 +- configs/mvebu_mcbin-88f8040_defconfig | 2 +- configs/mvebu_puzzle-m801-88f8040_defconfig | 2 +- configs/nanopc-t4-rk3399_defconfig | 2 +- configs/octeontx2_96xx_defconfig | 2 +- configs/octeontx_81xx_defconfig | 2 +- configs/octeontx_83xx_defconfig | 2 +- configs/p3450-0000_defconfig | 2 +- configs/pinebook-pro-rk3399_defconfig | 2 +- configs/qemu-x86_64_defconfig | 2 +- configs/qemu-x86_defconfig | 2 +- configs/qemu_arm64_defconfig | 2 +- configs/qemu_arm_defconfig | 2 +- configs/rcar3_salvator-x_defconfig | 2 +- configs/roc-pc-mezzanine-rk3399_defconfig | 2 +- configs/rock-pi-4-rk3399_defconfig | 2 +- configs/rock-pi-4c-rk3399_defconfig | 2 +- configs/rock-pi-n10-rk3399pro_defconfig | 2 +- configs/rock960-rk3399_defconfig | 2 +- configs/rockpro64-rk3399_defconfig | 2 +- configs/sandbox64_defconfig | 2 +- configs/sandbox_defconfig | 2 +- configs/sandbox_flattree_defconfig | 2 +- configs/sandbox_noinst_defconfig | 2 +- configs/sandbox_spl_defconfig | 2 +- configs/sifive_unmatched_defconfig | 2 +- configs/synquacer_developerbox_defconfig | 2 +- configs/turris_mox_defconfig | 2 +- configs/turris_omnia_defconfig | 2 +- doc/develop/driver-model/nvme.rst | 1 + drivers/nvme/Kconfig | 10 +++- drivers/nvme/Makefile | 1 + drivers/nvme/nvme.c | 38 ++------------ drivers/nvme/nvme.h | 3 ++ drivers/nvme/nvme_pci.c | 49 +++++++++++++++++++ 147 files changed, 207 insertions(+), 177 deletions(-) create mode 100644 drivers/nvme/nvme_pci.c diff --git a/configs/clearfog_gt_8k_defconfig b/configs/clearfog_gt_8k_defconfig index 6e344c9ce33..6dcd70fe12f 100644 --- a/configs/clearfog_gt_8k_defconfig +++ b/configs/clearfog_gt_8k_defconfig @@ -56,7 +56,7 @@ CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MVPP2=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_MVEBU=y CONFIG_PHY=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index d576b5c38d9..fe1c019f1db 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -41,7 +41,7 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y diff --git a/configs/khadas-vim3_android_ab_defconfig b/configs/khadas-vim3_android_ab_defconfig index 34f352f2d86..45cefd85e0a 100644 --- a/configs/khadas-vim3_android_ab_defconfig +++ b/configs/khadas-vim3_android_ab_defconfig @@ -62,7 +62,7 @@ CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MDIO_MUX_MESON_G12A=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_MESON=y CONFIG_MESON_G12A_USB_PHY=y diff --git a/configs/khadas-vim3_android_defconfig b/configs/khadas-vim3_android_defconfig index a6940054121..0c3fd6ddb38 100644 --- a/configs/khadas-vim3_android_defconfig +++ b/configs/khadas-vim3_android_defconfig @@ -60,7 +60,7 @@ CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MDIO_MUX_MESON_G12A=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_MESON=y CONFIG_MESON_G12A_USB_PHY=y diff --git a/configs/khadas-vim3_defconfig b/configs/khadas-vim3_defconfig index 5d17cd18dae..f85e2eebe78 100644 --- a/configs/khadas-vim3_defconfig +++ b/configs/khadas-vim3_defconfig @@ -48,7 +48,7 @@ CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MDIO_MUX_MESON_G12A=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_MESON=y CONFIG_MESON_G12A_USB_PHY=y diff --git a/configs/khadas-vim3l_android_ab_defconfig b/configs/khadas-vim3l_android_ab_defconfig index 4d22db224e7..b2bdf969227 100644 --- a/configs/khadas-vim3l_android_ab_defconfig +++ b/configs/khadas-vim3l_android_ab_defconfig @@ -62,7 +62,7 @@ CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MDIO_MUX_MESON_G12A=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_MESON=y CONFIG_MESON_G12A_USB_PHY=y diff --git a/configs/khadas-vim3l_android_defconfig b/configs/khadas-vim3l_android_defconfig index e3763666d79..085919b9741 100644 --- a/configs/khadas-vim3l_android_defconfig +++ b/configs/khadas-vim3l_android_defconfig @@ -60,7 +60,7 @@ CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MDIO_MUX_MESON_G12A=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_MESON=y CONFIG_MESON_G12A_USB_PHY=y diff --git a/configs/khadas-vim3l_defconfig b/configs/khadas-vim3l_defconfig index f76138f9104..c4162450254 100644 --- a/configs/khadas-vim3l_defconfig +++ b/configs/khadas-vim3l_defconfig @@ -48,7 +48,7 @@ CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MDIO_MUX_MESON_G12A=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_MESON=y CONFIG_MESON_G12A_USB_PHY=y diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index 520ab1baa06..b61276cf1dd 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -84,7 +84,7 @@ CONFIG_DM_DSA=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MSCC_FELIX_SWITCH=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCIE_ECAM_GENERIC=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_RV8803=y diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index ad3b7bff428..0b3964e9d8c 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -50,7 +50,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig index 3317a0592b0..93514082f22 100644 --- a/configs/ls1012afrdm_tfa_defconfig +++ b/configs/ls1012afrdm_tfa_defconfig @@ -50,7 +50,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index 6eaf0f5788b..f25c22e9265 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -50,7 +50,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig index facbb26f0df..343e38df08d 100644 --- a/configs/ls1012afrwy_qspi_defconfig +++ b/configs/ls1012afrwy_qspi_defconfig @@ -54,7 +54,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index 6e2118fda17..16bb10e6255 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -50,7 +50,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index 5370c321291..4ced1bfa5bb 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -54,7 +54,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index bac3f916100..91bfab0862c 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -72,7 +72,7 @@ CONFIG_SPI_FLASH_SST=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig index 476ebd04151..14eeade3056 100644 --- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -63,7 +63,7 @@ CONFIG_SPI_FLASH_SST=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig index 057c0475ae2..3531fa7b939 100644 --- a/configs/ls1012aqds_tfa_defconfig +++ b/configs/ls1012aqds_tfa_defconfig @@ -73,7 +73,7 @@ CONFIG_SPI_FLASH_SST=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index 771d69e17a7..227668912b3 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -52,7 +52,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index 83ba8ee5429..23370901a17 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -57,7 +57,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index 19550ea1b1f..bdd8c9a6ffc 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -54,7 +54,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index 3df6dd21a6b..94408c32b94 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -56,7 +56,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig index 5943fb6a484..911b4dba3a2 100644 --- a/configs/ls1021aiot_qspi_defconfig +++ b/configs/ls1021aiot_qspi_defconfig @@ -54,7 +54,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index e9e3ee9441b..f72f2b1bb50 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -71,7 +71,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index d587c35a430..925d68db8e1 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -76,7 +76,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index ebf724a409e..c71c8649d92 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -77,7 +77,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index d5a306e5c69..58629beb0c7 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -99,7 +99,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 3fcd53320fd..d252ed49e95 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -75,7 +75,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index dda02ae48ac..fb9f457b74d 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -77,7 +77,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index 188f125429b..1d6d88ff372 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -78,7 +78,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index 9dad311417b..f629080be23 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -68,7 +68,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 25afa72f218..38b17048c4f 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -95,7 +95,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index 3dd29121710..eb97c18fdd6 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -85,7 +85,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig index 42210602f9d..45b05adbb49 100644 --- a/configs/ls1021atsn_qspi_defconfig +++ b/configs/ls1021atsn_qspi_defconfig @@ -59,7 +59,7 @@ CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_SJA1105=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SCSI_AHCI_PLAT=y diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig index 627038cb6e7..7bc1963b2f3 100644 --- a/configs/ls1021atsn_sdcard_defconfig +++ b/configs/ls1021atsn_sdcard_defconfig @@ -75,7 +75,7 @@ CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_SJA1105=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SCSI_AHCI_PLAT=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 0c64cf08f32..2f66d833a31 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -63,7 +63,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index 39ba7bef26e..c1adc6e23fa 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -65,7 +65,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index de3183c8dd0..150179d6334 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -66,7 +66,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index 38f0731d220..016771a8f6d 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -64,7 +64,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index e43e2ba8c57..695505a9752 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -83,7 +83,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 429adf3e48e..19e7751e785 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -81,7 +81,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index bbb6f1aff61..af65bcad840 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -73,7 +73,7 @@ CONFIG_DM_DSA=y CONFIG_E1000=y CONFIG_MSCC_FELIX_SWITCH=y CONFIG_MDIO_MUX_I2CREG=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_ECAM_GENERIC=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index 2b90d8a0df4..bc473ae143d 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -79,7 +79,7 @@ CONFIG_DM_DSA=y CONFIG_E1000=y CONFIG_MSCC_FELIX_SWITCH=y CONFIG_MDIO_MUX_I2CREG=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_ECAM_GENERIC=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig b/configs/ls1028aqds_tfa_lpuart_defconfig index 84696fc13d1..417c8481241 100644 --- a/configs/ls1028aqds_tfa_lpuart_defconfig +++ b/configs/ls1028aqds_tfa_lpuart_defconfig @@ -78,7 +78,7 @@ CONFIG_DM_MDIO_MUX=y CONFIG_E1000=y CONFIG_FSL_ENETC=y CONFIG_MDIO_MUX_I2CREG=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_ECAM_GENERIC=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index 7fc8bec4341..8b5bb130f67 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -68,7 +68,7 @@ CONFIG_DM_DSA=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MSCC_FELIX_SWITCH=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_ECAM_GENERIC=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index 56535904eaa..2018d15a837 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -74,7 +74,7 @@ CONFIG_DM_DSA=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MSCC_FELIX_SWITCH=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_ECAM_GENERIC=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index 342dea5fcd2..ef1a591ec09 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -81,7 +81,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index dd8188a72b7..8dd6ce41d6c 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -82,7 +82,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index 6de0666ba51..3e548031071 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -102,7 +102,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index 60f9e16ca98..97fe2ce8bd6 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -82,7 +82,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index 9724cf96dfc..dd0a726502d 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -76,7 +76,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x40900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index aa5ae5e137c..be40f49f6e1 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -100,7 +100,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index ebbcd74a471..58204444043 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -93,7 +93,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index 15cb28ba95b..e196c4428f4 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -83,7 +83,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index 9bffcf7fe0c..6a897948850 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -92,7 +92,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index e2762cd0cf2..e7c277d6c62 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -65,7 +65,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index 8f3155bd69f..94daa1f10ba 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -68,7 +68,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index b3c1505f5e7..a86138f1798 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -80,7 +80,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index 17806758918..19a54d1ea2e 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -88,7 +88,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index 4977b4e2d23..ef82842b649 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -86,7 +86,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x940000 diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig index d8d65b813b0..6ff5614cb53 100644 --- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -66,7 +66,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x940000 diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig index b68c1252717..551807e879d 100644 --- a/configs/ls1043ardb_tfa_defconfig +++ b/configs/ls1043ardb_tfa_defconfig @@ -72,7 +72,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x940000 diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index a2ebe525edc..30daa5c6d0f 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -60,7 +60,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig index 8e19249f61c..c15302c753c 100644 --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_SECURE_BOOT_defconfig @@ -79,7 +79,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index f8b4faafc7b..bc326114cd1 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -82,7 +82,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig index 37b45ee0634..52855d12e51 100644 --- a/configs/ls1046aqds_lpuart_defconfig +++ b/configs/ls1046aqds_lpuart_defconfig @@ -83,7 +83,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index e0e736fa8bb..ab780c16221 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -102,7 +102,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index 99177d7638e..8111ce6432b 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -77,7 +77,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x40900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index 83c6c93ed9b..b5b501c9a95 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -102,7 +102,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index 291ca2ff746..01451930e6b 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -95,7 +95,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index 92f3b1797dc..740838baa10 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -83,7 +83,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 7ac94067374..11de0d40afa 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -93,7 +93,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index fe06a2e3285..a319bf39fc7 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -85,7 +85,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig index eb94ca3b983..92769655d58 100644 --- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig @@ -68,7 +68,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x40900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index 41e735da905..506b32c2487 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -72,7 +72,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x40900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig index 3b4a939c6be..87ab8ac4215 100644 --- a/configs/ls1046ardb_qspi_spl_defconfig +++ b/configs/ls1046ardb_qspi_spl_defconfig @@ -90,7 +90,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x40900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index eb43d79c121..033ccc24e69 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -84,7 +84,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig index 7e847c88f59..f841053fd8f 100644 --- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig @@ -64,7 +64,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig index 867acb24811..2a3f6cb3282 100644 --- a/configs/ls1046ardb_tfa_defconfig +++ b/configs/ls1046ardb_tfa_defconfig @@ -70,7 +70,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig index f51bc3d1230..094f11363f2 100644 --- a/configs/ls1088aqds_defconfig +++ b/configs/ls1088aqds_defconfig @@ -81,7 +81,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index 6f6206ba7fd..9b51ee98f30 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -76,7 +76,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index 68de77e238b..4187ff75641 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -79,7 +79,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig index ac0601a96d4..c594d783ed9 100644 --- a/configs/ls1088aqds_sdcard_ifc_defconfig +++ b/configs/ls1088aqds_sdcard_ifc_defconfig @@ -91,7 +91,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index 3a4f696dd82..1e83ab444be 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -89,7 +89,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index d4abdb3ff92..56b6da647cf 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -102,7 +102,7 @@ CONFIG_E1000=y CONFIG_MII=y CONFIG_MDIO_MUX_I2CREG=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index c4ae4b5a2de..f84a63bd296 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -77,7 +77,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index f3c0191213e..976d65bfbf2 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -80,7 +80,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index 566e1eb193b..a0c5d97ac5c 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -90,7 +90,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig index 53244a881d8..6f983fd753f 100644 --- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig @@ -78,7 +78,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index e2f975bb92b..4ba4507d344 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -84,7 +84,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index 45fe718596c..ace5820f33d 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -69,7 +69,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index b695f8a6f0d..d21a136c20e 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -72,7 +72,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 57622e6af69..82cd933103f 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -79,7 +79,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index fc0afefa7c7..0ac2b835e95 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -68,7 +68,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig index f24f0038a0f..42e0cb22c09 100644 --- a/configs/ls2080aqds_sdcard_defconfig +++ b/configs/ls2080aqds_sdcard_defconfig @@ -74,7 +74,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index 0e84f89ddfe..81cd8b44022 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -68,7 +68,7 @@ CONFIG_PHY_CORTINA=y CONFIG_CORTINA_FW_ADDR=0x580980000 CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index d350a3111c6..a7491ccb3a9 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -71,7 +71,7 @@ CONFIG_PHY_CORTINA=y CONFIG_CORTINA_FW_ADDR=0x580980000 CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index 41b6684a7f9..bc297e57ef8 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -80,7 +80,7 @@ CONFIG_PHY_CORTINA=y CONFIG_CORTINA_FW_ADDR=0x980000 CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig index 2a8a562f60e..a2a14194b63 100644 --- a/configs/ls2081ardb_defconfig +++ b/configs/ls2081ardb_defconfig @@ -64,7 +64,7 @@ CONFIG_PHY_CORTINA=y CONFIG_CORTINA_FW_ADDR=0x980000 CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index e247f498a3c..c8d7e670e37 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -90,7 +90,7 @@ CONFIG_E1000=y CONFIG_MII=y CONFIG_MDIO_MUX_I2CREG=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index e75fa0e541c..193990c2a39 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -67,7 +67,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index 788930086b4..ee8510914d6 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -74,7 +74,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index 032b133cc46..de37147aaec 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -79,7 +79,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index ffc3a7b2eff..f4902a12fe3 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -87,7 +87,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index d5b8168fe10..17e04c4d225 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -82,7 +82,7 @@ CONFIG_E1000=y CONFIG_MII=y CONFIG_MDIO_MUX_I2CREG=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_GEN4=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index b8addd592bc..f12ad8fac3a 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -89,7 +89,7 @@ CONFIG_E1000=y CONFIG_MII=y CONFIG_MDIO_MUX_I2CREG=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_GEN4=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index f53480cf7ad..52bd909b04f 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -74,7 +74,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_GEN4=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 8798f3e4a5b..3760fef4a84 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -83,7 +83,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_GEN4=y diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig index a46d44dc087..db5fda3060a 100644 --- a/configs/lx2160ardb_tfa_stmm_defconfig +++ b/configs/lx2160ardb_tfa_stmm_defconfig @@ -83,7 +83,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_GEN4=y diff --git a/configs/mvebu_crb_cn9130_defconfig b/configs/mvebu_crb_cn9130_defconfig index 039fd8b3dc3..f1215fa359e 100644 --- a/configs/mvebu_crb_cn9130_defconfig +++ b/configs/mvebu_crb_cn9130_defconfig @@ -62,7 +62,7 @@ CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MVPP2=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_MVEBU=y CONFIG_PHY=y diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig index e6168a76a62..622d687e5d5 100644 --- a/configs/mvebu_db_armada8k_defconfig +++ b/configs/mvebu_db_armada8k_defconfig @@ -51,7 +51,7 @@ CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MVPP2=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_MVEBU=y CONFIG_PHY=y diff --git a/configs/mvebu_db_cn9130_defconfig b/configs/mvebu_db_cn9130_defconfig index 42d7038c5a1..1789838691e 100644 --- a/configs/mvebu_db_cn9130_defconfig +++ b/configs/mvebu_db_cn9130_defconfig @@ -67,7 +67,7 @@ CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MVPP2=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_MVEBU=y CONFIG_PHY=y diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index ffe6518433c..4b8206a38f1 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -73,7 +73,7 @@ CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MVNETA=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_AARDVARK=y CONFIG_PHY=y diff --git a/configs/mvebu_mcbin-88f8040_defconfig b/configs/mvebu_mcbin-88f8040_defconfig index 2aa06f80a0e..f45ce91f6fa 100644 --- a/configs/mvebu_mcbin-88f8040_defconfig +++ b/configs/mvebu_mcbin-88f8040_defconfig @@ -56,7 +56,7 @@ CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MVPP2=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_MVEBU=y CONFIG_PHY=y diff --git a/configs/mvebu_puzzle-m801-88f8040_defconfig b/configs/mvebu_puzzle-m801-88f8040_defconfig index 053b2f4c964..af01e6176a4 100644 --- a/configs/mvebu_puzzle-m801-88f8040_defconfig +++ b/configs/mvebu_puzzle-m801-88f8040_defconfig @@ -60,7 +60,7 @@ CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MVPP2=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_MVEBU=y CONFIG_PHY=y diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index f31668c5c23..3b3da3870b2 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -37,7 +37,7 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y diff --git a/configs/octeontx2_96xx_defconfig b/configs/octeontx2_96xx_defconfig index 1298bfe3092..1ce892d9635 100644 --- a/configs/octeontx2_96xx_defconfig +++ b/configs/octeontx2_96xx_defconfig @@ -99,7 +99,7 @@ CONFIG_E1000_SPI=y CONFIG_CMD_E1000=y CONFIG_NET_OCTEONTX2=y CONFIG_OCTEONTX_SMI=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_REGION_MULTI_ENTRY=y CONFIG_PCI_SRIOV=y diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig index ba8cc97ab87..ddb9007bf11 100644 --- a/configs/octeontx_81xx_defconfig +++ b/configs/octeontx_81xx_defconfig @@ -99,7 +99,7 @@ CONFIG_E1000_SPI=y CONFIG_CMD_E1000=y CONFIG_NET_OCTEONTX=y CONFIG_OCTEONTX_SMI=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_REGION_MULTI_ENTRY=y CONFIG_PCI_SRIOV=y diff --git a/configs/octeontx_83xx_defconfig b/configs/octeontx_83xx_defconfig index 26759341c51..b8ebc2812e1 100644 --- a/configs/octeontx_83xx_defconfig +++ b/configs/octeontx_83xx_defconfig @@ -96,7 +96,7 @@ CONFIG_E1000_SPI=y CONFIG_CMD_E1000=y CONFIG_NET_OCTEONTX=y CONFIG_OCTEONTX_SMI=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_REGION_MULTI_ENTRY=y CONFIG_PCI_SRIOV=y diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig index e4265d63215..46f4cd01102 100644 --- a/configs/p3450-0000_defconfig +++ b/configs/p3450-0000_defconfig @@ -43,7 +43,7 @@ CONFIG_SYS_I2C_TEGRA=y CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_RTL8169=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_TEGRA=y CONFIG_SYS_NS16550=y diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index 81aedb28e37..d7378f5eb39 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -56,7 +56,7 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index 6d1a6ba66f0..591b31165ff 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -60,7 +60,7 @@ CONFIG_SYS_ATA_REG_OFFSET=0 CONFIG_SYS_ATA_ALT_OFFSET=0 CONFIG_ATAPI=y CONFIG_CPU=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_SPL_DM_RTC=y CONFIG_SPI=y CONFIG_USB_KEYBOARD=y diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index b0cf7019965..928fa68e2d5 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -43,7 +43,7 @@ CONFIG_SYS_ATA_REG_OFFSET=0 CONFIG_SYS_ATA_ALT_OFFSET=0 CONFIG_ATAPI=y CONFIG_CPU=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_SPI=y CONFIG_USB_KEYBOARD=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index 8f86f19e89e..606a7fdee03 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -48,7 +48,7 @@ CONFIG_SYS_MAX_FLASH_BANKS=2 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_ECAM_GENERIC=y CONFIG_SCSI=y diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index 653c76ba615..febf8f28065 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -50,7 +50,7 @@ CONFIG_SYS_MAX_FLASH_BANKS=2 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_ECAM_GENERIC=y CONFIG_SCSI=y diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig index f60ddf00979..d4dc8ecc51f 100644 --- a/configs/rcar3_salvator-x_defconfig +++ b/configs/rcar3_salvator-x_defconfig @@ -81,7 +81,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_RENESAS_RAVB=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_REGION_MULTI_ENTRY=y CONFIG_PCI_RCAR_GEN3=y diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index ca2fb9e13f1..b79200fd3b5 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -49,7 +49,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 9a3b8f781d6..4f15627d59c 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -41,7 +41,7 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index a27799f3439..0381a1ca3f5 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -41,7 +41,7 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig index bd8b1201ef7..c066d9160ad 100644 --- a/configs/rock-pi-n10-rk3399pro_defconfig +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -42,7 +42,7 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index e46f07e74d2..d95da518912 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -42,7 +42,7 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 637c5c2466c..d5e98a4f73d 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -48,7 +48,7 @@ CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index d82c1804207..7c157a23d0f 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -167,7 +167,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_SANDBOX=y CONFIG_PHY=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 68e958216eb..7ebeb89264c 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -209,7 +209,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_MULTIPLEXER=y CONFIG_MUX_MMIO=y CONFIG_DM_ETH=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_REGION_MULTI_ENTRY=y CONFIG_PCI_SANDBOX=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index d8097123085..217b0647bb5 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -136,7 +136,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_REGION_MULTI_ENTRY=y CONFIG_PCI_SANDBOX=y diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig index b288ac2685e..ec912cf0ec8 100644 --- a/configs/sandbox_noinst_defconfig +++ b/configs/sandbox_noinst_defconfig @@ -163,7 +163,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_SANDBOX=y CONFIG_PHY=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index cd1ad386ac8..1687ccf4530 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -165,7 +165,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_SANDBOX=y CONFIG_PHY=y diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index 299580894c4..86f8c7856ea 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -44,7 +44,7 @@ CONFIG_SPL_CLK=y CONFIG_SYS_I2C_EEPROM_ADDR=0x54 CONFIG_SPI_FLASH_ISSI=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_SIFIVE=y CONFIG_DM_RESET=y diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig index da57dc288fd..fe12c74374f 100644 --- a/configs/synquacer_developerbox_defconfig +++ b/configs/synquacer_developerbox_defconfig @@ -69,7 +69,7 @@ CONFIG_PHY_GIGE=y CONFIG_RGMII=y CONFIG_MII=y CONFIG_SNI_NETSEC=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_DM_RTC=y CONFIG_RTC_PCF8563=y CONFIG_SCSI=y diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index 415387b189d..84a0b4c2b20 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -79,7 +79,7 @@ CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_AARDVARK=y CONFIG_PHY=y diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index d6f70caeafa..938683616bf 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -78,7 +78,7 @@ CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_MVEBU=y CONFIG_DM_RTC=y diff --git a/doc/develop/driver-model/nvme.rst b/doc/develop/driver-model/nvme.rst index 736c0a063dc..fd0c0f00d2d 100644 --- a/doc/develop/driver-model/nvme.rst +++ b/doc/develop/driver-model/nvme.rst @@ -40,6 +40,7 @@ It only support basic block read/write functions in the NVMe driver. Config options -------------- CONFIG_NVME Enable NVMe device support +CONFIG_NVME_PCI Enable PCIe NVMe device support CONFIG_CMD_NVME Enable basic NVMe commands Usage in U-Boot diff --git a/drivers/nvme/Kconfig b/drivers/nvme/Kconfig index 1f6d1f56484..78da444c8b4 100644 --- a/drivers/nvme/Kconfig +++ b/drivers/nvme/Kconfig @@ -4,8 +4,16 @@ config NVME bool "NVM Express device support" - depends on BLK && PCI + depends on BLK select HAVE_BLOCK_DEVICE help This option enables support for NVM Express devices. It supports basic functions of NVMe (read/write). + +config NVME_PCI + bool "NVM Express PCI device support" + depends on PCI + select NVME + help + This option enables support for NVM Express PCI + devices. diff --git a/drivers/nvme/Makefile b/drivers/nvme/Makefile index 64f102b208c..fad9724e17b 100644 --- a/drivers/nvme/Makefile +++ b/drivers/nvme/Makefile @@ -3,3 +3,4 @@ # Copyright (C) 2017, Bin Meng obj-y += nvme-uclass.o nvme.o nvme_show.o +obj-$(CONFIG_NVME_PCI) += nvme_pci.o diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c index 3c529a2fce2..be518ec20b1 100644 --- a/drivers/nvme/nvme.c +++ b/drivers/nvme/nvme.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -698,7 +697,6 @@ static int nvme_blk_probe(struct udevice *udev) struct blk_desc *desc = dev_get_uclass_plat(udev); struct nvme_ns *ns = dev_get_priv(udev); u8 flbas; - struct pci_child_plat *pplat; struct nvme_id_ns *id; id = memalign(ndev->page_size, sizeof(struct nvme_id_ns)); @@ -723,8 +721,7 @@ static int nvme_blk_probe(struct udevice *udev) desc->log2blksz = ns->lba_shift; desc->blksz = 1 << ns->lba_shift; desc->bdev = udev; - pplat = dev_get_parent_plat(udev->parent); - sprintf(desc->vendor, "0x%.4x", pplat->vendor); + memcpy(desc->vendor, ndev->vendor, sizeof(ndev->vendor)); memcpy(desc->product, ndev->serial, sizeof(ndev->serial)); memcpy(desc->revision, ndev->firmware_rev, sizeof(ndev->firmware_rev)); @@ -818,27 +815,13 @@ U_BOOT_DRIVER(nvme_blk) = { .priv_auto = sizeof(struct nvme_ns), }; -static int nvme_bind(struct udevice *udev) +int nvme_init(struct udevice *udev) { - static int ndev_num; - char name[20]; - - sprintf(name, "nvme#%d", ndev_num++); - - return device_set_name(udev, name); -} - -static int nvme_probe(struct udevice *udev) -{ - int ret; struct nvme_dev *ndev = dev_get_priv(udev); struct nvme_id_ns *id; - - ndev->instance = trailing_strtol(udev->name); + int ret; INIT_LIST_HEAD(&ndev->namespaces); - ndev->bar = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0, - PCI_REGION_MEM); if (readl(&ndev->bar->csts) == -1) { ret = -ENODEV; printf("Error: %s: Out of memory!\n", udev->name); @@ -922,18 +905,3 @@ free_queue: free_nvme: return ret; } - -U_BOOT_DRIVER(nvme) = { - .name = "nvme", - .id = UCLASS_NVME, - .bind = nvme_bind, - .probe = nvme_probe, - .priv_auto = sizeof(struct nvme_dev), -}; - -struct pci_device_id nvme_supported[] = { - { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, ~0) }, - {} -}; - -U_BOOT_PCI_DEVICE(nvme, nvme_supported); diff --git a/drivers/nvme/nvme.h b/drivers/nvme/nvme.h index c6aae4da5df..8e9ae3c7f62 100644 --- a/drivers/nvme/nvme.h +++ b/drivers/nvme/nvme.h @@ -608,6 +608,7 @@ struct nvme_dev { u32 ctrl_config; struct nvme_bar __iomem *bar; struct list_head namespaces; + char vendor[8]; char serial[20]; char model[40]; char firmware_rev[8]; @@ -635,4 +636,6 @@ struct nvme_ns { u8 flbas; }; +int nvme_init(struct udevice *udev); + #endif /* __DRIVER_NVME_H__ */ diff --git a/drivers/nvme/nvme_pci.c b/drivers/nvme/nvme_pci.c new file mode 100644 index 00000000000..5f60fb884fb --- /dev/null +++ b/drivers/nvme/nvme_pci.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 NXP Semiconductors + * Copyright (C) 2017 Bin Meng + */ + +#include +#include +#include +#include "nvme.h" + +static int nvme_bind(struct udevice *udev) +{ + static int ndev_num; + char name[20]; + + sprintf(name, "nvme#%d", ndev_num++); + + return device_set_name(udev, name); +} + +static int nvme_probe(struct udevice *udev) +{ + struct nvme_dev *ndev = dev_get_priv(udev); + struct pci_child_plat *pplat; + + pplat = dev_get_parent_plat(udev); + sprintf(ndev->vendor, "0x%.4x", pplat->vendor); + + ndev->instance = trailing_strtol(udev->name); + ndev->bar = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0, + PCI_REGION_MEM); + return nvme_init(udev); +} + +U_BOOT_DRIVER(nvme) = { + .name = "nvme", + .id = UCLASS_NVME, + .bind = nvme_bind, + .probe = nvme_probe, + .priv_auto = sizeof(struct nvme_dev), +}; + +struct pci_device_id nvme_supported[] = { + { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, ~0) }, + {} +}; + +U_BOOT_PCI_DEVICE(nvme, nvme_supported); From 456305ec597908536e8e0de32dade43f9db00e8c Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Sat, 22 Jan 2022 20:38:12 +0100 Subject: [PATCH 02/15] mailbox: apple: Add driver for Apple IOP mailbox This mailbox driver provides a communication channel with the Apple IOP controllers found on Apple SoCs. These IOP controllers are used to implement various functions such as the System Manegement Controller (SMC) and NVMe storage. It allows sending and receiving a 96-bit message over a single channel. The header file with the struct used for mailbox messages is taken straight from Linux. Signed-off-by: Mark Kettenis Signed-off-by: Sven Peter Reviewed-by: Simon Glass Tested on: Macbook Air M1 Tested-by: Simon Glass --- arch/arm/Kconfig | 1 + drivers/mailbox/Kconfig | 11 +++++ drivers/mailbox/Makefile | 1 + drivers/mailbox/apple-mbox.c | 92 +++++++++++++++++++++++++++++++++++ include/linux/apple-mailbox.h | 19 ++++++++ 5 files changed, 124 insertions(+) create mode 100644 drivers/mailbox/apple-mbox.c create mode 100644 include/linux/apple-mailbox.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9a62b557869..ce51d87ac06 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -931,6 +931,7 @@ config ARCH_APPLE select DM select DM_GPIO select DM_KEYBOARD + select DM_MAILBOX select DM_SERIAL select DM_USB select DM_VIDEO diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index dd4b0ac0c33..73db2af0b81 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -10,6 +10,17 @@ config DM_MAILBOX the basis of a variety of inter-process/inter-CPU communication protocols. +config APPLE_MBOX + bool "Enable Apple IOP controller support" + depends on DM_MAILBOX && ARCH_APPLE + default y + help + Enable support for the mailboxes that provide a comminucation + channel with Apple IOP controllers integrated on Apple SoCs. + These IOP controllers are used to implement various functions + such as the System Management Controller (SMC) and NVMe and this + driver is required to get that functionality up and running. + config SANDBOX_MBOX bool "Enable the sandbox mailbox test driver" depends on DM_MAILBOX && SANDBOX diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index d2ace8cd212..59e8d0de93c 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -4,6 +4,7 @@ # obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox-uclass.o +obj-$(CONFIG_APPLE_MBOX) += apple-mbox.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o diff --git a/drivers/mailbox/apple-mbox.c b/drivers/mailbox/apple-mbox.c new file mode 100644 index 00000000000..30c8e2f03fa --- /dev/null +++ b/drivers/mailbox/apple-mbox.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 Mark Kettenis + */ + +#include +#include +#include +#include +#include +#include + +#define REG_A2I_STAT 0x110 +#define REG_A2I_STAT_EMPTY BIT(17) +#define REG_A2I_STAT_FULL BIT(16) +#define REG_I2A_STAT 0x114 +#define REG_I2A_STAT_EMPTY BIT(17) +#define REG_I2A_STAT_FULL BIT(16) +#define REG_A2I_MSG0 0x800 +#define REG_A2I_MSG1 0x808 +#define REG_I2A_MSG0 0x830 +#define REG_I2A_MSG1 0x838 + +struct apple_mbox_priv { + void *base; +}; + +static int apple_mbox_of_xlate(struct mbox_chan *chan, + struct ofnode_phandle_args *args) +{ + if (args->args_count != 0) + return -EINVAL; + + return 0; +} + +static int apple_mbox_send(struct mbox_chan *chan, const void *data) +{ + struct apple_mbox_priv *priv = dev_get_priv(chan->dev); + const struct apple_mbox_msg *msg = data; + + writeq(msg->msg0, priv->base + REG_A2I_MSG0); + writeq(msg->msg1, priv->base + REG_A2I_MSG1); + while (readl(priv->base + REG_A2I_STAT) & REG_A2I_STAT_FULL) + udelay(1); + + return 0; +} + +static int apple_mbox_recv(struct mbox_chan *chan, void *data) +{ + struct apple_mbox_priv *priv = dev_get_priv(chan->dev); + struct apple_mbox_msg *msg = data; + + if (readl(priv->base + REG_I2A_STAT) & REG_I2A_STAT_EMPTY) + return -ENODATA; + + msg->msg0 = readq(priv->base + REG_I2A_MSG0); + msg->msg1 = readq(priv->base + REG_I2A_MSG1); + return 0; +} + +struct mbox_ops apple_mbox_ops = { + .of_xlate = apple_mbox_of_xlate, + .send = apple_mbox_send, + .recv = apple_mbox_recv, +}; + +static int apple_mbox_probe(struct udevice *dev) +{ + struct apple_mbox_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -EINVAL; + + return 0; +} + +static const struct udevice_id apple_mbox_of_match[] = { + { .compatible = "apple,asc-mailbox-v4" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(apple_mbox) = { + .name = "apple-mbox", + .id = UCLASS_MAILBOX, + .of_match = apple_mbox_of_match, + .probe = apple_mbox_probe, + .priv_auto = sizeof(struct apple_mbox_priv), + .ops = &apple_mbox_ops, +}; diff --git a/include/linux/apple-mailbox.h b/include/linux/apple-mailbox.h new file mode 100644 index 00000000000..720fbb70294 --- /dev/null +++ b/include/linux/apple-mailbox.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * Apple mailbox message format + * + * Copyright (C) 2021 The Asahi Linux Contributors + */ + +#ifndef _LINUX_APPLE_MAILBOX_H_ +#define _LINUX_APPLE_MAILBOX_H_ + +#include + +/* encodes a single 96bit message sent over the single channel */ +struct apple_mbox_msg { + u64 msg0; + u32 msg1; +}; + +#endif From a4bd5e4120d6389476c078076ce2746e3058037a Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Sat, 22 Jan 2022 20:38:13 +0100 Subject: [PATCH 03/15] arm: apple: Change SoC name from "m1" into "apple" U-Boot is expected to support multiple generations of Apple SoCs in a single binary with a single defconfig. Therefore it makes more sense to set SYS_SOC to "apple". Signed-off-by: Mark Kettenis Reviewed-by: Simon Glass --- arch/arm/include/asm/{arch-m1 => arch-apple}/uart.h | 0 arch/arm/mach-apple/Kconfig | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename arch/arm/include/asm/{arch-m1 => arch-apple}/uart.h (100%) diff --git a/arch/arm/include/asm/arch-m1/uart.h b/arch/arm/include/asm/arch-apple/uart.h similarity index 100% rename from arch/arm/include/asm/arch-m1/uart.h rename to arch/arm/include/asm/arch-apple/uart.h diff --git a/arch/arm/mach-apple/Kconfig b/arch/arm/mach-apple/Kconfig index 80e8eb23079..75ee21e0f4c 100644 --- a/arch/arm/mach-apple/Kconfig +++ b/arch/arm/mach-apple/Kconfig @@ -7,7 +7,7 @@ config SYS_CONFIG_NAME default "apple" config SYS_SOC - default "m1" + default "apple" config SYS_MALLOC_LEN default 0x4000000 From 02e2588d3f8fed7bf25ac1677072dd607c4dd72e Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Sat, 22 Jan 2022 20:38:14 +0100 Subject: [PATCH 04/15] arm: apple: Add RTKit support Most Apple IOPs run a firmware that is based on what Apple calls RTKit. RTKit implements a common mailbox protocol. This code provides an implementation of the AP side of this protocol, providing a function to initialize RTKit-based firmwares as well as a function to do a clean shutdown of this firmware. Signed-off-by: Mark Kettenis Reviewed-by: Simon Glass Tested on: Macbook Air M1 Tested-by: Simon Glass --- arch/arm/include/asm/arch-apple/rtkit.h | 11 ++ arch/arm/mach-apple/Makefile | 1 + arch/arm/mach-apple/rtkit.c | 231 ++++++++++++++++++++++++ 3 files changed, 243 insertions(+) create mode 100644 arch/arm/include/asm/arch-apple/rtkit.h create mode 100644 arch/arm/mach-apple/rtkit.c diff --git a/arch/arm/include/asm/arch-apple/rtkit.h b/arch/arm/include/asm/arch-apple/rtkit.h new file mode 100644 index 00000000000..51f77f298c0 --- /dev/null +++ b/arch/arm/include/asm/arch-apple/rtkit.h @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021 Mark Kettenis + */ + +#define APPLE_RTKIT_PWR_STATE_SLEEP 0x01 +#define APPLE_RTKIT_PWR_STATE_QUIESCED 0x10 +#define APPLE_RTKIT_PWR_STATE_ON 0x20 + +int apple_rtkit_init(struct mbox_chan *); +int apple_rtkit_shutdown(struct mbox_chan *, int); diff --git a/arch/arm/mach-apple/Makefile b/arch/arm/mach-apple/Makefile index e74a8c9df10..52f30a777b2 100644 --- a/arch/arm/mach-apple/Makefile +++ b/arch/arm/mach-apple/Makefile @@ -2,3 +2,4 @@ obj-y += board.o obj-y += lowlevel_init.o +obj-y += rtkit.o diff --git a/arch/arm/mach-apple/rtkit.c b/arch/arm/mach-apple/rtkit.c new file mode 100644 index 00000000000..dff475cab7d --- /dev/null +++ b/arch/arm/mach-apple/rtkit.c @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021 Mark Kettenis + * (C) Copyright 2021 Copyright The Asahi Linux Contributors + */ + +#include +#include +#include + +#include +#include +#include + +#define APPLE_RTKIT_EP_MGMT 0 +#define APPLE_RTKIT_EP_CRASHLOG 1 +#define APPLE_RTKIT_EP_SYSLOG 2 +#define APPLE_RTKIT_EP_DEBUG 3 +#define APPLE_RTKIT_EP_IOREPORT 4 + +/* Messages for management endpoint. */ +#define APPLE_RTKIT_MGMT_TYPE GENMASK(59, 52) + +#define APPLE_RTKIT_MGMT_PWR_STATE GENMASK(15, 0) + +#define APPLE_RTKIT_MGMT_HELLO 1 +#define APPLE_RTKIT_MGMT_HELLO_REPLY 2 +#define APPLE_RTKIT_MGMT_HELLO_MINVER GENMASK(15, 0) +#define APPLE_RTKIT_MGMT_HELLO_MAXVER GENMASK(31, 16) + +#define APPLE_RTKIT_MGMT_STARTEP 5 +#define APPLE_RTKIT_MGMT_STARTEP_EP GENMASK(39, 32) +#define APPLE_RTKIT_MGMT_STARTEP_FLAG BIT(1) + +#define APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE 6 +#define APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE_ACK 7 + +#define APPLE_RTKIT_MGMT_EPMAP 8 +#define APPLE_RTKIT_MGMT_EPMAP_LAST BIT(51) +#define APPLE_RTKIT_MGMT_EPMAP_BASE GENMASK(34, 32) +#define APPLE_RTKIT_MGMT_EPMAP_BITMAP GENMASK(31, 0) + +#define APPLE_RTKIT_MGMT_EPMAP_REPLY 8 +#define APPLE_RTKIT_MGMT_EPMAP_REPLY_MORE BIT(0) + +#define APPLE_RTKIT_MIN_SUPPORTED_VERSION 11 +#define APPLE_RTKIT_MAX_SUPPORTED_VERSION 12 + +/* Messages for internal endpoints. */ +#define APPLE_RTKIT_BUFFER_REQUEST 1 +#define APPLE_RTKIT_BUFFER_REQUEST_SIZE GENMASK(51, 44) +#define APPLE_RTKIT_BUFFER_REQUEST_IOVA GENMASK(41, 0) + +int apple_rtkit_init(struct mbox_chan *chan) +{ + struct apple_mbox_msg msg; + int endpoints[256]; + int nendpoints = 0; + int endpoint; + int min_ver, max_ver, want_ver; + int msgtype, pwrstate; + u64 reply; + u32 bitmap, base; + int i, ret; + + /* Wakup the IOP. */ + msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE) | + FIELD_PREP(APPLE_RTKIT_MGMT_PWR_STATE, APPLE_RTKIT_PWR_STATE_ON); + msg.msg1 = APPLE_RTKIT_EP_MGMT; + ret = mbox_send(chan, &msg); + if (ret < 0) + return ret; + + /* Wait for protocol version negotiation message. */ + ret = mbox_recv(chan, &msg, 10000); + if (ret < 0) + return ret; + + endpoint = msg.msg1; + msgtype = FIELD_GET(APPLE_RTKIT_MGMT_TYPE, msg.msg0); + if (endpoint != APPLE_RTKIT_EP_MGMT) { + printf("%s: unexpected endpoint %d\n", __func__, endpoint); + return -EINVAL; + } + if (msgtype != APPLE_RTKIT_MGMT_HELLO) { + printf("%s: unexpected message type %d\n", __func__, msgtype); + return -EINVAL; + } + + min_ver = FIELD_GET(APPLE_RTKIT_MGMT_HELLO_MINVER, msg.msg0); + max_ver = FIELD_GET(APPLE_RTKIT_MGMT_HELLO_MAXVER, msg.msg0); + want_ver = min(APPLE_RTKIT_MAX_SUPPORTED_VERSION, max_ver); + + if (min_ver > APPLE_RTKIT_MAX_SUPPORTED_VERSION) { + printf("%s: firmware min version %d is too new\n", + __func__, min_ver); + return -ENOTSUPP; + } + + if (max_ver < APPLE_RTKIT_MIN_SUPPORTED_VERSION) { + printf("%s: firmware max version %d is too old\n", + __func__, max_ver); + return -ENOTSUPP; + } + + /* Ack version. */ + msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_HELLO_REPLY) | + FIELD_PREP(APPLE_RTKIT_MGMT_HELLO_MINVER, want_ver) | + FIELD_PREP(APPLE_RTKIT_MGMT_HELLO_MAXVER, want_ver); + msg.msg1 = APPLE_RTKIT_EP_MGMT; + ret = mbox_send(chan, &msg); + if (ret < 0) + return ret; + +wait_epmap: + /* Wait for endpoint map message. */ + ret = mbox_recv(chan, &msg, 10000); + if (ret < 0) + return ret; + + endpoint = msg.msg1; + msgtype = FIELD_GET(APPLE_RTKIT_MGMT_TYPE, msg.msg0); + if (endpoint != APPLE_RTKIT_EP_MGMT) { + printf("%s: unexpected endpoint %d\n", __func__, endpoint); + return -EINVAL; + } + if (msgtype != APPLE_RTKIT_MGMT_EPMAP) { + printf("%s: unexpected message type %d\n", __func__, msgtype); + return -EINVAL; + } + + bitmap = FIELD_GET(APPLE_RTKIT_MGMT_EPMAP_BITMAP, msg.msg0); + base = FIELD_GET(APPLE_RTKIT_MGMT_EPMAP_BASE, msg.msg0); + for (i = 0; i < 32; i++) { + if (bitmap & (1U << i)) + endpoints[nendpoints++] = base * 32 + i; + } + + /* Ack endpoint map. */ + reply = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_EPMAP_REPLY) | + FIELD_PREP(APPLE_RTKIT_MGMT_EPMAP_BASE, base); + if (msg.msg0 & APPLE_RTKIT_MGMT_EPMAP_LAST) + reply |= APPLE_RTKIT_MGMT_EPMAP_LAST; + else + reply |= APPLE_RTKIT_MGMT_EPMAP_REPLY_MORE; + msg.msg0 = reply; + msg.msg1 = APPLE_RTKIT_EP_MGMT; + ret = mbox_send(chan, &msg); + if (ret < 0) + return ret; + + if (reply & APPLE_RTKIT_MGMT_EPMAP_REPLY_MORE) + goto wait_epmap; + + for (i = 0; i < nendpoints; i++) { + /* Don't start the syslog endpoint since we can't + easily handle its messages in U-Boot. */ + if (endpoints[i] == APPLE_RTKIT_EP_SYSLOG) + continue; + + /* Request endpoint. */ + msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_STARTEP) | + FIELD_PREP(APPLE_RTKIT_MGMT_STARTEP_EP, endpoints[i]) | + APPLE_RTKIT_MGMT_STARTEP_FLAG; + msg.msg1 = APPLE_RTKIT_EP_MGMT; + ret = mbox_send(chan, &msg); + if (ret < 0) + return ret; + } + + pwrstate = APPLE_RTKIT_PWR_STATE_SLEEP; + while (pwrstate != APPLE_RTKIT_PWR_STATE_ON) { + ret = mbox_recv(chan, &msg, 100000); + if (ret < 0) + return ret; + + endpoint = msg.msg1; + msgtype = FIELD_GET(APPLE_RTKIT_MGMT_TYPE, msg.msg0); + + if (endpoint == APPLE_RTKIT_EP_CRASHLOG || + endpoint == APPLE_RTKIT_EP_SYSLOG || + endpoint == APPLE_RTKIT_EP_IOREPORT) { + u64 addr = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_IOVA, msg.msg0); + u64 size = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_SIZE, msg.msg0); + + if (msgtype == APPLE_RTKIT_BUFFER_REQUEST && addr != 0) + continue; + + msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_BUFFER_REQUEST) | + FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_SIZE, size) | + FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_IOVA, addr); + msg.msg1 = endpoint; + ret = mbox_send(chan, &msg); + if (ret < 0) + return ret; + continue; + } + + if (endpoint != APPLE_RTKIT_EP_MGMT) { + printf("%s: unexpected endpoint %d\n", __func__, endpoint); + return -EINVAL; + } + if (msgtype != APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE_ACK) { + printf("%s: unexpected message type %d\n", __func__, msgtype); + return -EINVAL; + } + + pwrstate = FIELD_GET(APPLE_RTKIT_MGMT_PWR_STATE, msg.msg0); + } + + return 0; +} + +int apple_rtkit_shutdown(struct mbox_chan *chan, int pwrstate) +{ + struct apple_mbox_msg msg; + int ret; + + msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE) | + FIELD_PREP(APPLE_RTKIT_MGMT_PWR_STATE, pwrstate); + msg.msg1 = APPLE_RTKIT_EP_MGMT; + ret = mbox_send(chan, &msg); + if (ret < 0) + return ret; + + ret = mbox_recv(chan, &msg, 100000); + if (ret < 0) + return ret; + + return 0; +} From 19d9dad39c28a6e932ee2ec8361f42211613761d Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Sat, 22 Jan 2022 20:38:15 +0100 Subject: [PATCH 05/15] nvme: Introduce driver ops The NVMe storage controller integrated on Apple SoCs deviates from the NVMe standard in two aspects. It uses a "linear" submission queue and it integrates an NVMMU that needs to be programmed for each NVMe command. Introduce driver ops such that we can set up the linear submission queue and program the NVMMU in the driver for this strange beast. Signed-off-by: Mark Kettenis Reviewed-by: Simon Glass Tested on: Macbook Air M1 Tested-by: Simon Glass --- drivers/nvme/nvme.c | 45 +++++++++++++++---------------------- drivers/nvme/nvme.h | 55 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+), 27 deletions(-) diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c index be518ec20b1..e7cbf39c96a 100644 --- a/drivers/nvme/nvme.c +++ b/drivers/nvme/nvme.c @@ -27,33 +27,6 @@ #define IO_TIMEOUT 30 #define MAX_PRP_POOL 512 -enum nvme_queue_id { - NVME_ADMIN_Q, - NVME_IO_Q, - NVME_Q_NUM, -}; - -/* - * An NVM Express queue. Each device has at least two (one for admin - * commands and one for I/O commands). - */ -struct nvme_queue { - struct nvme_dev *dev; - struct nvme_command *sq_cmds; - struct nvme_completion *cqes; - wait_queue_head_t sq_full; - u32 __iomem *q_db; - u16 q_depth; - s16 cq_vector; - u16 sq_head; - u16 sq_tail; - u16 cq_head; - u16 qid; - u8 cq_phase; - u8 cqe_seen; - unsigned long cmdid_data[]; -}; - static int nvme_wait_ready(struct nvme_dev *dev, bool enabled) { u32 bit = enabled ? NVME_CSTS_RDY : 0; @@ -167,12 +140,19 @@ static u16 nvme_read_completion_status(struct nvme_queue *nvmeq, u16 index) */ static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) { + struct nvme_ops *ops; u16 tail = nvmeq->sq_tail; memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); flush_dcache_range((ulong)&nvmeq->sq_cmds[tail], (ulong)&nvmeq->sq_cmds[tail] + sizeof(*cmd)); + ops = (struct nvme_ops *)nvmeq->dev->udev->driver->ops; + if (ops && ops->submit_cmd) { + ops->submit_cmd(nvmeq, cmd); + return; + } + if (++tail == nvmeq->q_depth) tail = 0; writel(tail, nvmeq->q_db); @@ -183,6 +163,7 @@ static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, u32 *result, unsigned timeout) { + struct nvme_ops *ops; u16 head = nvmeq->cq_head; u16 phase = nvmeq->cq_phase; u16 status; @@ -203,6 +184,10 @@ static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, return -ETIMEDOUT; } + ops = (struct nvme_ops *)nvmeq->dev->udev->driver->ops; + if (ops && ops->complete_cmd) + ops->complete_cmd(nvmeq, cmd); + status >>= 1; if (status) { printf("ERROR: status = %x, phase = %d, head = %d\n", @@ -243,6 +228,7 @@ static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd, static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) { + struct nvme_ops *ops; struct nvme_queue *nvmeq = malloc(sizeof(*nvmeq)); if (!nvmeq) return NULL; @@ -268,6 +254,10 @@ static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, dev->queue_count++; dev->queues[qid] = nvmeq; + ops = (struct nvme_ops *)dev->udev->driver->ops; + if (ops && ops->setup_queue) + ops->setup_queue(nvmeq); + return nvmeq; free_queue: @@ -821,6 +811,7 @@ int nvme_init(struct udevice *udev) struct nvme_id_ns *id; int ret; + ndev->udev = udev; INIT_LIST_HEAD(&ndev->namespaces); if (readl(&ndev->bar->csts) == -1) { ret = -ENODEV; diff --git a/drivers/nvme/nvme.h b/drivers/nvme/nvme.h index 8e9ae3c7f62..bc6b79f8dd1 100644 --- a/drivers/nvme/nvme.h +++ b/drivers/nvme/nvme.h @@ -596,6 +596,7 @@ enum { /* Represents an NVM Express device. Each nvme_dev is a PCI function. */ struct nvme_dev { + struct udevice *udev; struct list_head node; struct nvme_queue **queues; u32 __iomem *dbs; @@ -622,6 +623,33 @@ struct nvme_dev { u32 nn; }; +/* Admin queue and a single I/O queue. */ +enum nvme_queue_id { + NVME_ADMIN_Q, + NVME_IO_Q, + NVME_Q_NUM, +}; + +/* + * An NVM Express queue. Each device has at least two (one for admin + * commands and one for I/O commands). + */ +struct nvme_queue { + struct nvme_dev *dev; + struct nvme_command *sq_cmds; + struct nvme_completion *cqes; + u32 __iomem *q_db; + u16 q_depth; + s16 cq_vector; + u16 sq_head; + u16 sq_tail; + u16 cq_head; + u16 qid; + u8 cq_phase; + u8 cqe_seen; + unsigned long cmdid_data[]; +}; + /* * An NVM Express namespace is equivalent to a SCSI LUN. * Each namespace is operated as an independent "device". @@ -636,6 +664,33 @@ struct nvme_ns { u8 flbas; }; +struct nvme_ops { + /** + * setup_queue - Controller-specific NVM Express queue setup. + * + * @nvmeq: NVM Express queue + * Return: 0 if OK, -ve on error + */ + int (*setup_queue)(struct nvme_queue *nvmeq); + /** + * submit_cmd - Controller-specific NVM Express command submission. + * + * If this function pointer is set to NULL, normal command + * submission is performed according to the NVM Express spec. + * + * @nvmeq: NVM Express queue + * @cmd: NVM Express command + */ + void (*submit_cmd)(struct nvme_queue *nvmeq, struct nvme_command *cmd); + /** + * complete_cmd - Controller-specific NVM Express command completion + * + * @nvmeq: NVM Express queue + * @cmd: NVM Express command + */ + void (*complete_cmd)(struct nvme_queue *nvmeq, struct nvme_command *cmd); +}; + int nvme_init(struct udevice *udev); #endif /* __DRIVER_NVME_H__ */ From ca99a17e02ab4f99b1455be349858d5a7aa7553c Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Sat, 22 Jan 2022 20:38:16 +0100 Subject: [PATCH 06/15] nvme: Add shutdown function Add a function to disable the NVMe controller. This will be used to let the driver for the NVMe storage integrated on Apple SoCs shutdown the NVMe controller such we can shutdown the NVMe IOP controller in a clean way afterwards before handing control to the OS. Signed-off-by: Mark Kettenis Reviewed-by: Simon Glass Tested on: Macbook Air M1 Tested-by: Simon Glass --- drivers/nvme/nvme.c | 7 +++++++ drivers/nvme/nvme.h | 12 ++++++++++++ 2 files changed, 19 insertions(+) diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c index e7cbf39c96a..1d56517e996 100644 --- a/drivers/nvme/nvme.c +++ b/drivers/nvme/nvme.c @@ -896,3 +896,10 @@ free_queue: free_nvme: return ret; } + +int nvme_shutdown(struct udevice *udev) +{ + struct nvme_dev *ndev = dev_get_priv(udev); + + return nvme_disable_ctrl(ndev); +} diff --git a/drivers/nvme/nvme.h b/drivers/nvme/nvme.h index bc6b79f8dd1..bc1d612dde4 100644 --- a/drivers/nvme/nvme.h +++ b/drivers/nvme/nvme.h @@ -691,6 +691,18 @@ struct nvme_ops { void (*complete_cmd)(struct nvme_queue *nvmeq, struct nvme_command *cmd); }; +/** + * nvme_init() - Initialize NVM Express device + * @udev: The NVM Express device + * Return: 0 if OK, -ve on error + */ int nvme_init(struct udevice *udev); +/** + * nvme_shutdown() - Shutdown NVM Express device + * @udev: The NVM Express device + * Return: 0 if OK, -ve on error + */ +int nvme_shutdown(struct udevice *udev); + #endif /* __DRIVER_NVME_H__ */ From 81fafbbeba3211ed60ac8aff41a2e1fcb9a40431 Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Sat, 22 Jan 2022 20:38:17 +0100 Subject: [PATCH 07/15] power: domain: apple: Add reset support The power management controller found on Apple SoCs als provides a way to reset all devices within a power domain. This is needed to cleanly shutdown the NVMe controller before we hand over control to the OS. Signed-off-by: Mark Kettenis Reviewed-by: Simon Glass Tested on: Macbook Air M1 Tested-by: Simon Glass Reviewed-by: Jaehoon Chung --- arch/arm/Kconfig | 1 + drivers/power/domain/apple-pmgr.c | 73 ++++++++++++++++++++++++++++++- 2 files changed, 73 insertions(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ce51d87ac06..5048d3d33c4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -932,6 +932,7 @@ config ARCH_APPLE select DM_GPIO select DM_KEYBOARD select DM_MAILBOX + select DM_RESET select DM_SERIAL select DM_USB select DM_VIDEO diff --git a/drivers/power/domain/apple-pmgr.c b/drivers/power/domain/apple-pmgr.c index d25f136b9dc..4d06e76ff5e 100644 --- a/drivers/power/domain/apple-pmgr.c +++ b/drivers/power/domain/apple-pmgr.c @@ -6,14 +6,22 @@ #include #include #include +#include #include #include #include +#include #include #include -#define APPLE_PMGR_PS_TARGET GENMASK(3, 0) +#define APPLE_PMGR_RESET BIT(31) +#define APPLE_PMGR_DEV_DISABLE BIT(10) +#define APPLE_PMGR_WAS_CLKGATED BIT(9) +#define APPLE_PMGR_WAS_PWRGATED BIT(8) #define APPLE_PMGR_PS_ACTUAL GENMASK(7, 4) +#define APPLE_PMGR_PS_TARGET GENMASK(3, 0) + +#define APPLE_PMGR_FLAGS (APPLE_PMGR_WAS_CLKGATED | APPLE_PMGR_WAS_PWRGATED) #define APPLE_PMGR_PS_ACTIVE 0xf #define APPLE_PMGR_PS_PWRGATE 0x0 @@ -25,6 +33,65 @@ struct apple_pmgr_priv { u32 offset; /* offset within regmap for this domain */ }; +static int apple_reset_of_xlate(struct reset_ctl *reset_ctl, + struct ofnode_phandle_args *args) +{ + if (args->args_count != 0) + return -EINVAL; + + return 0; +} + +static int apple_reset_request(struct reset_ctl *reset_ctl) +{ + return 0; +} + +static int apple_reset_free(struct reset_ctl *reset_ctl) +{ + return 0; +} + +static int apple_reset_assert(struct reset_ctl *reset_ctl) +{ + struct apple_pmgr_priv *priv = dev_get_priv(reset_ctl->dev->parent); + + regmap_update_bits(priv->regmap, priv->offset, + APPLE_PMGR_FLAGS | APPLE_PMGR_DEV_DISABLE, + APPLE_PMGR_DEV_DISABLE); + regmap_update_bits(priv->regmap, priv->offset, + APPLE_PMGR_FLAGS | APPLE_PMGR_RESET, + APPLE_PMGR_RESET); + + return 0; +} + +static int apple_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct apple_pmgr_priv *priv = dev_get_priv(reset_ctl->dev->parent); + + regmap_update_bits(priv->regmap, priv->offset, + APPLE_PMGR_FLAGS | APPLE_PMGR_RESET, 0); + regmap_update_bits(priv->regmap, priv->offset, + APPLE_PMGR_FLAGS | APPLE_PMGR_DEV_DISABLE, 0); + + return 0; +} + +struct reset_ops apple_reset_ops = { + .of_xlate = apple_reset_of_xlate, + .request = apple_reset_request, + .rfree = apple_reset_free, + .rst_assert = apple_reset_assert, + .rst_deassert = apple_reset_deassert, +}; + +static struct driver apple_reset_driver = { + .name = "apple_reset", + .id = UCLASS_RESET, + .ops = &apple_reset_ops, +}; + static int apple_pmgr_request(struct power_domain *power_domain) { return 0; @@ -78,6 +145,7 @@ static const struct udevice_id apple_pmgr_ids[] = { static int apple_pmgr_probe(struct udevice *dev) { struct apple_pmgr_priv *priv = dev_get_priv(dev); + struct udevice *child; int ret; ret = dev_power_domain_on(dev); @@ -92,6 +160,9 @@ static int apple_pmgr_probe(struct udevice *dev) if (ret < 0) return ret; + device_bind(dev, &apple_reset_driver, "apple_reset", NULL, + dev_ofnode(dev), &child); + return 0; } From 50333c94f2de161cdfda2ef1c9845c3a28e7a5d6 Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Sat, 22 Jan 2022 20:38:18 +0100 Subject: [PATCH 08/15] nvme: apple: Add driver for Apple NVMe storage controller Add a driver for the NVMe storage controller integrated on Apple SoCs. This NVMe controller isn't PCI based and deviates from the NVMe standard in its implementation of the command submission queue and the integration of an NVMMU that needs to be managed. This commit tweaks the core NVMe code to support the linear command submission queue implemented by this controller. But setting up the submission queue and managing the NVMMU controller is handled by implementing the driver ops that were added in an earlier commit. Signed-off-by: Mark Kettenis Tested-on: firefly-rk3399 Tested-by: Mark Kettenis Tested on: Macbook Air M1 Tested-by: Simon Glass --- configs/apple_m1_defconfig | 1 + drivers/nvme/Kconfig | 11 ++ drivers/nvme/Makefile | 1 + drivers/nvme/nvme_apple.c | 240 +++++++++++++++++++++++++++++++++++++ 4 files changed, 253 insertions(+) create mode 100644 drivers/nvme/nvme_apple.c diff --git a/configs/apple_m1_defconfig b/configs/apple_m1_defconfig index cb235e4e7df..1528217b178 100644 --- a/configs/apple_m1_defconfig +++ b/configs/apple_m1_defconfig @@ -11,6 +11,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_NET is not set # CONFIG_MMC is not set CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_NVME_APPLE=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_KEYBOARD=y diff --git a/drivers/nvme/Kconfig b/drivers/nvme/Kconfig index 78da444c8b4..0cb465160bb 100644 --- a/drivers/nvme/Kconfig +++ b/drivers/nvme/Kconfig @@ -10,6 +10,17 @@ config NVME This option enables support for NVM Express devices. It supports basic functions of NVMe (read/write). +config NVME_APPLE + bool "Apple NVMe controller support" + select NVME + help + This option enables support for the NVMe storage + controller integrated on Apple SoCs. This controller + isn't PCI-based based and deviates from the NVMe + standard implementation in its implementation of + the command submission queue and the integration + of an NVMMU that needs to be managed. + config NVME_PCI bool "NVM Express PCI device support" depends on PCI diff --git a/drivers/nvme/Makefile b/drivers/nvme/Makefile index fad9724e17b..fa7b6194460 100644 --- a/drivers/nvme/Makefile +++ b/drivers/nvme/Makefile @@ -3,4 +3,5 @@ # Copyright (C) 2017, Bin Meng obj-y += nvme-uclass.o nvme.o nvme_show.o +obj-$(CONFIG_NVME_APPLE) += nvme_apple.o obj-$(CONFIG_NVME_PCI) += nvme_pci.o diff --git a/drivers/nvme/nvme_apple.c b/drivers/nvme/nvme_apple.c new file mode 100644 index 00000000000..d9d491c2be1 --- /dev/null +++ b/drivers/nvme/nvme_apple.c @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021 Mark Kettenis + */ + +#include +#include +#include +#include +#include "nvme.h" +#include + +#include +#include +#include + +/* ASC registers */ +#define REG_CPU_CTRL 0x0044 +#define REG_CPU_CTRL_RUN BIT(4) + +/* Apple NVMe registers */ +#define ANS_MAX_PEND_CMDS_CTRL 0x01210 +#define ANS_MAX_QUEUE_DEPTH 64 +#define ANS_BOOT_STATUS 0x01300 +#define ANS_BOOT_STATUS_OK 0xde71ce55 +#define ANS_MODESEL 0x01304 +#define ANS_UNKNOWN_CTRL 0x24008 +#define ANS_PRP_NULL_CHECK (1 << 11) +#define ANS_LINEAR_SQ_CTRL 0x24908 +#define ANS_LINEAR_SQ_CTRL_EN (1 << 0) +#define ANS_ASQ_DB 0x2490c +#define ANS_IOSQ_DB 0x24910 +#define ANS_NVMMU_NUM 0x28100 +#define ANS_NVMMU_BASE_ASQ 0x28108 +#define ANS_NVMMU_BASE_IOSQ 0x28110 +#define ANS_NVMMU_TCB_INVAL 0x28118 +#define ANS_NVMMU_TCB_STAT 0x28120 + +#define ANS_NVMMU_TCB_SIZE 0x4000 +#define ANS_NVMMU_TCB_PITCH 0x80 + +/* + * The Apple NVMe controller includes an IOMMU known as NVMMU. The + * NVMMU is programmed through an array of TCBs. These TCBs are paired + * with the corresponding slot in the submission queues and need to be + * configured with the command details before a command is allowed to + * execute. This is necessary even for commands that don't do DMA. + */ +struct ans_nvmmu_tcb { + u8 opcode; + u8 flags; + u8 slot; + u8 pad0; + u32 prpl_len; + u8 pad1[16]; + u64 prp1; + u64 prp2; +}; + +#define ANS_NVMMU_TCB_WRITE BIT(0) +#define ANS_NVMMU_TCB_READ BIT(1) + +struct apple_nvme_priv { + struct nvme_dev ndev; + void *base; /* NVMe registers */ + void *asc; /* ASC registers */ + struct reset_ctl_bulk resets; /* ASC reset */ + struct mbox_chan chan; + struct ans_nvmmu_tcb *tcbs[NVME_Q_NUM]; /* Submission queue TCBs */ + u32 __iomem *q_db[NVME_Q_NUM]; /* Submission queue doorbell */ +}; + +static int apple_nvme_setup_queue(struct nvme_queue *nvmeq) +{ + struct apple_nvme_priv *priv = + container_of(nvmeq->dev, struct apple_nvme_priv, ndev); + struct nvme_dev *dev = nvmeq->dev; + + switch (nvmeq->qid) { + case NVME_ADMIN_Q: + case NVME_IO_Q: + break; + default: + return -EINVAL; + } + + priv->tcbs[nvmeq->qid] = (void *)memalign(4096, ANS_NVMMU_TCB_SIZE); + memset((void *)priv->tcbs[nvmeq->qid], 0, ANS_NVMMU_TCB_SIZE); + + switch (nvmeq->qid) { + case NVME_ADMIN_Q: + priv->q_db[nvmeq->qid] = + ((void __iomem *)dev->bar) + ANS_ASQ_DB; + nvme_writeq((ulong)priv->tcbs[nvmeq->qid], + ((void __iomem *)dev->bar) + ANS_NVMMU_BASE_ASQ); + break; + case NVME_IO_Q: + priv->q_db[nvmeq->qid] = + ((void __iomem *)dev->bar) + ANS_IOSQ_DB; + nvme_writeq((ulong)priv->tcbs[nvmeq->qid], + ((void __iomem *)dev->bar) + ANS_NVMMU_BASE_IOSQ); + break; + } + + return 0; +} + +static void apple_nvme_submit_cmd(struct nvme_queue *nvmeq, + struct nvme_command *cmd) +{ + struct apple_nvme_priv *priv = + container_of(nvmeq->dev, struct apple_nvme_priv, ndev); + struct ans_nvmmu_tcb *tcb; + u16 tail = nvmeq->sq_tail; + + tcb = ((void *)priv->tcbs[nvmeq->qid]) + tail * ANS_NVMMU_TCB_PITCH; + memset(tcb, 0, sizeof(*tcb)); + tcb->opcode = cmd->common.opcode; + tcb->flags = ANS_NVMMU_TCB_WRITE | ANS_NVMMU_TCB_READ; + tcb->slot = tail; + tcb->prpl_len = cmd->rw.length; + tcb->prp1 = cmd->common.prp1; + tcb->prp2 = cmd->common.prp2; + + writel(tail, priv->q_db[nvmeq->qid]); +} + +static void apple_nvme_complete_cmd(struct nvme_queue *nvmeq, + struct nvme_command *cmd) +{ + struct apple_nvme_priv *priv = + container_of(nvmeq->dev, struct apple_nvme_priv, ndev); + struct ans_nvmmu_tcb *tcb; + u16 tail = nvmeq->sq_tail; + + tcb = ((void *)priv->tcbs[nvmeq->qid]) + tail * ANS_NVMMU_TCB_PITCH; + memset(tcb, 0, sizeof(*tcb)); + writel(tail, ((void __iomem *)nvmeq->dev->bar) + ANS_NVMMU_TCB_INVAL); + readl(((void __iomem *)nvmeq->dev->bar) + ANS_NVMMU_TCB_STAT); + + if (++tail == nvmeq->q_depth) + tail = 0; + nvmeq->sq_tail = tail; +} + +static int apple_nvme_probe(struct udevice *dev) +{ + struct apple_nvme_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + u32 ctrl, stat; + int ret; + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -EINVAL; + + addr = dev_read_addr_index(dev, 1); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + priv->asc = map_sysmem(addr, 0); + + ret = reset_get_bulk(dev, &priv->resets); + if (ret < 0) + return ret; + + ret = mbox_get_by_index(dev, 0, &priv->chan); + if (ret < 0) + return ret; + + ctrl = readl(priv->asc + REG_CPU_CTRL); + writel(ctrl | REG_CPU_CTRL_RUN, priv->asc + REG_CPU_CTRL); + + ret = apple_rtkit_init(&priv->chan); + if (ret < 0) + return ret; + + ret = readl_poll_sleep_timeout(priv->base + ANS_BOOT_STATUS, stat, + (stat == ANS_BOOT_STATUS_OK), 100, + 500000); + if (ret < 0) { + printf("%s: NVMe firmware didn't boot\n", __func__); + return -ETIMEDOUT; + } + + writel(ANS_LINEAR_SQ_CTRL_EN, priv->base + ANS_LINEAR_SQ_CTRL); + writel(((ANS_MAX_QUEUE_DEPTH << 16) | ANS_MAX_QUEUE_DEPTH), + priv->base + ANS_MAX_PEND_CMDS_CTRL); + + writel(readl(priv->base + ANS_UNKNOWN_CTRL) & ~ANS_PRP_NULL_CHECK, + priv->base + ANS_UNKNOWN_CTRL); + + strcpy(priv->ndev.vendor, "Apple"); + + writel((ANS_NVMMU_TCB_SIZE / ANS_NVMMU_TCB_PITCH) - 1, + priv->base + ANS_NVMMU_NUM); + writel(0, priv->base + ANS_MODESEL); + + priv->ndev.bar = priv->base; + return nvme_init(dev); +} + +static int apple_nvme_remove(struct udevice *dev) +{ + struct apple_nvme_priv *priv = dev_get_priv(dev); + u32 ctrl; + + nvme_shutdown(dev); + + apple_rtkit_shutdown(&priv->chan, APPLE_RTKIT_PWR_STATE_SLEEP); + + ctrl = readl(priv->asc + REG_CPU_CTRL); + writel(ctrl & ~REG_CPU_CTRL_RUN, priv->asc + REG_CPU_CTRL); + + reset_assert_bulk(&priv->resets); + reset_deassert_bulk(&priv->resets); + + return 0; +} + +static const struct nvme_ops apple_nvme_ops = { + .setup_queue = apple_nvme_setup_queue, + .submit_cmd = apple_nvme_submit_cmd, + .complete_cmd = apple_nvme_complete_cmd, +}; + +static const struct udevice_id apple_nvme_ids[] = { + { .compatible = "apple,nvme-ans2" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(apple_nvme) = { + .name = "apple_nvme", + .id = UCLASS_NVME, + .of_match = apple_nvme_ids, + .priv_auto = sizeof(struct apple_nvme_priv), + .probe = apple_nvme_probe, + .remove = apple_nvme_remove, + .ops = &apple_nvme_ops, + .flags = DM_FLAG_OS_PREPARE, +}; From dbb273a5b6c02fd5a191ce4c059c596439a839fe Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Sat, 22 Jan 2022 20:38:19 +0100 Subject: [PATCH 09/15] configs: apple: Add NVMe boot target Add a boot target for NVMe such that we can boot from NVMe. Signed-off-by: Mark Kettenis --- include/configs/apple.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/configs/apple.h b/include/configs/apple.h index 3e5fb495f1a..47faad81509 100644 --- a/include/configs/apple.h +++ b/include/configs/apple.h @@ -13,6 +13,12 @@ "fdt_addr_r=0x960100000\0" \ "kernel_addr_r=0x960200000\0" +#if CONFIG_IS_ENABLED(CMD_NVME) + #define BOOT_TARGET_NVME(func) func(NVME, nvme, 0) +#else + #define BOOT_TARGET_NVME(func) +#endif + #if CONFIG_IS_ENABLED(CMD_USB) #define BOOT_TARGET_USB(func) func(USB, usb, 0) #else @@ -20,6 +26,7 @@ #endif #define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_NVME(func) \ BOOT_TARGET_USB(func) #include From 7184e2997e7d97ba3e697a0acc1800ddd89d3f6d Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Sun, 23 Jan 2022 16:48:12 +0100 Subject: [PATCH 10/15] spi: apple: Add driver for Apple SPI controller Add a driver for the SPI controller integrated on Apple SoCs. This is necessary to support the keyboard on Apple Silicon laopts since their keyboard uses an Apple-specific HID over SPI protocol. Signed-off-by: Mark Kettenis Reviewed-by: Simon Glass Tested on: Macbook Air M1 Tested-by: Simon Glass --- arch/arm/Kconfig | 2 + drivers/spi/Kconfig | 7 + drivers/spi/Makefile | 1 + drivers/spi/apple_spi.c | 285 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 295 insertions(+) create mode 100644 drivers/spi/apple_spi.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5048d3d33c4..80533943896 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -934,6 +934,7 @@ config ARCH_APPLE select DM_MAILBOX select DM_RESET select DM_SERIAL + select DM_SPI select DM_USB select DM_VIDEO select IOMMU @@ -943,6 +944,7 @@ config ARCH_APPLE select POSITION_INDEPENDENT select POWER_DOMAIN select REGMAP + select SPI select SYSCON select SYSRESET select SYSRESET_WATCHDOG diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index d07e9a28af8..0a6a85f9c48 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -50,6 +50,13 @@ config ALTERA_SPI IP core. Please find details on the "Embedded Peripherals IP User Guide" of Altera. +config APPLE_SPI + bool "Apple SPI driver" + default y if ARCH_APPLE + help + Enable the Apple SPI driver. This driver can be used to + access the SPI flash and keyboard on machines based on Apple SoCs. + config ATCSPI200_SPI bool "Andestech ATCSPI200 SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index d2f24bccefd..bea746f3e3e 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_SPI_MEM) += spi-mem-nodm.o endif obj-$(CONFIG_ALTERA_SPI) += altera_spi.o +obj-$(CONFIG_APPLE_SPI) += apple_spi.o obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_QSPI) += atmel-quadspi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o diff --git a/drivers/spi/apple_spi.c b/drivers/spi/apple_spi.c new file mode 100644 index 00000000000..f35f5af1f6f --- /dev/null +++ b/drivers/spi/apple_spi.c @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 Mark Kettenis + * Copyright The Asahi Linux Contributors + */ + +#include +#include +#include +#include +#include +#include +#include + +#define APPLE_SPI_CTRL 0x000 +#define APPLE_SPI_CTRL_RUN BIT(0) +#define APPLE_SPI_CTRL_TX_RESET BIT(2) +#define APPLE_SPI_CTRL_RX_RESET BIT(3) + +#define APPLE_SPI_CFG 0x004 +#define APPLE_SPI_CFG_CPHA BIT(1) +#define APPLE_SPI_CFG_CPOL BIT(2) +#define APPLE_SPI_CFG_MODE GENMASK(6, 5) +#define APPLE_SPI_CFG_MODE_POLLED 0 +#define APPLE_SPI_CFG_MODE_IRQ 1 +#define APPLE_SPI_CFG_MODE_DMA 2 +#define APPLE_SPI_CFG_IE_RXCOMPLETE BIT(7) +#define APPLE_SPI_CFG_IE_TXRXTHRESH BIT(8) +#define APPLE_SPI_CFG_LSB_FIRST BIT(13) +#define APPLE_SPI_CFG_WORD_SIZE GENMASK(16, 15) +#define APPLE_SPI_CFG_WORD_SIZE_8B 0 +#define APPLE_SPI_CFG_WORD_SIZE_16B 1 +#define APPLE_SPI_CFG_WORD_SIZE_32B 2 +#define APPLE_SPI_CFG_FIFO_THRESH GENMASK(18, 17) +#define APPLE_SPI_CFG_FIFO_THRESH_8B 0 +#define APPLE_SPI_CFG_FIFO_THRESH_4B 1 +#define APPLE_SPI_CFG_FIFO_THRESH_1B 2 +#define APPLE_SPI_CFG_IE_TXCOMPLETE BIT(21) + +#define APPLE_SPI_STATUS 0x008 +#define APPLE_SPI_STATUS_RXCOMPLETE BIT(0) +#define APPLE_SPI_STATUS_TXRXTHRESH BIT(1) +#define APPLE_SPI_STATUS_TXCOMPLETE BIT(2) + +#define APPLE_SPI_PIN 0x00c +#define APPLE_SPI_PIN_KEEP_MOSI BIT(0) +#define APPLE_SPI_PIN_CS BIT(1) + +#define APPLE_SPI_TXDATA 0x010 +#define APPLE_SPI_RXDATA 0x020 +#define APPLE_SPI_CLKDIV 0x030 +#define APPLE_SPI_CLKDIV_MIN 0x002 +#define APPLE_SPI_CLKDIV_MAX 0x7ff +#define APPLE_SPI_RXCNT 0x034 +#define APPLE_SPI_WORD_DELAY 0x038 +#define APPLE_SPI_TXCNT 0x04c + +#define APPLE_SPI_FIFOSTAT 0x10c +#define APPLE_SPI_FIFOSTAT_TXFULL BIT(4) +#define APPLE_SPI_FIFOSTAT_LEVEL_TX GENMASK(15, 8) +#define APPLE_SPI_FIFOSTAT_RXEMPTY BIT(20) +#define APPLE_SPI_FIFOSTAT_LEVEL_RX GENMASK(31, 24) + +#define APPLE_SPI_IE_XFER 0x130 +#define APPLE_SPI_IF_XFER 0x134 +#define APPLE_SPI_XFER_RXCOMPLETE BIT(0) +#define APPLE_SPI_XFER_TXCOMPLETE BIT(1) + +#define APPLE_SPI_IE_FIFO 0x138 +#define APPLE_SPI_IF_FIFO 0x13c +#define APPLE_SPI_FIFO_RXTHRESH BIT(4) +#define APPLE_SPI_FIFO_TXTHRESH BIT(5) +#define APPLE_SPI_FIFO_RXFULL BIT(8) +#define APPLE_SPI_FIFO_TXEMPTY BIT(9) +#define APPLE_SPI_FIFO_RXUNDERRUN BIT(16) +#define APPLE_SPI_FIFO_TXOVERFLOW BIT(17) + +#define APPLE_SPI_SHIFTCFG 0x150 +#define APPLE_SPI_SHIFTCFG_CLK_ENABLE BIT(0) +#define APPLE_SPI_SHIFTCFG_CS_ENABLE BIT(1) +#define APPLE_SPI_SHIFTCFG_AND_CLK_DATA BIT(8) +#define APPLE_SPI_SHIFTCFG_CS_AS_DATA BIT(9) +#define APPLE_SPI_SHIFTCFG_TX_ENABLE BIT(10) +#define APPLE_SPI_SHIFTCFG_RX_ENABLE BIT(11) +#define APPLE_SPI_SHIFTCFG_BITS GENMASK(21, 16) +#define APPLE_SPI_SHIFTCFG_OVERRIDE_CS BIT(24) + +#define APPLE_SPI_PINCFG 0x154 +#define APPLE_SPI_PINCFG_KEEP_CLK BIT(0) +#define APPLE_SPI_PINCFG_KEEP_CS BIT(1) +#define APPLE_SPI_PINCFG_KEEP_MOSI BIT(2) +#define APPLE_SPI_PINCFG_CLK_IDLE_VAL BIT(8) +#define APPLE_SPI_PINCFG_CS_IDLE_VAL BIT(9) +#define APPLE_SPI_PINCFG_MOSI_IDLE_VAL BIT(10) + +#define APPLE_SPI_DELAY_PRE 0x160 +#define APPLE_SPI_DELAY_POST 0x168 +#define APPLE_SPI_DELAY_ENABLE BIT(0) +#define APPLE_SPI_DELAY_NO_INTERBYTE BIT(1) +#define APPLE_SPI_DELAY_SET_SCK BIT(4) +#define APPLE_SPI_DELAY_SET_MOSI BIT(6) +#define APPLE_SPI_DELAY_SCK_VAL BIT(8) +#define APPLE_SPI_DELAY_MOSI_VAL BIT(12) + +#define APPLE_SPI_FIFO_DEPTH 16 + +#define APPLE_SPI_TIMEOUT_MS 200 + +struct apple_spi_priv { + void *base; + u32 clkfreq; /* Input clock frequency */ +}; + +static void apple_spi_set_cs(struct apple_spi_priv *priv, int on) +{ + writel(on ? 0 : APPLE_SPI_PIN_CS, priv->base + APPLE_SPI_PIN); +} + +/* Fill Tx FIFO. */ +static void apple_spi_tx(struct apple_spi_priv *priv, uint *len, + const void **dout) +{ + const u8 *out = *dout; + u32 data, fifostat; + uint count; + + fifostat = readl(priv->base + APPLE_SPI_FIFOSTAT); + count = APPLE_SPI_FIFO_DEPTH - + FIELD_GET(APPLE_SPI_FIFOSTAT_LEVEL_TX, fifostat); + while (*len > 0 && count > 0) { + data = out ? *out++ : 0; + writel(data, priv->base + APPLE_SPI_TXDATA); + (*len)--; + count--; + } + + *dout = out; +} + +/* Empty Rx FIFO. */ +static void apple_spi_rx(struct apple_spi_priv *priv, uint *len, + void **din) +{ + u8 *in = *din; + u32 data, fifostat; + uint count; + + fifostat = readl(priv->base + APPLE_SPI_FIFOSTAT); + count = FIELD_GET(APPLE_SPI_FIFOSTAT_LEVEL_RX, fifostat); + while (*len > 0 && count > 0) { + data = readl(priv->base + APPLE_SPI_RXDATA); + if (in) + *in++ = data; + (*len)--; + count--; + } + + *din = in; +} + +static int apple_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct apple_spi_priv *priv = dev_get_priv(dev->parent); + unsigned long start = get_timer(0); + uint txlen, rxlen; + int ret = 0; + + if ((bitlen % 8) != 0) + return -EINVAL; + txlen = rxlen = bitlen / 8; + + if (flags & SPI_XFER_BEGIN) + apple_spi_set_cs(priv, 1); + + if (txlen > 0) { + /* Reset FIFOs */ + writel(APPLE_SPI_CTRL_RX_RESET | APPLE_SPI_CTRL_TX_RESET, + priv->base + APPLE_SPI_CTRL); + + /* Set the transfer length */ + writel(txlen, priv->base + APPLE_SPI_TXCNT); + writel(rxlen, priv->base + APPLE_SPI_RXCNT); + + /* Prime transmit FIFO */ + apple_spi_tx(priv, &txlen, &dout); + + /* Start transfer */ + writel(APPLE_SPI_CTRL_RUN, priv->base + APPLE_SPI_CTRL); + + while ((txlen > 0 || rxlen > 0)) { + apple_spi_rx(priv, &rxlen, &din); + apple_spi_tx(priv, &txlen, &dout); + + if (get_timer(start) > APPLE_SPI_TIMEOUT_MS) { + ret = -ETIMEDOUT; + break; + } + } + + /* Stop transfer. */ + writel(0, priv->base + APPLE_SPI_CTRL); + } + + if (flags & SPI_XFER_END) + apple_spi_set_cs(priv, 0); + + return ret; +} + +static int apple_spi_set_speed(struct udevice *dev, uint speed) +{ + struct apple_spi_priv *priv = dev_get_priv(dev); + u32 div; + + div = DIV_ROUND_UP(priv->clkfreq, speed); + if (div < APPLE_SPI_CLKDIV_MIN) + div = APPLE_SPI_CLKDIV_MIN; + if (div > APPLE_SPI_CLKDIV_MAX) + div = APPLE_SPI_CLKDIV_MAX; + + writel(div, priv->base + APPLE_SPI_CLKDIV); + + return 0; +} + +static int apple_spi_set_mode(struct udevice *bus, uint mode) +{ + return 0; +} + +struct dm_spi_ops apple_spi_ops = { + .xfer = apple_spi_xfer, + .set_speed = apple_spi_set_speed, + .set_mode = apple_spi_set_mode, +}; + +static int apple_spi_probe(struct udevice *dev) +{ + struct apple_spi_priv *priv = dev_get_priv(dev); + struct clk clkdev; + int ret; + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -EINVAL; + + ret = clk_get_by_index(dev, 0, &clkdev); + if (ret) + return ret; + priv->clkfreq = clk_get_rate(&clkdev); + + /* Set CS high (inactive) and disable override and auto-CS */ + writel(APPLE_SPI_PIN_CS, priv->base + APPLE_SPI_PIN); + writel(readl(priv->base + APPLE_SPI_SHIFTCFG) & ~APPLE_SPI_SHIFTCFG_OVERRIDE_CS, + priv->base + APPLE_SPI_SHIFTCFG); + writel((readl(priv->base + APPLE_SPI_PINCFG) & ~APPLE_SPI_PINCFG_CS_IDLE_VAL) | + APPLE_SPI_PINCFG_KEEP_CS, priv->base + APPLE_SPI_PINCFG); + + /* Reset FIFOs */ + writel(APPLE_SPI_CTRL_RX_RESET | APPLE_SPI_CTRL_TX_RESET, + priv->base + APPLE_SPI_CTRL); + + /* Configure defaults */ + writel(FIELD_PREP(APPLE_SPI_CFG_MODE, APPLE_SPI_CFG_MODE_IRQ) | + FIELD_PREP(APPLE_SPI_CFG_WORD_SIZE, APPLE_SPI_CFG_WORD_SIZE_8B) | + FIELD_PREP(APPLE_SPI_CFG_FIFO_THRESH, APPLE_SPI_CFG_FIFO_THRESH_8B), + priv->base + APPLE_SPI_CFG); + + return 0; +} + +static const struct udevice_id apple_spi_of_match[] = { + { .compatible = "apple,spi" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(apple_spi) = { + .name = "apple_spi", + .id = UCLASS_SPI, + .of_match = apple_spi_of_match, + .probe = apple_spi_probe, + .priv_auto = sizeof(struct apple_spi_priv), + .ops = &apple_spi_ops, +}; From d42f1074253505f4e129267faa0d34676ca54d1f Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Sun, 23 Jan 2022 16:48:13 +0100 Subject: [PATCH 11/15] input: apple: Add support for Apple SPI keyboard This driver adds support for the keyboard on Apple Silicon laptops. The controller for this keyboard sits on an SPI bus and uses an Apple-specific HID over SPI protocol. The packets sent by this controller for key presses and key releases are fairly simple and are decoded directly by the code in this driver and converted into standard Linux keycodes. The same controller handles the touchpad found on these laptops. Packets for touchpad events are simply ignored. Signed-off-by: Mark Kettenis Reviewed-by: Simon Glass Tested on: Macbook Air M1 Tested-by: Simon Glass --- configs/apple_m1_defconfig | 1 + drivers/input/Kconfig | 8 + drivers/input/Makefile | 1 + drivers/input/apple_spi_kbd.c | 271 ++++++++++++++++++++++++++++++++++ include/configs/apple.h | 2 +- 5 files changed, 282 insertions(+), 1 deletion(-) create mode 100644 drivers/input/apple_spi_kbd.c diff --git a/configs/apple_m1_defconfig b/configs/apple_m1_defconfig index 1528217b178..433cc623340 100644 --- a/configs/apple_m1_defconfig +++ b/configs/apple_m1_defconfig @@ -15,5 +15,6 @@ CONFIG_NVME_APPLE=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_KEYBOARD=y +CONFIG_APPLE_SPI_KEYB=y CONFIG_VIDEO_SIMPLE=y # CONFIG_GENERATE_SMBIOS_TABLE is not set diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index 0b753f37bf4..2718b3674a5 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -47,6 +47,14 @@ config KEYBOARD and is only used by novena. For new boards, use driver model instead. +config APPLE_SPI_KEYB + bool "Enable Apple SPI keyboard support" + depends on DM_KEYBOARD && DM_SPI + help + This adds a driver for the keyboards found on various + laptops based on Apple SoCs. These keyboards use an + Apple-specific HID-over-SPI protocol. + config CROS_EC_KEYB bool "Enable Chrome OS EC keyboard support" depends on INPUT diff --git a/drivers/input/Makefile b/drivers/input/Makefile index e440c921e4e..b1133f772f2 100644 --- a/drivers/input/Makefile +++ b/drivers/input/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_$(SPL_TPL_)DM_KEYBOARD) += input.o keyboard-uclass.o ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_APPLE_SPI_KEYB) += apple_spi_kbd.o obj-$(CONFIG_I8042_KEYB) += i8042.o obj-$(CONFIG_TEGRA_KEYBOARD) += input.o tegra-kbc.o obj-$(CONFIG_TWL4030_INPUT) += twl4030.o diff --git a/drivers/input/apple_spi_kbd.c b/drivers/input/apple_spi_kbd.c new file mode 100644 index 00000000000..7cf12f453a3 --- /dev/null +++ b/drivers/input/apple_spi_kbd.c @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 Mark Kettenis + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * The Apple SPI keyboard controller implements a protocol that + * closely resembles HID Keyboard Boot protocol. The key codes are + * mapped according to the HID Keyboard/Keypad Usage Table. + */ + +/* Modifier key bits */ +#define HID_MOD_LEFTCTRL BIT(0) +#define HID_MOD_LEFTSHIFT BIT(1) +#define HID_MOD_LEFTALT BIT(2) +#define HID_MOD_LEFTGUI BIT(3) +#define HID_MOD_RIGHTCTRL BIT(4) +#define HID_MOD_RIGHTSHIFT BIT(5) +#define HID_MOD_RIGHTALT BIT(6) +#define HID_MOD_RIGHTGUI BIT(7) + +static const u8 hid_kbd_keymap[] = { + KEY_RESERVED, 0xff, 0xff, 0xff, + KEY_A, KEY_B, KEY_C, KEY_D, + KEY_E, KEY_F, KEY_G, KEY_H, + KEY_I, KEY_J, KEY_K, KEY_L, + KEY_M, KEY_N, KEY_O, KEY_P, + KEY_Q, KEY_R, KEY_S, KEY_T, + KEY_U, KEY_V, KEY_W, KEY_X, + KEY_Y, KEY_Z, KEY_1, KEY_2, + KEY_3, KEY_4, KEY_5, KEY_6, + KEY_7, KEY_8, KEY_9, KEY_0, + KEY_ENTER, KEY_ESC, KEY_BACKSPACE, KEY_TAB, + KEY_SPACE, KEY_MINUS, KEY_EQUAL, KEY_LEFTBRACE, + KEY_RIGHTBRACE, KEY_BACKSLASH, 0xff, KEY_SEMICOLON, + KEY_APOSTROPHE, KEY_GRAVE, KEY_COMMA, KEY_DOT, + KEY_SLASH, KEY_CAPSLOCK, KEY_F1, KEY_F2, + KEY_F3, KEY_F4, KEY_F5, KEY_F6, + KEY_F7, KEY_F8, KEY_F9, KEY_F10, + KEY_F11, KEY_F12, KEY_SYSRQ, KEY_SCROLLLOCK, + KEY_PAUSE, KEY_INSERT, KEY_HOME, KEY_PAGEUP, + KEY_DELETE, KEY_END, KEY_PAGEDOWN, KEY_RIGHT, + KEY_LEFT, KEY_DOWN, KEY_UP, KEY_NUMLOCK, + KEY_KPSLASH, KEY_KPASTERISK, KEY_KPMINUS, KEY_KPPLUS, + KEY_KPENTER, KEY_KP1, KEY_KP2, KEY_KP3, + KEY_KP4, KEY_KP5, KEY_KP6, KEY_KP7, + KEY_KP8, KEY_KP9, KEY_KP0, KEY_KPDOT, + KEY_BACKSLASH, KEY_COMPOSE, KEY_POWER, KEY_KPEQUAL, +}; + +/* Report ID used for keyboard input reports. */ +#define KBD_REPORTID 0x01 + +struct apple_spi_kbd_report { + u8 reportid; + u8 modifiers; + u8 reserved; + u8 keycode[6]; + u8 fn; +}; + +struct apple_spi_kbd_priv { + struct gpio_desc enable; + struct apple_spi_kbd_report old; /* previous keyboard input report */ + struct apple_spi_kbd_report new; /* current keyboard input report */ +}; + +/* Keyboard device. */ +#define KBD_DEVICE 0x01 + +/* The controller sends us fixed-size packets of 256 bytes. */ +struct apple_spi_kbd_packet { + u8 flags; +#define PACKET_READ 0x20 + u8 device; + u16 offset; + u16 remaining; + u16 len; + u8 data[246]; + u16 crc; +}; + +/* Packets contain a single variable-sized message. */ +struct apple_spi_kbd_msg { + u8 type; +#define MSG_REPORT 0x10 + u8 device; + u8 unknown; + u8 msgid; + u16 rsplen; + u16 cmdlen; + u8 data[0]; +}; + +static void apple_spi_kbd_service_modifiers(struct input_config *input) +{ + struct apple_spi_kbd_priv *priv = dev_get_priv(input->dev); + u8 new = priv->new.modifiers; + u8 old = priv->old.modifiers; + + if ((new ^ old) & HID_MOD_LEFTCTRL) + input_add_keycode(input, KEY_LEFTCTRL, + old & HID_MOD_LEFTCTRL); + if ((new ^ old) & HID_MOD_RIGHTCTRL) + input_add_keycode(input, KEY_RIGHTCTRL, + old & HID_MOD_RIGHTCTRL); + if ((new ^ old) & HID_MOD_LEFTSHIFT) + input_add_keycode(input, KEY_LEFTSHIFT, + old & HID_MOD_LEFTSHIFT); + if ((new ^ old) & HID_MOD_RIGHTSHIFT) + input_add_keycode(input, KEY_RIGHTSHIFT, + old & HID_MOD_RIGHTSHIFT); + if ((new ^ old) & HID_MOD_LEFTALT) + input_add_keycode(input, KEY_LEFTALT, + old & HID_MOD_LEFTALT); + if ((new ^ old) & HID_MOD_RIGHTALT) + input_add_keycode(input, KEY_RIGHTALT, + old & HID_MOD_RIGHTALT); + if ((new ^ old) & HID_MOD_LEFTGUI) + input_add_keycode(input, KEY_LEFTMETA, + old & HID_MOD_LEFTGUI); + if ((new ^ old) & HID_MOD_RIGHTGUI) + input_add_keycode(input, KEY_RIGHTMETA, + old & HID_MOD_RIGHTGUI); +} + +static void apple_spi_kbd_service_key(struct input_config *input, int i, + int released) +{ + struct apple_spi_kbd_priv *priv = dev_get_priv(input->dev); + u8 *new; + u8 *old; + + if (released) { + new = priv->new.keycode; + old = priv->old.keycode; + } else { + new = priv->old.keycode; + old = priv->new.keycode; + } + + if (memscan(new, old[i], sizeof(priv->new.keycode)) == + new + sizeof(priv->new.keycode) && + old[i] < ARRAY_SIZE(hid_kbd_keymap)) + input_add_keycode(input, hid_kbd_keymap[old[i]], released); +} + +static int apple_spi_kbd_check(struct input_config *input) +{ + struct udevice *dev = input->dev; + struct apple_spi_kbd_priv *priv = dev_get_priv(dev); + struct apple_spi_kbd_packet packet; + struct apple_spi_kbd_msg *msg; + struct apple_spi_kbd_report *report; + int i, ret; + + memset(&packet, 0, sizeof(packet)); + + ret = dm_spi_claim_bus(dev); + if (ret < 0) + return ret; + + /* + * The keyboard controller needs delays after asserting CS# + * and before deasserting CS#. + */ + ret = dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_BEGIN); + if (ret < 0) + goto fail; + udelay(100); + ret = dm_spi_xfer(dev, sizeof(packet) * 8, NULL, &packet, 0); + if (ret < 0) + goto fail; + udelay(100); + ret = dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END); + if (ret < 0) + goto fail; + + dm_spi_release_bus(dev); + + /* + * The keyboard controller needs a delay between subsequent + * SPI transfers. + */ + udelay(250); + + msg = (struct apple_spi_kbd_msg *)packet.data; + report = (struct apple_spi_kbd_report *)msg->data; + if (packet.flags == PACKET_READ && packet.device == KBD_DEVICE && + msg->type == MSG_REPORT && msg->device == KBD_DEVICE && + msg->cmdlen == sizeof(struct apple_spi_kbd_report) && + report->reportid == KBD_REPORTID) { + memcpy(&priv->new, report, + sizeof(struct apple_spi_kbd_report)); + apple_spi_kbd_service_modifiers(input); + for (i = 0; i < sizeof(priv->new.keycode); i++) { + apple_spi_kbd_service_key(input, i, 1); + apple_spi_kbd_service_key(input, i, 0); + } + memcpy(&priv->old, &priv->new, + sizeof(struct apple_spi_kbd_report)); + return 1; + } + + return 0; + +fail: + /* + * Make sure CS# is deasserted. If this fails there is nothing + * we can do, so ignore any errors. + */ + dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END); + dm_spi_release_bus(dev); + return ret; +} + +static int apple_spi_kbd_probe(struct udevice *dev) +{ + struct apple_spi_kbd_priv *priv = dev_get_priv(dev); + struct keyboard_priv *uc_priv = dev_get_uclass_priv(dev); + struct stdio_dev *sdev = &uc_priv->sdev; + struct input_config *input = &uc_priv->input; + int ret; + + ret = gpio_request_by_name(dev, "spien-gpios", 0, &priv->enable, + GPIOD_IS_OUT); + if (ret < 0) + return ret; + + /* Reset the keyboard controller. */ + dm_gpio_set_value(&priv->enable, 1); + udelay(5000); + dm_gpio_set_value(&priv->enable, 0); + udelay(5000); + + /* Enable the keyboard controller. */ + dm_gpio_set_value(&priv->enable, 1); + + input->dev = dev; + input->read_keys = apple_spi_kbd_check; + input_add_tables(input, false); + strcpy(sdev->name, "spikbd"); + + return input_stdio_register(sdev); +} + +static const struct keyboard_ops apple_spi_kbd_ops = { +}; + +static const struct udevice_id apple_spi_kbd_of_match[] = { + { .compatible = "apple,spi-hid-transport" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(apple_spi_kbd) = { + .name = "apple_spi_kbd", + .id = UCLASS_KEYBOARD, + .of_match = apple_spi_kbd_of_match, + .probe = apple_spi_kbd_probe, + .priv_auto = sizeof(struct apple_spi_kbd_priv), + .ops = &apple_spi_kbd_ops, +}; diff --git a/include/configs/apple.h b/include/configs/apple.h index 47faad81509..f12e9bdef5a 100644 --- a/include/configs/apple.h +++ b/include/configs/apple.h @@ -5,7 +5,7 @@ /* Environment */ #define ENV_DEVICE_SETTINGS \ - "stdin=serial,usbkbd\0" \ + "stdin=serial,usbkbd,spikbd\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" From 6303b275a3424dc1b6c79e98ac575ab2c88659eb Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Mon, 31 Jan 2022 09:20:21 +0200 Subject: [PATCH 12/15] powerpc: mpc8xx: drop CONFIG_SYS_RESET_ADDRESS There are no boards that define CONFIG_SYS_RESET_ADDRESS, so drop the associated mpc8xx code that checks for it. Signed-off-by: Ovidiu Panait Reviewed-by: Stefan Roese Acked-by: Christophe Leroy --- arch/powerpc/cpu/mpc8xx/cpu.c | 11 ++--------- scripts/config_whitelist.txt | 1 - 2 files changed, 2 insertions(+), 10 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c index 893aecef21c..6d16ed084e6 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu.c +++ b/arch/powerpc/cpu/mpc8xx/cpu.c @@ -215,19 +215,12 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) /* * Trying to execute the next instruction at a non-existing address * should cause a machine check, resulting in reset - */ -#ifdef CONFIG_SYS_RESET_ADDRESS - addr = CONFIG_SYS_RESET_ADDRESS; -#else - /* + * * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid address. - * Better pick an address known to be invalid on your system and assign - * it to CONFIG_SYS_RESET_ADDRESS. - * "(ulong)-1" used to be a good choice for many systems... */ addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong); -#endif + ((void (*)(void)) addr)(); return 1; } diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 6b21e3918d1..d0adcf7b125 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1823,7 +1823,6 @@ CONFIG_SYS_RCAR_I2C1_BASE CONFIG_SYS_RCAR_I2C2_BASE CONFIG_SYS_RCAR_I2C3_BASE CONFIG_SYS_RESET_ADDR -CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_RFD CONFIG_SYS_RGMII1_PHY_ADDR CONFIG_SYS_RGMII2_PHY_ADDR From 1ca890d789b45ddcda73454fe2b54f5fdb10ee3b Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Mon, 31 Jan 2022 09:20:22 +0200 Subject: [PATCH 13/15] common: drop CONFIG_SYS_RESET_ADDR There are no boards that define CONFIG_SYS_RESET_ADDR, so drop the remaining comments referencing it and also the config_whitelist.txt entry. Signed-off-by: Ovidiu Panait Reviewed-by: Stefan Roese Acked-by: thomas@wytron.com.tw --- include/configs/10m50_devboard.h | 9 --------- include/configs/3c120_devboard.h | 9 --------- scripts/config_whitelist.txt | 1 - 3 files changed, 19 deletions(-) diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h index 04ce88c9dd9..3b4d1fd6265 100644 --- a/include/configs/10m50_devboard.h +++ b/include/configs/10m50_devboard.h @@ -47,13 +47,4 @@ CONFIG_SYS_SDRAM_SIZE - \ CONFIG_SYS_MONITOR_LEN) -/* - * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above - * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the - * reset address, no? This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - */ - - #endif /* __CONFIG_H */ diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h index e12e54fe4fb..763cb8db7cf 100644 --- a/include/configs/3c120_devboard.h +++ b/include/configs/3c120_devboard.h @@ -47,13 +47,4 @@ CONFIG_SYS_SDRAM_SIZE - \ CONFIG_SYS_MONITOR_LEN) -/* - * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above - * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the - * reset address, no? This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - */ - - #endif /* __CONFIG_H */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index d0adcf7b125..a6bc234f51e 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1822,7 +1822,6 @@ CONFIG_SYS_RCAR_I2C0_BASE CONFIG_SYS_RCAR_I2C1_BASE CONFIG_SYS_RCAR_I2C2_BASE CONFIG_SYS_RCAR_I2C3_BASE -CONFIG_SYS_RESET_ADDR CONFIG_SYS_RFD CONFIG_SYS_RGMII1_PHY_ADDR CONFIG_SYS_RGMII2_PHY_ADDR From a1ad6a94a1bf92ea64297e698ad76a32ae02d6cc Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Sun, 6 Feb 2022 13:21:14 +0100 Subject: [PATCH 14/15] apple: Fix debug uart clock rate The clock rate for the serial console on Apple M1 systems is 24 MHz instead of 240 kHz. Signed-off-by: Mark Kettenis --- configs/apple_m1_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/apple_m1_defconfig b/configs/apple_m1_defconfig index 433cc623340..8583e4ad8c7 100644 --- a/configs/apple_m1_defconfig +++ b/configs/apple_m1_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_APPLE=y CONFIG_DEFAULT_DEVICE_TREE="t8103-j274" CONFIG_DEBUG_UART_BASE=0x235200000 -CONFIG_DEBUG_UART_CLOCK=240000 +CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_SYS_LOAD_ADDR=0x880000000 CONFIG_USE_PREBOOT=y From ad41ed120893522e23cc24550bb2d1dfb745a075 Mon Sep 17 00:00:00 2001 From: Sinthu Raja Date: Mon, 29 Nov 2021 17:34:49 +0530 Subject: [PATCH 15/15] arm:dts:k3-am64-sk: EMIF tool update to 0.8.0 with 1333MTs for lpddr4 EMIF tool for AM64 SK is now updated to 0.8.0 that includes * disabled Write DQ training * improve CA ODT to 60 ohms The lpddr4 enabled with periodic WDQ training is causing periodic 26us stall. This makes the SoC stall without doing anything which leads to R5 interrupt latency in TCM memory. Due to this periodic training there are some outstanding CPU transactions waiting for the lpddr4 to complete. Hence, disable the periodic write DQ training during the non-initialization stage of lpddr4 which results in an approximate 1us stall. Also, update the lpddr4 config to improve CA ODT by 60 ohms The rationales are as follows: - PI_WDQLVL_EN: 2 Bits register field to support write DQ leveling, disable bit 1 that supports Write DQ during non-initialization to avoid ~26us stall during code execution. - MR11_DATA_F1/F2_x register fields value changed to 0x66 that changes the CA ODT from 48ohm to 60ohm to improve the eye margin on CA bus by increasing the signal swing. Signed-off-by: James Doublesin Signed-off-by: Sinthu Raja --- arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi | 28 ++++++++++++------------ 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi b/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi index 64a159f6d01..dde5ab150da 100644 --- a/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi +++ b/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi @@ -2,8 +2,8 @@ /* * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ * This file was generated with the - * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.06.00 - * Mon Apr 26 2021 20:47:47 GMT-0500 (Central Daylight Time) + * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.00 + * Wed Oct 13 2021 10:08:29 GMT-0500 (Central Daylight Time) * DDR Type: LPDDR4 * F0 = 50MHz F1 = 666.7MHz F2 = 666.7MHz * Density (per channel): 16Gb @@ -268,8 +268,8 @@ #define DDRSS_CTL_251_DATA 0x00000000 #define DDRSS_CTL_252_DATA 0x00000000 #define DDRSS_CTL_253_DATA 0x00000000 -#define DDRSS_CTL_254_DATA 0x66006666 -#define DDRSS_CTL_255_DATA 0x00002766 +#define DDRSS_CTL_254_DATA 0x46004646 +#define DDRSS_CTL_255_DATA 0x00002746 #define DDRSS_CTL_256_DATA 0x00000027 #define DDRSS_CTL_257_DATA 0x00000027 #define DDRSS_CTL_258_DATA 0x00000027 @@ -660,13 +660,13 @@ #define DDRSS_PI_220_DATA 0x000000A7 #define DDRSS_PI_221_DATA 0x00001900 #define DDRSS_PI_222_DATA 0x32000056 -#define DDRSS_PI_223_DATA 0x06000301 +#define DDRSS_PI_223_DATA 0x06000101 #define DDRSS_PI_224_DATA 0x001D0204 #define DDRSS_PI_225_DATA 0x32120059 -#define DDRSS_PI_226_DATA 0x05000301 +#define DDRSS_PI_226_DATA 0x05000101 #define DDRSS_PI_227_DATA 0x001D0409 #define DDRSS_PI_228_DATA 0x32120059 -#define DDRSS_PI_229_DATA 0x05000301 +#define DDRSS_PI_229_DATA 0x05000101 #define DDRSS_PI_230_DATA 0x00000409 #define DDRSS_PI_231_DATA 0x05030900 #define DDRSS_PI_232_DATA 0x00040900 @@ -748,7 +748,7 @@ #define DDRSS_PI_308_DATA 0x00000031 #define DDRSS_PI_309_DATA 0x00000000 #define DDRSS_PI_310_DATA 0x00000000 -#define DDRSS_PI_311_DATA 0x66000000 +#define DDRSS_PI_311_DATA 0x46000000 #define DDRSS_PI_312_DATA 0x00150F27 #define DDRSS_PI_313_DATA 0x00000000 #define DDRSS_PI_314_DATA 0x00000024 @@ -756,7 +756,7 @@ #define DDRSS_PI_316_DATA 0x00000031 #define DDRSS_PI_317_DATA 0x00000000 #define DDRSS_PI_318_DATA 0x00000000 -#define DDRSS_PI_319_DATA 0x66000000 +#define DDRSS_PI_319_DATA 0x46000000 #define DDRSS_PI_320_DATA 0x00150F27 #define DDRSS_PI_321_DATA 0x00000000 #define DDRSS_PI_322_DATA 0x00000004 @@ -772,7 +772,7 @@ #define DDRSS_PI_332_DATA 0x00000031 #define DDRSS_PI_333_DATA 0x00000000 #define DDRSS_PI_334_DATA 0x00000000 -#define DDRSS_PI_335_DATA 0x66000000 +#define DDRSS_PI_335_DATA 0x46000000 #define DDRSS_PI_336_DATA 0x00150F27 #define DDRSS_PI_337_DATA 0x00000000 #define DDRSS_PI_338_DATA 0x00000024 @@ -780,7 +780,7 @@ #define DDRSS_PI_340_DATA 0x00000031 #define DDRSS_PI_341_DATA 0x00000000 #define DDRSS_PI_342_DATA 0x00000000 -#define DDRSS_PI_343_DATA 0x66000000 +#define DDRSS_PI_343_DATA 0x46000000 #define DDRSS_PI_344_DATA 0x00150F27 #define DDRSS_PHY_0_DATA 0x04F00000 #define DDRSS_PHY_1_DATA 0x00000000 @@ -873,7 +873,7 @@ #define DDRSS_PHY_88_DATA 0x51516041 #define DDRSS_PHY_89_DATA 0x31C06000 #define DDRSS_PHY_90_DATA 0x07AB0340 -#define DDRSS_PHY_91_DATA 0x0100C0C0 +#define DDRSS_PHY_91_DATA 0x0000C0C0 #define DDRSS_PHY_92_DATA 0x03040000 #define DDRSS_PHY_93_DATA 0x00000403 #define DDRSS_PHY_94_DATA 0x42100010 @@ -1129,7 +1129,7 @@ #define DDRSS_PHY_344_DATA 0x51516041 #define DDRSS_PHY_345_DATA 0x31C06000 #define DDRSS_PHY_346_DATA 0x07AB0340 -#define DDRSS_PHY_347_DATA 0x0100C0C0 +#define DDRSS_PHY_347_DATA 0x0000C0C0 #define DDRSS_PHY_348_DATA 0x03040000 #define DDRSS_PHY_349_DATA 0x00000403 #define DDRSS_PHY_350_DATA 0x42100010 @@ -2157,7 +2157,7 @@ #define DDRSS_PHY_1372_DATA 0x00000002 #define DDRSS_PHY_1373_DATA 0x00000000 #define DDRSS_PHY_1374_DATA 0x00001142 -#define DDRSS_PHY_1375_DATA 0x030207AB +#define DDRSS_PHY_1375_DATA 0x03020000 #define DDRSS_PHY_1376_DATA 0x00000080 #define DDRSS_PHY_1377_DATA 0x03900390 #define DDRSS_PHY_1378_DATA 0x03900390