mirrors/u-boot
1
0
Fork 0
mirror of https://source.denx.de/u-boot/u-boot.git synced 2025-08-23 07:31:27 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity

Merge branch '2023-01-10-platform-updates'

Browse Source 
- Platform updates for TI, nuvoton pinctrl, starqltechn/sdm845 fixes,
  and assorted platform CONFIG_BUILD_TARGET corrections
This commit is contained in:
Tom Rini 2023-01-10 21:13:57 -05:00
commit ee4f86cc04
51 changed files with 226 additions and 83 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
Kconfig
View File

@ -456,11 +456,12 @@ config BUILD_TARGET
string "Build target special images" string "Build target special images"
default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10 default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10
default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5 default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5
default "u-boot-with-spl.kwb" if ARCH_MVEBU && SPL default "u-boot-with-spl.kwb" if ARMADA_32BIT && SPL
default "u-boot-elf.srec" if RCAR_GEN3 default "u-boot-elf.srec" if RCAR_GEN3
default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \ default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \
ARCH_SUNXI || RISCV || ARCH_ZYNQMP) ARCH_SUNXI || RISCV || ARCH_ZYNQMP)
default "u-boot.kwb" if ARCH_KIRKWOOD default "u-boot.kwb" if (ARCH_KIRKWOOD || ARMADA_32BIT) && !SPL
default "u-boot-with-spl.bin" if MPC85xx && !E500MC && !E5500 && !E6500 && SPL
default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
default "u-boot-with-spl.imx" if ARCH_MX6 && SPL default "u-boot-with-spl.imx" if ARCH_MX6 && SPL
help help

22
arch/arm/dts/k3-am625-sk-u-boot.dtsi
View File

@ -126,3 +126,25 @@
}; };
}; };
}; };
&cpsw3g {
reg = <0x0 0x8000000 0x0 0x200000>,
<0x0 0x43000200 0x0 0x8>;
reg-names = "cpsw_nuss", "mac_efuse";
/delete-property/ ranges;
u-boot,dm-spl;
cpsw-phy-sel@04044 {
compatible = "ti,am64-phy-gmii-sel";
reg = <0x0 0x00104044 0x0 0x8>;
u-boot,dm-spl;
};
};
&cpsw_port1 {
u-boot,dm-spl;
};
&cpsw_port2 {
status = "disabled";
};

2
arch/arm/include/asm/arch-npcm8xx/rst.h
View File

@ -16,7 +16,7 @@
#define SW1RST BIT(28) #define SW1RST BIT(28)
#define SW2RST BIT(27) #define SW2RST BIT(27)
#define SW3RST BIT(26) #define SW3RST BIT(26)
#define SW4RST BIT(25) #define TIPRST BIT(25)
#define WD1RST BIT(24) #define WD1RST BIT(24)
#define WD2RST BIT(23) #define WD2RST BIT(23)
#define RST_STS_MASK GENMASK(31, 23) #define RST_STS_MASK GENMASK(31, 23)

4
arch/arm/mach-k3/Kconfig
View File

@ -69,7 +69,9 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
default 0x41cffbfc if SOC_K3_J721E default 0x41cffbfc if SOC_K3_J721E
default 0x41cfdbfc if SOC_K3_J721S2 default 0x41cfdbfc if SOC_K3_J721S2
default 0x701bebfc if SOC_K3_AM642 default 0x701bebfc if SOC_K3_AM642
default 0x43c3f290 if SOC_K3_AM625 || SOC_K3_AM62A7 default 0x43c3f290 if SOC_K3_AM625
default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R
default 0x7000f290 if SOC_K3_AM62A7 && ARM64
help help
Address at which ROM stores the value which determines if SPL Address at which ROM stores the value which determines if SPL
is booted up by primary boot media or secondary boot media. is booted up by primary boot media or secondary boot media.

19
arch/arm/mach-k3/am625_init.c
View File

@ -173,21 +173,20 @@ void board_init_f(ulong dummy)
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
{ {
u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
switch (boot_device) {
case BOOT_DEVICE_MMC1: switch (bootmode) {
if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK) >> case BOOT_DEVICE_EMMC:
MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT)
return MMCSD_MODE_EMMCBOOT; return MMCSD_MODE_EMMCBOOT;
return MMCSD_MODE_FS; case BOOT_DEVICE_MMC:
if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK)
case BOOT_DEVICE_MMC2:
return MMCSD_MODE_FS;
default:
return MMCSD_MODE_RAW; return MMCSD_MODE_RAW;
default:
return MMCSD_MODE_FS;
} }
} }

12
arch/arm/mach-k3/am62a7_init.c
View File

@ -25,9 +25,12 @@ static struct rom_extended_boot_data bootdata __section(".data");
static void store_boot_info_from_rom(void) static void store_boot_info_from_rom(void)
{ {
bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
if (IS_ENABLED(CONFIG_CPU_V7R)) {
memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO, memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO,
sizeof(struct rom_extended_boot_data)); sizeof(struct rom_extended_boot_data));
} }
}
static void ctrl_mmr_unlock(void) static void ctrl_mmr_unlock(void)
{ {
@ -123,6 +126,15 @@ void board_init_f(ulong dummy)
k3_sysfw_loader(true, NULL, NULL); k3_sysfw_loader(true, NULL, NULL);
#endif #endif
#if defined(CONFIG_CPU_V7R)
/*
* Relocate boot information to OCRAM (after TIFS has opend this
* region for us) so the next bootloader stages can keep access to
* primary vs backup bootmodes.
*/
writel(bootindex, K3_BOOT_PARAM_TABLE_INDEX_OCRAM);
#endif
/* /*
* Force probe of clk_k3 driver here to ensure basic default clock * Force probe of clk_k3 driver here to ensure basic default clock
* configuration is always done. * configuration is always done.

17
arch/arm/mach-k3/include/mach/am62a_hardware.h
View File

@ -68,7 +68,22 @@
#define ROM_ENTENDED_BOOT_DATA_INFO 0x43c3f1e0 #define ROM_ENTENDED_BOOT_DATA_INFO 0x43c3f1e0
/* Use Last 2K as Scratch pad */ #define K3_BOOT_PARAM_TABLE_INDEX_OCRAM 0x7000F290
/*
* During the boot process ROM will kill anything that writes to OCSRAM.
* This means the wakeup SPL cannot use this region during boot. To
* complicate things, TIFS will set a firewall between HSM RAM and the
* main domain.
*
* So, during the wakeup SPL, we will need to store the EEPROM data
* somewhere in HSM RAM, and the main domain's SPL will need to store it
* somewhere in OCSRAM
*/
#ifdef CONFIG_CPU_V7R
#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c30000
#else
#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x70000001 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x70000001
#endif /* CONFIG_CPU_V7R */
#endif /* __ASM_ARCH_AM62A_HARDWARE_H */ #endif /* __ASM_ARCH_AM62A_HARDWARE_H */

2
arch/arm/mach-omap2/omap3/Kconfig
View File

@ -163,7 +163,7 @@ config SYS_SOC
source "board/logicpd/am3517evm/Kconfig" source "board/logicpd/am3517evm/Kconfig"
source "board/ti/beagle/Kconfig" source "board/ti/beagle/Kconfig"
source "board/timll/devkit8000/Kconfig" source "board/timll/devkit8000/Kconfig"
source "board/ti/evm/Kconfig" source "board/ti/omap3evm/Kconfig"
source "board/isee/igep00x0/Kconfig" source "board/isee/igep00x0/Kconfig"
source "board/logicpd/omap3som/Kconfig" source "board/logicpd/omap3som/Kconfig"
source "board/nokia/rx51/Kconfig" source "board/nokia/rx51/Kconfig"

18
arch/arm/mach-snapdragon/init_sdm845.c
View File

@ -78,5 +78,23 @@ __weak int misc_init_r(void)
env_set("key_power", "0"); env_set("key_power", "0");
} }
/*
* search for kaslr address, set by primary bootloader by searching first
* 0x100 relocated bytes at u-boot's initial load address range
*/
uintptr_t start = gd->ram_base;
uintptr_t end = start + 0x800000;
u8 *addr = (u8 *)start;
phys_addr_t *relocaddr = (phys_addr_t *)gd->relocaddr;
u32 block_size = 0x1000;
while (memcmp(addr, relocaddr, 0x100) && (uintptr_t)addr < end)
addr += block_size;
if ((uintptr_t)addr >= end)
printf("KASLR not found in range 0x%lx - 0x%lx", start, end);
else
env_set_addr("KASLR", addr);
return 0; return 0;
} }

2
board/ti/evm/Kconfig → board/ti/omap3evm/Kconfig
View File

@ -1,7 +1,7 @@
if TARGET_OMAP3_EVM if TARGET_OMAP3_EVM
config SYS_BOARD config SYS_BOARD
default "evm" default "omap3evm"
config SYS_VENDOR config SYS_VENDOR
default "ti" default "ti"

2
board/ti/evm/MAINTAINERS → board/ti/omap3evm/MAINTAINERS
View File

@ -1,6 +1,6 @@
EVM BOARD EVM BOARD
M: Derald D. Woods <woods.technical@gmail.com> M: Derald D. Woods <woods.technical@gmail.com>
S: Maintained S: Maintained
F: board/ti/evm/ F: board/ti/omap3evm/
F: include/configs/omap3_evm.h F: include/configs/omap3_evm.h
F: configs/omap3_evm_defconfig F: configs/omap3_evm_defconfig

0
board/ti/evm/Makefile → board/ti/omap3evm/Makefile
View File

0
board/ti/evm/evm.c → board/ti/omap3evm/evm.c
View File

0
board/ti/evm/evm.h → board/ti/omap3evm/evm.h
View File

1
configs/P1010RDB-PA_36BIT_NAND_defconfig
View File

@ -51,7 +51,6 @@ CONFIG_TPL_RELOC_MALLOC=y
CONFIG_TPL_RELOC_MALLOC_ADDR=0xd0034000 CONFIG_TPL_RELOC_MALLOC_ADDR=0xd0034000
CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000 CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000
CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_TPL=y CONFIG_TPL=y
CONFIG_TPL_DRIVERS_MISC=y CONFIG_TPL_DRIVERS_MISC=y
CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_ENV_SUPPORT=y

1
configs/P1010RDB-PA_36BIT_SDCARD_defconfig
View File

@ -48,7 +48,6 @@ CONFIG_SPL_RELOC_MALLOC_SIZE=0x20000
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y CONFIG_CMD_IMLS=y

1
configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
View File

@ -50,7 +50,6 @@ CONFIG_SPL_RELOC_MALLOC_SIZE=0x20000
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y CONFIG_CMD_IMLS=y

1
configs/P1010RDB-PA_NAND_defconfig
View File

@ -50,7 +50,6 @@ CONFIG_TPL_RELOC_MALLOC=y
CONFIG_TPL_RELOC_MALLOC_ADDR=0xd0034000 CONFIG_TPL_RELOC_MALLOC_ADDR=0xd0034000
CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000 CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000
CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_TPL=y CONFIG_TPL=y
CONFIG_TPL_DRIVERS_MISC=y CONFIG_TPL_DRIVERS_MISC=y
CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_ENV_SUPPORT=y

1
configs/P1010RDB-PA_SDCARD_defconfig
View File

@ -47,7 +47,6 @@ CONFIG_SPL_RELOC_MALLOC_SIZE=0x20000
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y CONFIG_CMD_IMLS=y

1
configs/P1010RDB-PA_SPIFLASH_defconfig
View File

@ -49,7 +49,6 @@ CONFIG_SPL_RELOC_MALLOC_SIZE=0x20000
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y CONFIG_CMD_IMLS=y

1
configs/P1010RDB-PB_36BIT_NAND_defconfig
View File

@ -52,7 +52,6 @@ CONFIG_TPL_RELOC_MALLOC=y
CONFIG_TPL_RELOC_MALLOC_ADDR=0xd0034000 CONFIG_TPL_RELOC_MALLOC_ADDR=0xd0034000
CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000 CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000
CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_TPL=y CONFIG_TPL=y
CONFIG_TPL_DRIVERS_MISC=y CONFIG_TPL_DRIVERS_MISC=y
CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_ENV_SUPPORT=y

1
configs/P1010RDB-PB_36BIT_SDCARD_defconfig
View File

@ -49,7 +49,6 @@ CONFIG_SPL_RELOC_MALLOC_SIZE=0x20000
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y CONFIG_CMD_IMLS=y

1
configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
View File

@ -51,7 +51,6 @@ CONFIG_SPL_RELOC_MALLOC_SIZE=0x20000
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y CONFIG_CMD_IMLS=y

1
configs/P1010RDB-PB_NAND_defconfig
View File

@ -51,7 +51,6 @@ CONFIG_TPL_RELOC_MALLOC=y
CONFIG_TPL_RELOC_MALLOC_ADDR=0xd0034000 CONFIG_TPL_RELOC_MALLOC_ADDR=0xd0034000
CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000 CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000
CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_TPL=y CONFIG_TPL=y
CONFIG_TPL_DRIVERS_MISC=y CONFIG_TPL_DRIVERS_MISC=y
CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_ENV_SUPPORT=y

1
configs/P1010RDB-PB_SDCARD_defconfig
View File

@ -48,7 +48,6 @@ CONFIG_SPL_RELOC_MALLOC_SIZE=0x20000
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y CONFIG_CMD_IMLS=y

1
configs/P1010RDB-PB_SPIFLASH_defconfig
View File

@ -50,7 +50,6 @@ CONFIG_SPL_RELOC_MALLOC_SIZE=0x20000
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y CONFIG_CMD_IMLS=y

1
configs/P1020RDB-PC_36BIT_NAND_defconfig
View File

@ -52,7 +52,6 @@ CONFIG_TPL_RELOC_MALLOC=y
CONFIG_TPL_RELOC_MALLOC_ADDR=0xf8fb4000 CONFIG_TPL_RELOC_MALLOC_ADDR=0xf8fb4000
CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000 CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000
CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_TPL=y CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_ENV_SUPPORT=y
CONFIG_TPL_I2C=y CONFIG_TPL_I2C=y

1
configs/P1020RDB-PC_36BIT_SDCARD_defconfig
View File

@ -49,7 +49,6 @@ CONFIG_SPL_RELOC_MALLOC_SIZE=0x1b000
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set # CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276

1
configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
View File

@ -51,7 +51,6 @@ CONFIG_SPL_RELOC_MALLOC_SIZE=0x1b000
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set # CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276

1
configs/P1020RDB-PC_NAND_defconfig
View File

@ -51,7 +51,6 @@ CONFIG_TPL_RELOC_MALLOC=y
CONFIG_TPL_RELOC_MALLOC_ADDR=0xf8fb4000 CONFIG_TPL_RELOC_MALLOC_ADDR=0xf8fb4000
CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000 CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000
CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_TPL=y CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_ENV_SUPPORT=y
CONFIG_TPL_I2C=y CONFIG_TPL_I2C=y

1
configs/P1020RDB-PC_SDCARD_defconfig
View File

@ -48,7 +48,6 @@ CONFIG_SPL_RELOC_MALLOC_SIZE=0x1b000
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set # CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276

1
configs/P1020RDB-PC_SPIFLASH_defconfig
View File

@ -50,7 +50,6 @@ CONFIG_SPL_RELOC_MALLOC_SIZE=0x1b000
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set # CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276

1
configs/P1020RDB-PD_NAND_defconfig
View File

@ -51,7 +51,6 @@ CONFIG_TPL_RELOC_MALLOC=y
CONFIG_TPL_RELOC_MALLOC_ADDR=0xf8fb4000 CONFIG_TPL_RELOC_MALLOC_ADDR=0xf8fb4000
CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000 CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000
CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_TPL=y CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_ENV_SUPPORT=y
CONFIG_TPL_I2C=y CONFIG_TPL_I2C=y

1
configs/P1020RDB-PD_SDCARD_defconfig
View File

@ -48,7 +48,6 @@ CONFIG_SPL_RELOC_MALLOC_SIZE=0x1b000
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set # CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276

1
configs/P1020RDB-PD_SPIFLASH_defconfig
View File

@ -50,7 +50,6 @@ CONFIG_SPL_RELOC_MALLOC_SIZE=0x1b000
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set # CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276

1
configs/P2020RDB-PC_36BIT_NAND_defconfig
View File

@ -52,7 +52,6 @@ CONFIG_TPL_RELOC_MALLOC=y
CONFIG_TPL_RELOC_MALLOC_ADDR=0xf8fb4000 CONFIG_TPL_RELOC_MALLOC_ADDR=0xf8fb4000
CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000 CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000
CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_TPL=y CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_ENV_SUPPORT=y
CONFIG_TPL_I2C=y CONFIG_TPL_I2C=y

1
configs/P2020RDB-PC_36BIT_SDCARD_defconfig
View File

@ -49,7 +49,6 @@ CONFIG_SPL_RELOC_MALLOC_SIZE=0x5b000
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set # CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276

1
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
View File

@ -51,7 +51,6 @@ CONFIG_SPL_RELOC_MALLOC_SIZE=0x5b000
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set # CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276

1
configs/P2020RDB-PC_NAND_defconfig
View File

@ -51,7 +51,6 @@ CONFIG_TPL_RELOC_MALLOC=y
CONFIG_TPL_RELOC_MALLOC_ADDR=0xf8fb4000 CONFIG_TPL_RELOC_MALLOC_ADDR=0xf8fb4000
CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000 CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000
CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_TPL=y CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_ENV_SUPPORT=y
CONFIG_TPL_I2C=y CONFIG_TPL_I2C=y

1
configs/P2020RDB-PC_SDCARD_defconfig
View File

@ -48,7 +48,6 @@ CONFIG_SPL_RELOC_MALLOC_SIZE=0x5b000
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set # CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276

1
configs/P2020RDB-PC_SPIFLASH_defconfig
View File

@ -50,7 +50,6 @@ CONFIG_SPL_RELOC_MALLOC_SIZE=0x5b000
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set # CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276

1
configs/am62ax_evm_a53_defconfig
View File

@ -20,7 +20,6 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_PAD_TO=0x0 CONFIG_SPL_PAD_TO=0x0
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

15
configs/am62ax_evm_r5_defconfig
View File

@ -13,20 +13,25 @@ CONFIG_SPL_TEXT_BASE=0x43c00000
CONFIG_SPL_MMC=y CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_SIZE_LIMIT=0x40000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x7145
CONFIG_SPL_SIZE_LIMIT=0x3A7F0
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500
CONFIG_SPL_FS_FAT=y CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7000ffff CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c3a7f0
CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
# CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
CONFIG_SPL_MAX_SIZE=0x3B000
CONFIG_SPL_PAD_TO=0x0 CONFIG_SPL_PAD_TO=0x0
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x43c37800 CONFIG_SPL_BSS_START_ADDR=0x43c3b000
CONFIG_SPL_BSS_MAX_SIZE=0x5000 CONFIG_SPL_BSS_MAX_SIZE=0x3000
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_SEPARATE_BSS=y

14
configs/am62x_evm_a53_defconfig
View File

@ -7,6 +7,7 @@ CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM625=y CONFIG_SOC_K3_AM625=y
CONFIG_K3_ATF_LOAD_ADDR=0x9e780000 CONFIG_K3_ATF_LOAD_ADDR=0x9e780000
CONFIG_TARGET_AM625_A53_EVM=y CONFIG_TARGET_AM625_A53_EVM=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am625-sk" CONFIG_DEFAULT_DEVICE_TREE="k3-am625-sk"
CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_SPL_MMC=y CONFIG_SPL_MMC=y
@ -14,6 +15,7 @@ CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FS_FAT=y CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y CONFIG_SPL_SPI=y
CONFIG_DISTRO_DEFAULTS=y CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
@ -21,7 +23,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern" CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; setenv fdtfile ti/${name_fdt}; run distro_bootcmd"
CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80a00000 CONFIG_SPL_BSS_START_ADDR=0x80a00000
@ -32,12 +34,10 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_SPI=y
CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_POWER_DOMAIN=y
# CONFIG_SPL_SPI_FLASH_TINY is not set # CONFIG_SPL_SPI_FLASH_TINY is not set
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y
@ -57,6 +57,8 @@ CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y CONFIG_CLK=y
CONFIG_SPL_CLK=y CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y CONFIG_CLK_TI_SCI=y
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DM_MAILBOX=y CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y CONFIG_K3_SEC_PROXY=y
@ -71,7 +73,11 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_SOFT_RESET=y CONFIG_SPI_FLASH_SOFT_RESET=y
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_S28HS512T=y CONFIG_SPI_FLASH_S28HX_T=y
CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_FIXED=y
CONFIG_TI_AM65_CPSW_NUSS=y
CONFIG_PHY=y
CONFIG_PINCTRL=y CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y CONFIG_PINCTRL_SINGLE=y

32
configs/am62x_evm_r5_defconfig
View File

@ -7,6 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2 CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM625=y CONFIG_SOC_K3_AM625=y
CONFIG_TARGET_AM625_R5_EVM=y CONFIG_TARGET_AM625_R5_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_DM_GPIO=y CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am625-r5-sk" CONFIG_DEFAULT_DEVICE_TREE="k3-am625-r5-sk"
@ -18,10 +19,8 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_SIZE_LIMIT=0x40000 CONFIG_SPL_SIZE_LIMIT=0x40000
CONFIG_SPL_FS_FAT=y CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_SPI=y
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7000ffff CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7000ffff
CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT=y
@ -42,10 +41,9 @@ CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y CONFIG_SPL_EARLY_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_RAM_DEVICE=y
@ -53,6 +51,7 @@ CONFIG_SPL_REMOTEPROC=y
# CONFIG_SPL_SPI_FLASH_TINY is not set # CONFIG_SPL_SPI_FLASH_TINY is not set
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y CONFIG_CMD_ASKENV=y
@ -88,6 +87,14 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y CONFIG_MMC_SDHCI_AM654=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_SOFT_RESET=y
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_S28HX_T=y
CONFIG_PINCTRL=y CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set # CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y CONFIG_SPL_PINCTRL=y
@ -101,23 +108,14 @@ CONFIG_DM_RESET=y
CONFIG_RESET_TI_SCI=y CONFIG_RESET_TI_SCI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y CONFIG_DM_SERIAL=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_SOFT_RESET=y
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_S28HS512T=y
CONFIG_SOC_DEVICE=y CONFIG_SOC_DEVICE=y
CONFIG_SOC_DEVICE_TI_K3=y CONFIG_SOC_DEVICE_TI_K3=y
CONFIG_SOC_TI=y CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_TIMER=y CONFIG_TIMER=y
CONFIG_SPL_TIMER=y CONFIG_SPL_TIMER=y
CONFIG_OMAP_TIMER=y CONFIG_OMAP_TIMER=y
CONFIG_LIB_RATIONAL=y CONFIG_LIB_RATIONAL=y
CONFIG_SPL_LIB_RATIONAL=y CONFIG_SPL_LIB_RATIONAL=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000

4
configs/starqltechn_defconfig
View File

@ -20,14 +20,14 @@ CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GPIO=y CONFIG_CMD_GPIO=y
CONFIG_CMD_BMP=y CONFIG_CMD_BMP=y
# CONFIG_NET is not set # CONFIG_NET is not set
# CONFIG_DM_STDIO is not set
CONFIG_CLK=y CONFIG_CLK=y
CONFIG_MSM_GPIO=y CONFIG_MSM_GPIO=y
CONFIG_QCOM_PMIC_GPIO=y CONFIG_QCOM_PMIC_GPIO=y
CONFIG_PINCTRL=y CONFIG_PINCTRL=y
CONFIG_DM_PMIC=y CONFIG_DM_PMIC=y
CONFIG_PMIC_QCOM=y CONFIG_PMIC_QCOM=y
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_REQUIRE_SERIAL_CONSOLE=y
CONFIG_MSM_GENI_SERIAL=y
CONFIG_SPMI_MSM=y CONFIG_SPMI_MSM=y
CONFIG_VIDEO=y CONFIG_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_SYS_WHITE_ON_BLACK=y

20
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
View File

@ -47,6 +47,10 @@
#define WD0RST BIT(29) #define WD0RST BIT(29)
#define WD1RST BIT(24) #define WD1RST BIT(24)
#define WD2RST BIT(23) #define WD2RST BIT(23)
#define SWRST1 BIT(28)
#define SWRST2 BIT(27)
#define SWRST3 BIT(26)
#define SW4RST BIT(25)
#define GPIOX_MODULE_RESET 16 #define GPIOX_MODULE_RESET 16
#define CA9C_RESET BIT(0) #define CA9C_RESET BIT(0)
@ -1374,6 +1378,14 @@ static bool is_gpio_persist(struct udevice *dev, u8 bank)
regmap_read(priv->rst_regmap, NPCM7XX_RST_WD1RCR, &tmp); regmap_read(priv->rst_regmap, NPCM7XX_RST_WD1RCR, &tmp);
else if (value & WD2RST) else if (value & WD2RST)
regmap_read(priv->rst_regmap, NPCM7XX_RST_WD2RCR, &tmp); regmap_read(priv->rst_regmap, NPCM7XX_RST_WD2RCR, &tmp);
else if (value & SWRST1)
regmap_read(priv->rst_regmap, NPCM7XX_RST_SWRSTC1, &tmp);
else if (value & SWRST2)
regmap_read(priv->rst_regmap, NPCM7XX_RST_SWRSTC2, &tmp);
else if (value & SWRST3)
regmap_read(priv->rst_regmap, NPCM7XX_RST_SWRSTC3, &tmp);
else if (value & SW4RST)
regmap_read(priv->rst_regmap, NPCM7XX_RST_SWRSTC4, &tmp);
else else
return false; return false;
@ -1392,11 +1404,19 @@ static int npcm7xx_gpio_reset_persist(struct udevice *dev, unsigned int banknum,
regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD1RCR, BIT(num), 0); regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD1RCR, BIT(num), 0);
regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD2RCR, BIT(num), 0); regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD2RCR, BIT(num), 0);
regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_CORSTC, BIT(num), 0); regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_CORSTC, BIT(num), 0);
regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_SWRSTC1, BIT(num), 0);
regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_SWRSTC2, BIT(num), 0);
regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_SWRSTC3, BIT(num), 0);
regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_SWRSTC4, BIT(num), 0);
} else { } else {
regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD0RCR, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET); regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD0RCR, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);
regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD1RCR, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET); regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD1RCR, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);
regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD2RCR, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET); regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD2RCR, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);
regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_CORSTC, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET); regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_CORSTC, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);
regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_SWRSTC1, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);
regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_SWRSTC2, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);
regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_SWRSTC3, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);
regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_SWRSTC4, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);
} }
return 0; return 0;

22
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
View File

@ -20,7 +20,7 @@
#define SWRSTC1 0x44 #define SWRSTC1 0x44
#define SWRSTC2 0x48 #define SWRSTC2 0x48
#define SWRSTC3 0x4c #define SWRSTC3 0x4c
#define SWRSTC4 0x50 #define TIPRSTC 0x50
#define CORSTC 0x5c #define CORSTC 0x5c
#define FLOCKR1 0x74 #define FLOCKR1 0x74
#define INTCR4 0xc0 #define INTCR4 0xc0
@ -772,6 +772,10 @@ static int npcm8xx_gpio_reset_persist(struct udevice *dev, uint bank,
regmap_update_bits(priv->rst_regmap, WD1RCR, BIT(offset), 0); regmap_update_bits(priv->rst_regmap, WD1RCR, BIT(offset), 0);
regmap_update_bits(priv->rst_regmap, WD2RCR, BIT(offset), 0); regmap_update_bits(priv->rst_regmap, WD2RCR, BIT(offset), 0);
regmap_update_bits(priv->rst_regmap, CORSTC, BIT(offset), 0); regmap_update_bits(priv->rst_regmap, CORSTC, BIT(offset), 0);
regmap_update_bits(priv->rst_regmap, SWRSTC1, BIT(offset), 0);
regmap_update_bits(priv->rst_regmap, SWRSTC2, BIT(offset), 0);
regmap_update_bits(priv->rst_regmap, SWRSTC3, BIT(offset), 0);
regmap_update_bits(priv->rst_regmap, TIPRSTC, BIT(offset), 0);
} else { } else {
regmap_update_bits(priv->rst_regmap, WD0RCR, BIT(offset), regmap_update_bits(priv->rst_regmap, WD0RCR, BIT(offset),
BIT(offset)); BIT(offset));
@ -781,6 +785,14 @@ static int npcm8xx_gpio_reset_persist(struct udevice *dev, uint bank,
BIT(offset)); BIT(offset));
regmap_update_bits(priv->rst_regmap, CORSTC, BIT(offset), regmap_update_bits(priv->rst_regmap, CORSTC, BIT(offset),
BIT(offset)); BIT(offset));
regmap_update_bits(priv->rst_regmap, SWRSTC1, BIT(offset),
BIT(offset));
regmap_update_bits(priv->rst_regmap, SWRSTC2, BIT(offset),
BIT(offset));
regmap_update_bits(priv->rst_regmap, SWRSTC3, BIT(offset),
BIT(offset));
regmap_update_bits(priv->rst_regmap, TIPRSTC, BIT(offset),
BIT(offset));
} }
return 0; return 0;
@ -804,6 +816,14 @@ static bool is_gpio_persist(struct udevice *dev, uint bank)
regmap_read(priv->rst_regmap, WD1RCR, &val); regmap_read(priv->rst_regmap, WD1RCR, &val);
else if (status & WD2RST) else if (status & WD2RST)
regmap_read(priv->rst_regmap, WD2RCR, &val); regmap_read(priv->rst_regmap, WD2RCR, &val);
else if (status & SW1RST)
regmap_read(priv->rst_regmap, SWRSTC1, &val);
else if (status & SW2RST)
regmap_read(priv->rst_regmap, SWRSTC2, &val);
else if (status & SW3RST)
regmap_read(priv->rst_regmap, SWRSTC3, &val);
else if (status & TIPRST)
regmap_read(priv->rst_regmap, TIPRSTC, &val);
else else
return false; return false;

34
include/configs/am62ax_evm.h
View File

@ -9,7 +9,6 @@
#define __CONFIG_AM62AX_EVM_H #define __CONFIG_AM62AX_EVM_H
#include <linux/sizes.h> #include <linux/sizes.h>
#include <config_distro_bootcmd.h>
#include <environment/ti/mmc.h> #include <environment/ti/mmc.h>
#include <environment/ti/k3_dfu.h> #include <environment/ti/k3_dfu.h>
@ -55,12 +54,41 @@
"${bootdir}/${name_fit}\0" \ "${bootdir}/${name_fit}\0" \
"partitions=" PARTS_DEFAULT "partitions=" PARTS_DEFAULT
#define BOOTENV_DEV_TI_MMC(devtypeu, devtypel, instance) \
DEFAULT_MMC_TI_ARGS \
EXTRA_ENV_AM62A7_BOARD_SETTINGS_MMC \
"bootcmd_ti_mmc=" \
"run findfdt; run envboot; run init_mmc;" \
"if test ${boot_fit} -eq 1; then;" \
"run get_fit_mmc; run get_overlaystring;" \
"run run_fit;" \
"else;" \
"run get_kern_mmc; run get_fdt_mmc;" \
"run get_overlay_mmc;" \
"run run_kern;" \
"fi;\0"
#define BOOTENV_DEV_NAME_TI_MMC(devtyeu, devtypel, instance) \
"ti_mmc "
#if CONFIG_IS_ENABLED(CMD_MMC)
#define BOOT_TARGET_MMC(func) \
func(TI_MMC, ti_mmc, na)
#else
#define BOOT_TARGET_MMC(func)
#endif /* CONFIG_IS_ENABLED(CMD_MMC) */
#define BOOT_TARGET_DEVICES(func) \
BOOT_TARGET_MMC(func)
#include <config_distro_bootcmd.h>
/* Incorporate settings into the U-Boot environment */ /* Incorporate settings into the U-Boot environment */
#define CFG_EXTRA_ENV_SETTINGS \ #define CFG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \ DEFAULT_LINUX_BOOT_ENV \
DEFAULT_MMC_TI_ARGS \ DEFAULT_FIT_TI_ARGS \
EXTRA_ENV_AM62A7_BOARD_SETTINGS \ EXTRA_ENV_AM62A7_BOARD_SETTINGS \
EXTRA_ENV_AM62A7_BOARD_SETTINGS_MMC \ BOOTENV
/* Now for the remaining common defines */ /* Now for the remaining common defines */
#include <configs/ti_armv7_common.h> #include <configs/ti_armv7_common.h>

26
include/configs/am62x_evm.h
View File

@ -15,6 +15,29 @@
/* DDR Configuration */ /* DDR Configuration */
#define CFG_SYS_SDRAM_BASE1 0x880000000 #define CFG_SYS_SDRAM_BASE1 0x880000000
#ifdef CONFIG_CMD_MMC
#define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
#else
#define DISTRO_BOOT_DEV_MMC(func)
#endif
#ifdef CONFIG_CMD_PXE
#define DISTRO_BOOT_DEV_PXE(func) func(PXE, pxe, na)
#else
#define DISTRO_BOOT_DEV_PXE(func)
#endif
#ifdef CONFIG_CMD_DHCP
#define DISTRO_BOOT_DEV_DHCP(func) func(DHCP, dhcp, na)
#else
#define DISTRO_BOOT_DEV_DHCP(func)
#endif
#define BOOT_TARGET_DEVICES(func) \
DISTRO_BOOT_DEV_MMC(func) \
DISTRO_BOOT_DEV_PXE(func) \
DISTRO_BOOT_DEV_DHCP(func)
#define PARTS_DEFAULT \ #define PARTS_DEFAULT \
/* Linux partitions */ \ /* Linux partitions */ \
"name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0"
@ -59,7 +82,8 @@
DEFAULT_LINUX_BOOT_ENV \ DEFAULT_LINUX_BOOT_ENV \
DEFAULT_MMC_TI_ARGS \ DEFAULT_MMC_TI_ARGS \
EXTRA_ENV_AM625_BOARD_SETTINGS \ EXTRA_ENV_AM625_BOARD_SETTINGS \
EXTRA_ENV_AM625_BOARD_SETTINGS_MMC EXTRA_ENV_AM625_BOARD_SETTINGS_MMC \
BOOTENV
/* Now for the remaining common defines */ /* Now for the remaining common defines */
#include <configs/ti_armv7_common.h> #include <configs/ti_armv7_common.h>

5
include/configs/sdm845.h
View File

@ -16,8 +16,9 @@
#define CFG_EXTRA_ENV_SETTINGS \ #define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x4000000\0" \ "bootm_size=0x4000000\0" \
"bootm_low=0x80000000\0" \ "bootm_low=0x80000000\0" \
"stdout=vidconsole\0" \ "stdin=serial\0" \
"stderr=vidconsole\0" \ "stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0" \
"preboot=source $prevbl_initrd_start_addr:prebootscript\0" \ "preboot=source $prevbl_initrd_start_addr:prebootscript\0" \
"bootcmd=source $prevbl_initrd_start_addr:bootscript\0" "bootcmd=source $prevbl_initrd_start_addr:bootscript\0"