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Xilinx changes for v2023.10-rc1 v2

Browse Source 
axi_emac:
 - Change return value if RX packet is not ready
 
 cadence_qspi:
 - Enable flash reset for Versal NET
 
 dt:
 - Various DT syncups with Linux kernel
 - SOM - reserved pmufw memory location
 
 fpga:
 - Add load event
 
 mtd:
 - Add missing dependency for FLASH_CFI_MTD
 
 spi/nand:
 - Minor cleanup in Xilinx drivers
 
 versal-net:
 - Prioritize boot device in boot_targets
 - Wire mini ospi/qspi/emmc configurations
 
 watchdog:
 - Use new versal-wwdt property
 
 xilinx:
 - fix sparse warnings in various places ps7_init*
 - add missing headers
 - consolidate code around zynqmp_mmio_read/write
 - switch to amd.com email
 
 zynqmp_clk:
 - Add handling for gem rx/tsu clocks
 
 zynq_gem:
 - Configure mdio clock at run time
 
 zynq:
 - Enable fdt overlay support
 
 zynq_sdhci:
 - Call dll reset only for ZynqMP SOCs
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Merge tag 'xilinx-for-v2023.10-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2023.10-rc1 v2

axi_emac:
- Change return value if RX packet is not ready

cadence_qspi:
- Enable flash reset for Versal NET

dt:
- Various DT syncups with Linux kernel
- SOM - reserved pmufw memory location

fpga:
- Add load event

mtd:
- Add missing dependency for FLASH_CFI_MTD

spi/nand:
- Minor cleanup in Xilinx drivers

versal-net:
- Prioritize boot device in boot_targets
- Wire mini ospi/qspi/emmc configurations

watchdog:
- Use new versal-wwdt property

xilinx:
- fix sparse warnings in various places ps7_init*
- add missing headers
- consolidate code around zynqmp_mmio_read/write
- switch to amd.com email

zynqmp_clk:
- Add handling for gem rx/tsu clocks

zynq_gem:
- Configure mdio clock at run time

zynq:
- Enable fdt overlay support

zynq_sdhci:
- Call dll reset only for ZynqMP SOCs
This commit is contained in:
Tom Rini 2023-07-21 09:57:59 -04:00
commit e7f7e2e1e2
138 changed files with 869 additions and 251 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/dts/Makefile
View File

@ -416,6 +416,9 @@ dtb-$(CONFIG_ARCH_VERSAL) += \
xilinx-versal-virt.dtb
dtb-$(CONFIG_ARCH_VERSAL_NET) += \
versal-net-mini.dtb \
versal-net-mini-emmc.dtb \
versal-net-mini-ospi-single.dtb \
versal-net-mini-qspi-single.dtb \
xilinx-versal-net-virt.dtb
dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
zynqmp-r5.dtb

2
arch/arm/dts/avnet-ultra96-rev1.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2018 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;

4
arch/arm/dts/versal-mini-emmc0.dts
View File

@ -4,8 +4,8 @@
*
* (C) Copyright 2018-2019, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;

4
arch/arm/dts/versal-mini-emmc1.dts
View File

@ -4,8 +4,8 @@
*
* (C) Copyright 2018-2019, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;

4
arch/arm/dts/versal-mini-ospi.dtsi
View File

@ -4,8 +4,8 @@
*
* (C) Copyright 2018-2019, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;

4
arch/arm/dts/versal-mini-qspi.dtsi
View File

@ -4,8 +4,8 @@
*
* (C) Copyright 2018-2019, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;

2
arch/arm/dts/versal-mini.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2019, Xilinx, Inc.
*
* Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/
/dts-v1/;

64
arch/arm/dts/versal-net-mini-emmc.dts Normal file
View File

@ -0,0 +1,64 @@
// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Xilinx Versal NET Mini eMMC Configuration
*
* (C) Copyright 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
* Ashok Reddy Soma <ashok.reddy.soma@amd.com>
*/
/dts-v1/;
/ {
compatible = "xlnx,versal-net-mini";
#address-cells = <2>;
#size-cells = <2>;
model = "Xilinx Versal NET MINI eMMC";
aliases {
serial0 = &dcc;
mmc0 = &sdhci1;
};
chosen {
stdout-path = "serial0:115200";
};
memory@0 {
device_type = "memory";
reg = <0 0 0 0x20000000>;
};
clk200: clk200 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
dcc: dcc {
compatible = "arm,dcc";
status = "okay";
bootph-all;
};
amba: amba {
bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
sdhci1: sdhci@f1050000 {
compatible = "xlnx,versal-net-emmc";
status = "okay";
non-removable;
disable-wp;
bus-width = <8>;
reg = <0 0xf1050000 0 0x10000>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&clk200>, <&clk200>;
xlnx,mio-bank = <0>;
};
};
};

19
arch/arm/dts/versal-net-mini-ospi-single.dts Normal file
View File

@ -0,0 +1,19 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Versal NET OSPI single DTS
*
* (C) Copyright 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
* Ashok Reddy Soma <ashok.reddy.soma@amd.com>
*/
#include "versal-net-mini-ospi.dtsi"
/ {
model = "Xilinx Versal NET MINI OSPI SINGLE";
};
&flash0 {
spi-rx-bus-width = <8>;
};

78
arch/arm/dts/versal-net-mini-ospi.dtsi Normal file
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@ -0,0 +1,78 @@
// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Xilinx Versal NET Mini OSPI Configuration
*
* (C) Copyright 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
* Ashok Reddy Soma <ashok.reddy.soma@amd.com>
*/
/dts-v1/;
/ {
compatible = "xlnx,versal-net-mini";
#address-cells = <2>;
#size-cells = <2>;
model = "Xilinx Versal NET MINI OSPI";
aliases {
serial0 = &dcc;
spi0 = &ospi;
};
chosen {
stdout-path = "serial0:115200";
};
memory@bbf00000 {
device_type = "memory";
reg = <0 0xBBF00000 0 0x100000>;
};
clk125: clk125 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
dcc: dcc {
compatible = "arm,dcc";
status = "okay";
bootph-all;
};
amba: amba {
bootph-all;
compatible = "simple-bus";
#address-cells = <0x2>;
#size-cells = <0x2>;
ranges;
ospi: spi@f1010000 {
compatible = "cadence,qspi", "cdns,qspi-nor";
status = "okay";
reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>;
clock-names = "ref_clk", "pclk";
clocks = <&clk125>, <&clk125>;
bus-num = <2>;
num-cs = <1>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,is-dma = <1>;
cdns,is-stig-pgm = <1>;
cdns,trigger-address = <0xc0000000>;
#address-cells = <1>;
#size-cells = <0>;
flash0: flash@0 {
compatible = "mt35xu02g", "micron,m25p80",
"jedec,spi-nor";
reg = <0>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <20000000>;
};
};
};
};

16
arch/arm/dts/versal-net-mini-qspi-single.dts Normal file
View File

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Versal NET QSPI single DTS
*
* (C) Copyright 2023, Advanced Micro Devices, Inc.
*/
#include "versal-net-mini-qspi.dtsi"
/ {
model = "Xilinx Versal NET MINI QSPI SINGLE";
};
&flash0 {
spi-rx-bus-width = <4>;
};

72
arch/arm/dts/versal-net-mini-qspi.dtsi Normal file
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@ -0,0 +1,72 @@
// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Xilinx Versal NET Mini QSPI Configuration
*
* (C) Copyright 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
* Ashok Reddy Soma <ashok.reddy.soma@amd.com>
*/
/dts-v1/;
/ {
compatible = "xlnx,versal-net-mini";
#address-cells = <2>;
#size-cells = <2>;
model = "Xilinx Versal NET MINI QSPI";
aliases {
serial0 = &dcc;
spi0 = &qspi;
};
chosen {
stdout-path = "serial0:115200";
};
memory@bbf00000 {
device_type = "memory";
reg = <0 0xbbf00000 0 0x100000>;
};
clk150: clk150 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <150000000>;
};
dcc: dcc {
compatible = "arm,dcc";
status = "okay";
bootph-all;
};
amba: amba {
bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
qspi: spi@f1030000 {
compatible = "xlnx,versal-qspi-1.0";
status = "okay";
clock-names = "ref_clk", "pclk";
num-cs = <1>;
reg = <0 0xf1030000 0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk150>, <&clk150>;
flash0: flash@0 {
compatible = "n25q512a", "micron,m25p80",
"jedec,spi-nor";
reg = <0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <20000000>;
};
};
};
};

2
arch/arm/dts/zynq-7000.dtsi
View File

@ -153,6 +153,7 @@
clocks = <&clkc 38>;
interrupt-parent = <&intc>;
interrupts = <0 25 4>;
clock-frequency = <400000>;
reg = <0xe0004000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
@ -164,6 +165,7 @@
clocks = <&clkc 39>;
interrupt-parent = <&intc>;
interrupts = <0 48 4>;
clock-frequency = <400000>;
reg = <0xe0005000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;

2
arch/arm/dts/zynq-dlc20-rev1.0.dts
View File

@ -2,7 +2,7 @@
/*
* Copyright (C) 2018 Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
#include "zynq-7000.dtsi"

2
arch/arm/dts/zynq-minized.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2017 - 2018, Xilinx, Inc.
*
* Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
* Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
*/
/dts-v1/;

5
arch/arm/dts/zynq-zc702.dts
View File

@ -5,6 +5,7 @@
*/
/dts-v1/;
#include "zynq-7000.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Xilinx ZC702 board";
@ -102,8 +103,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
scl-gpios = <&gpio0 50 0>;
sda-gpios = <&gpio0 51 0>;
scl-gpios = <&gpio0 50 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio0 51 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-mux@74 {
compatible = "nxp,pca9548";

2
arch/arm/dts/zynqmp-a2197-revA.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;

12
arch/arm/dts/zynqmp-clk-ccf.dtsi
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
@ -126,7 +126,7 @@
};
&gpu {
clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>;
clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>;
};
&lpd_dma_chan1 {
@ -169,24 +169,28 @@
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
<&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
<&zynqmp_clk GEM_TSU>;
assigned-clocks = <&zynqmp_clk GEM_TSU>;
};
&gem1 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
<&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
<&zynqmp_clk GEM_TSU>;
assigned-clocks = <&zynqmp_clk GEM_TSU>;
};
&gem2 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
<&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
<&zynqmp_clk GEM_TSU>;
assigned-clocks = <&zynqmp_clk GEM_TSU>;
};
&gem3 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
<&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
<&zynqmp_clk GEM_TSU>;
assigned-clocks = <&zynqmp_clk GEM_TSU>;
};
&gpio {
@ -285,10 +289,6 @@
clocks = <&zynqmp_clk AMS_REF>;
};
&zynqmp_pcap {
clocks = <&zynqmp_clk PCAP>;
};
&zynqmp_dpdma {
clocks = <&zynqmp_clk DPDMA_REF>;
assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */

4
arch/arm/dts/zynqmp-dlc21-revA.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2019 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@ -131,7 +131,7 @@
"", "", "", "", "", /* 155 - 159 */
"", "", "", "", "", /* 160 - 164 */
"", "", "", "", "", /* 165 - 169 */
"", "", "", ""; /* 170 - 174 */
"", "", "", ""; /* 170 - 173 */
};
&i2c0 { /* MIO34/35 */

4
arch/arm/dts/zynqmp-e-a2197-00-revA.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2019 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@ -201,7 +201,7 @@
"", "", "", "", "", /* 155 - 159 */
"", "", "", "", "", /* 160 - 164 */
"", "", "", "", "", /* 165 - 169 */
"", "", "", ""; /* 170 - 174 */
"", "", "", ""; /* 170 - 173 */
};
&i2c0 { /* MIO 34-35 - can't stay here */

8
arch/arm/dts/zynqmp-g-a2197-00-revA.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@ -125,14 +125,14 @@
"", "", "", "", "", /* 155 - 159 */
"", "", "", "", "", /* 160 - 164 */
"", "", "", "", "", /* 165 - 169 */
"", "", "", ""; /* 170 - 174 */
"", "", "", ""; /* 170 - 173 */
};
&i2c0 { /* MIO 34-35 - can't stay here */
status = "okay";
clock-frequency = <400000>;
scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-mux@74 { /* u94 */
compatible = "nxp,pca9548";
#address-cells = <1>;

4
arch/arm/dts/zynqmp-m-a2197-01-revA.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@ -154,7 +154,7 @@
"", "", "", "", "", /* 155 - 159 */
"", "", "", "", "", /* 160 - 164 */
"", "", "", "", "", /* 165 - 169 */
"", "", "", ""; /* 170 - 174 */
"", "", "", ""; /* 170 - 173 */
};
&i2c0 { /* MIO 34-35 - can't stay here */

4
arch/arm/dts/zynqmp-m-a2197-02-revA.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@ -149,7 +149,7 @@
"", "", "", "", "", /* 155 - 159 */
"", "", "", "", "", /* 160 - 164 */
"", "", "", "", "", /* 165 - 169 */
"", "", "", ""; /* 170 - 174 */
"", "", "", ""; /* 170 - 173 */
};
&i2c0 { /* MIO 34-35 - can't stay here */

4
arch/arm/dts/zynqmp-m-a2197-03-revA.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@ -149,7 +149,7 @@
"", "", "", "", "", /* 155 - 159 */
"", "", "", "", "", /* 160 - 164 */
"", "", "", "", "", /* 165 - 169 */
"", "", "", ""; /* 170 - 174 */
"", "", "", ""; /* 170 - 173 */
};
&i2c0 { /* MIO 34-35 - can't stay here */

2
arch/arm/dts/zynqmp-mini-emmc0.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2018, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
*/
/dts-v1/;

2
arch/arm/dts/zynqmp-mini-emmc1.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2018, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
*/
/dts-v1/;

4
arch/arm/dts/zynqmp-mini-nand.dts
View File

@ -4,8 +4,8 @@
*
* (C) Copyright 2018, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;

4
arch/arm/dts/zynqmp-mini-qspi.dts
View File

@ -4,8 +4,8 @@
*
* (C) Copyright 2015 - 2020, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;

2
arch/arm/dts/zynqmp-mini.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2017, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;

4
arch/arm/dts/zynqmp-p-a2197-00-revA.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@ -134,7 +134,7 @@
"", "", "", "", "", /* 155 - 159 */
"", "", "", "", "", /* 160 - 164 */
"", "", "", "", "", /* 165 - 169 */
"", "", "", ""; /* 170 - 174 */
"", "", "", ""; /* 170 - 173 */
};
&i2c0 { /* MIO 34-35 - can't stay here */

2
arch/arm/dts/zynqmp-r5.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2018, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;

10
arch/arm/dts/zynqmp-sck-kr-g-revA.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#include <dt-bindings/gpio/gpio.h>
@ -68,8 +68,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
u14: ina260@40 { /* u14 */
compatible = "ti,ina260";
@ -188,6 +188,7 @@
phy-handle = <&phy0>;
phy-mode = "sgmii";
is-internal-pcspma;
assigned-clock-rates = <250000000>;
};
&gem1 { /* mdio mio50/51, gem mio38 - mio49 */
@ -196,6 +197,7 @@
pinctrl-0 = <&pinctrl_gem1_default>;
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
assigned-clock-rates = <250000000>;
mdio: mdio {
#address-cells = <1>;
@ -208,7 +210,7 @@
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
reset-assert-us = <100>;
reset-assert-us = <300>;
reset-deassert-us = <280>;
reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>;
};

10
arch/arm/dts/zynqmp-sck-kr-g-revB.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2021 - 2022, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#include <dt-bindings/gpio/gpio.h>
@ -68,8 +68,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
u14: ina260@40 { /* u14 */
compatible = "ti,ina260";
@ -188,6 +188,7 @@
phy-handle = <&phy0>;
phy-mode = "sgmii";
is-internal-pcspma;
assigned-clock-rates = <250000000>;
};
&gem1 { /* mdio mio50/51, gem mio38 - mio49 */
@ -196,6 +197,7 @@
pinctrl-0 = <&pinctrl_gem1_default>;
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
assigned-clock-rates = <250000000>;
mdio: mdio {
#address-cells = <1>;
@ -208,7 +210,7 @@
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
reset-assert-us = <100>;
reset-assert-us = <300>;
reset-deassert-us = <280>;
reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>;
};

7
arch/arm/dts/zynqmp-sck-kv-g-revA.dts
View File

@ -9,7 +9,7 @@
* "Y" – A01 board modified with legacy interposer (Nexperia)
* "Z" – A01 board modified with Diode interposer
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#include <dt-bindings/gpio/gpio.h>
@ -34,8 +34,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
u14: ina260@40 { /* u14 */
compatible = "ti,ina260";
@ -165,6 +165,7 @@
pinctrl-0 = <&pinctrl_gem3_default>;
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
assigned-clock-rates = <250000000>;
mdio: mdio {
#address-cells = <1>;

10
arch/arm/dts/zynqmp-sck-kv-g-revB.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#include <dt-bindings/gpio/gpio.h>
@ -16,7 +16,8 @@
/plugin/;
&{/} {
compatible = "xlnx,zynqmp-sk-kv260-rev1",
compatible = "xlnx,zynqmp-sk-kv260-rev2",
"xlnx,zynqmp-sk-kv260-rev1",
"xlnx,zynqmp-sk-kv260-revB",
"xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
model = "ZynqMP KV260 revB";
@ -28,8 +29,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
u14: ina260@40 { /* u14 */
compatible = "ti,ina260";
@ -152,6 +153,7 @@
pinctrl-0 = <&pinctrl_gem3_default>;
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
assigned-clock-rates = <250000000>;
mdio: mdio {
#address-cells = <1>;

5
arch/arm/dts/zynqmp-sm-k24-revA.dts
View File

@ -11,8 +11,9 @@
#include "zynqmp-sm-k26-revA.dts"
/ {
model = "ZynqMP SM-K24 RevA";
compatible = "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24",
model = "ZynqMP SM-K24 RevA/B/1";
compatible = "xlnx,zynqmp-sm-k24-rev1", "xlnx,zynqmp-sm-k24-revB",
"xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24",
"xlnx,zynqmp";
memory@0 {

19
arch/arm/dts/zynqmp-sm-k26-revA.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@ -50,6 +50,17 @@
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
pmu_region: pmu@7ff00000 {
reg = <0x0 0x7ff00000 0x0 0x100000>;
no-map;
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
@ -256,8 +267,8 @@
status = "okay";
bootph-all;
clock-frequency = <400000>;
scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
eeprom: eeprom@50 { /* u46 - also at address 0x58 */
bootph-all;
@ -352,7 +363,7 @@
"", "", "", "", "", /* 155 - 159 */
"", "", "", "", "", /* 160 - 164 */
"", "", "", "", "", /* 165 - 169 */
"", "", "", ""; /* 170 - 174 */
"", "", "", ""; /* 170 - 173 */
};
&xilinx_ams {

2
arch/arm/dts/zynqmp-smk-k26-revA.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#include "zynqmp-sm-k26-revA.dts"

2
arch/arm/dts/zynqmp-zc1232-revA.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;

4
arch/arm/dts/zynqmp-zc1254-revA.dts
View File

@ -4,8 +4,8 @@
*
* (C) Copyright 2015 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
* Michal Simek <michal.simek@amd.com>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/
/dts-v1/;

6
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2015 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@ -118,8 +118,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
eeprom: eeprom@55 {
compatible = "atmel,24c64"; /* 24AA64 */

6
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2015 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@ -109,8 +109,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
tca6416_u26: gpio@20 {
compatible = "ti,tca6416";

2
arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2016 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;

2
arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2015 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;

12
arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
View File

@ -4,8 +4,8 @@
*
* (C) Copyright 2015 - 2021, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@ -91,8 +91,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
scl-gpios = <&gpio 74 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 75 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio 74 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 75 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
&i2c1 {
@ -100,8 +100,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 76 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 77 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio 76 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 77 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};

8
arch/arm/dts/zynqmp-zcu100-revC.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2016 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
* Nathalie Chan King Choy
*/
@ -188,8 +188,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
clock-frequency = <100000>;
i2c-mux@75 { /* u11 */
compatible = "nxp,pca9548";
@ -569,6 +569,7 @@
pinctrl-0 = <&pinctrl_usb0_default>;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 0>;
/delete-property/ reset-gpios;
};
&dwc3_0 {
@ -584,6 +585,7 @@
pinctrl-0 = <&pinctrl_usb1_default>;
phy-names = "usb3-phy";
phys = <&psgtr 3 PHY_TYPE_USB3 1 0>;
reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;
};
&dwc3_1 {

2
arch/arm/dts/zynqmp-zcu102-rev1.0.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2016 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#include "zynqmp-zcu102-revB.dts"

2
arch/arm/dts/zynqmp-zcu102-rev1.1.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2016 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#include "zynqmp-zcu102-rev1.0.dts"

10
arch/arm/dts/zynqmp-zcu102-revA.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2015 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@ -232,8 +232,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
tca6416_u97: gpio@20 {
compatible = "ti,tca6416";
@ -496,8 +496,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
/* PL i2c via PCA9306 - u45 */
i2c-mux@74 { /* u34 */

2
arch/arm/dts/zynqmp-zcu102-revB.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2016 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#include "zynqmp-zcu102-revA.dts"

6
arch/arm/dts/zynqmp-zcu104-revA.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@ -139,8 +139,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
/* Another connection to this bus via PL i2c via PCA9306 - u45 */
i2c-mux@74 { /* u34 */

6
arch/arm/dts/zynqmp-zcu104-revC.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@ -144,8 +144,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
tca6416_u97: gpio@20 {
compatible = "ti,tca6416";

2
arch/arm/dts/zynqmp-zcu106-rev1.0.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2016 - 2022, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#include "zynqmp-zcu106-revA.dts"

10
arch/arm/dts/zynqmp-zcu106-revA.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2016 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@ -232,8 +232,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
tca6416_u97: gpio@20 {
compatible = "ti,tca6416";
@ -495,8 +495,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
/* PL i2c via PCA9306 - u45 */
i2c-mux@74 { /* u34 */

10
arch/arm/dts/zynqmp-zcu111-revA.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@ -204,8 +204,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
tca6416_u22: gpio@20 {
compatible = "ti,tca6416";
@ -384,8 +384,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-mux@74 { /* u26 */
compatible = "nxp,pca9548";

4
arch/arm/dts/zynqmp-zcu1275-revA.dts
View File

@ -4,8 +4,8 @@
*
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
* Michal Simek <michal.simek@amd.com>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/
/dts-v1/;

4
arch/arm/dts/zynqmp-zcu1275-revB.dts
View File

@ -4,8 +4,8 @@
*
* (C) Copyright 2018 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
* Michal Simek <michal.simek@amd.com>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/
/dts-v1/;

4
arch/arm/dts/zynqmp-zcu1285-revA.dts
View File

@ -4,8 +4,8 @@
*
* (C) Copyright 2018 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
* Michal Simek <michal.simek@amd.com>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/
/dts-v1/;

12
arch/arm/dts/zynqmp-zcu208-revA.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@ -222,7 +222,7 @@
"", "", "", "", "", /* 155 - 159 */
"", "", "", "", "", /* 160 - 164 */
"", "", "", "", "", /* 165 - 169 */
"", "", "", ""; /* 170 - 174 */
"", "", "", ""; /* 170 - 173 */
};
&i2c0 {
@ -231,8 +231,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
tca6416_u15: gpio@20 { /* u15 */
compatible = "ti,tca6416";
@ -397,8 +397,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-mux@74 {
compatible = "nxp,pca9548"; /* u20 */

12
arch/arm/dts/zynqmp-zcu216-revA.dts
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@ -228,7 +228,7 @@
"", "", "", "", "", /* 155 - 159 */
"", "", "", "", "", /* 160 - 164 */
"", "", "", "", "", /* 165 - 169 */
"", "", "", ""; /* 170 - 174 */
"", "", "", ""; /* 170 - 173 */
};
&gpu {
@ -241,8 +241,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
tca6416_u15: gpio@20 { /* u15 */
compatible = "ti,tca6416";
@ -407,8 +407,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-mux@74 {
compatible = "nxp,pca9548"; /* u20 */

35
arch/arm/dts/zynqmp.dtsi
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2014 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -33,6 +33,7 @@
operating-points-v2 = <&cpu_opp_table>;
reg = <0x0>;
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2>;
};
cpu1: cpu@1 {
@ -42,6 +43,7 @@
reg = <0x1>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2>;
};
cpu2: cpu@2 {
@ -51,6 +53,7 @@
reg = <0x2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2>;
};
cpu3: cpu@3 {
@ -60,6 +63,13 @@
reg = <0x3>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2>;
};
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
idle-states {
@ -111,7 +121,7 @@
#size-cells = <2>;
ranges;
ipi_mailbox_pmu1: mailbox@ff990400 {
ipi_mailbox_pmu1: mailbox@ff9905c0 {
bootph-all;
reg = <0x0 0xff9905c0 0x0 0x20>,
<0x0 0xff9905e0 0x0 0x20>,
@ -139,6 +149,10 @@
<0 144 4>,
<0 145 4>,
<0 146 4>;
interrupt-affinity = <&cpu0>,
<&cpu1>,
<&cpu2>,
<&cpu3>;
};
psci {
@ -179,7 +193,6 @@
zynqmp_pcap: pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
clock-names = "ref_clk";
};
xlnx_aes: zynqmp-aes {
@ -396,12 +409,12 @@
gpu: gpu@fd4b0000 {
status = "disabled";
compatible = "arm,mali-400", "arm,mali-utgard";
compatible = "xlnx,zynqmp-mali", "arm,mali-400";
reg = <0x0 0xfd4b0000 0x0 0x10000>;
interrupt-parent = <&gic>;
interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
clock-names = "gpu", "gpu_pp0", "gpu_pp1";
interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1";
clock-names = "bus", "core";
power-domains = <&zynqmp_firmware PD_GPU>;
};
@ -611,6 +624,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 17 4>;
clock-frequency = <400000>;
reg = <0x0 0xff020000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
@ -622,6 +636,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 18 4>;
clock-frequency = <400000>;
reg = <0x0 0xff030000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
@ -876,7 +891,6 @@
iommus = <&smmu 0x860>;
snps,quirk-frame-length-adjustment = <0x20>;
clock-names = "ref";
snps,enable_guctl1_resume_quirk;
snps,enable_guctl1_ipd_quirk;
snps,xhci-stream-quirk;
snps,resume-hs-terminations;
@ -908,7 +922,6 @@
iommus = <&smmu 0x861>;
snps,quirk-frame-length-adjustment = <0x20>;
clock-names = "ref";
snps,enable_guctl1_resume_quirk;
snps,enable_guctl1_ipd_quirk;
snps,xhci-stream-quirk;
snps,resume-hs-terminations;
@ -940,21 +953,19 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 56 4>;
interrupt-names = "ams-irq";
reg = <0x0 0xffa50000 0x0 0x800>;
reg-names = "ams-base";
#address-cells = <1>;
#size-cells = <1>;
#io-channel-cells = <1>;
ranges = <0 0 0xffa50800 0x800>;
ams_ps: ams_ps@0 {
ams_ps: ams-ps@0 {
compatible = "xlnx,zynqmp-ams-ps";
status = "disabled";
reg = <0x0 0x400>;
};
ams_pl: ams_pl@400 {
ams_pl: ams-pl@400 {
compatible = "xlnx,zynqmp-ams-pl";
status = "disabled";
reg = <0x400 0x400>;

2
arch/arm/mach-tegra/arm64-mmu.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
* (This file derived from arch/arm/mach-zynqmp/cpu.c)
*
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.

11
arch/arm/mach-versal-net/include/mach/hardware.h
View File

@ -81,3 +81,14 @@ enum versal_net_platform {
#define VERSAL_SLCR_BASEADDR 0xF1060000
#define VERSAL_AXI_MUX_SEL (VERSAL_SLCR_BASEADDR + 0x504)
#define VERSAL_OSPI_LINEAR_MODE BIT(1)
#define FLASH_RESET_GPIO 0xc
#define WPROT_CRP 0xF126001C
#define RST_GPIO 0xF1260318
#define WPROT_LPD_MIO 0xFF080728
#define WPROT_PMC_MIO 0xF1060828
#define BOOT_MODE_DIR 0xF1020204
#define BOOT_MODE_OUT 0xF1020208
#define MIO_PIN_12 0xF1060030
#define BANK0_OUTPUT 0xF1020040
#define BANK0_TRI 0xF1060200

2
arch/arm/mach-versal-net/include/mach/sys_proto.h
View File

@ -7,5 +7,3 @@
#include <linux/build_bug.h>
void mem_map_fill(void);
int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);

2
arch/arm/mach-versal/Makefile
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2016 - 2018 Xilinx, Inc.
# Michal Simek <michal.simek@xilinx.com>
# Michal Simek <michal.simek@amd.com>
#
obj-y += clk.o

2
arch/arm/mach-versal/clk.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 - 2018 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#include <common.h>

2
arch/arm/mach-versal/cpu.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 - 2018 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#include <common.h>

2
arch/arm/mach-versal/include/mach/sys_proto.h
View File

@ -13,5 +13,3 @@ enum {
void initialize_tcm(bool mode);
void tcm_init(u8 mode);
void mem_map_fill(void);
int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);

2
arch/arm/mach-versal/mp.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* (C) Copyright 2019 Xilinx, Inc.
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
*/
#include <common.h>

2
arch/arm/mach-zynqmp/Makefile
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2014 - 2015 Xilinx, Inc.
# Michal Simek <michal.simek@xilinx.com>
# Michal Simek <michal.simek@amd.com>
obj-y += clk.o
obj-y += cpu.o

2
arch/arm/mach-zynqmp/clk.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#include <common.h>

2
arch/arm/mach-zynqmp/cpu.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#include <common.h>

2
arch/arm/mach-zynqmp/handoff.c
View File

@ -2,7 +2,7 @@
/*
* Copyright 2016 - 2017 Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#include <common.h>

2
arch/arm/mach-zynqmp/include/mach/clk.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#ifndef _ASM_ARCH_CLK_H_

2
arch/arm/mach-zynqmp/include/mach/hardware.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#ifndef _ASM_ARCH_HARDWARE_H

5
arch/arm/mach-zynqmp/include/mach/sys_proto.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#ifndef _ASM_ARCH_SYS_PROTO_H
@ -48,9 +48,6 @@ enum {
unsigned int zynqmp_get_silicon_version(void);
int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
int zynqmp_mmio_read(const u32 address, u32 *value);
void initialize_tcm(bool mode);
void mem_map_fill(void);
#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)

3
arch/arm/mach-zynqmp/mp.c
View File

@ -1,12 +1,13 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#include <common.h>
#include <cpu_func.h>
#include <log.h>
#include <zynqmp_firmware.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>

2
arch/arm/mach-zynqmp/psu_spl_init.c
View File

@ -2,7 +2,7 @@
/*
* Copyright 2018 Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#include <common.h>
#include <asm/io.h>

2
arch/arm/mach-zynqmp/spl.c
View File

@ -2,7 +2,7 @@
/*
* Copyright 2015 - 2016 Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#include <common.h>

2
arch/microblaze/cpu/spl.c
View File

@ -2,7 +2,7 @@
/*
* (C) Copyright 2013 - 2014 Xilinx, Inc
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#include <common.h>

2
arch/microblaze/cpu/u-boot-spl.lds
View File

@ -2,7 +2,7 @@
/*
* (C) Copyright 2013 - 2014 Xilinx, Inc
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#include <asm-offsets.h>

2
arch/microblaze/include/asm/spl.h
View File

@ -2,7 +2,7 @@
/*
* (C) Copyright 2013 - 2014 Xilinx, Inc
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#ifndef _ASM_MICROBLAZE_SPL_H_

2
board/xilinx/common/Makefile
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
#
# (C) Copyright 2020 Xilinx, Inc.
# Michal Simek <michal.simek@xilinx.com>
# Michal Simek <michal.simek@amd.com>
#
obj-y += board.o

2
board/xilinx/common/board.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) Copyright 2020 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#ifndef _BOARD_XILINX_COMMON_BOARD_H

2
board/xilinx/common/cpu-info.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2014 - 2020 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#include <common.h>

2
board/xilinx/common/fru.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Xilinx, Inc.
* Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/
#ifndef __FRU_H

24
board/xilinx/versal-net/board.c
View File

@ -227,15 +227,33 @@ int board_late_init(void)
break;
case QSPI_MODE_24BIT:
puts("QSPI_MODE_24\n");
mode = "xspi0";
if (uclass_get_device_by_name(UCLASS_SPI,
"spi@f1030000", &dev)) {
puts("Boot from QSPI but without QSPI enabled!\n");
return -1;
}
mode = "xspi";
bootseq = dev_seq(dev);
break;
case QSPI_MODE_32BIT:
puts("QSPI_MODE_32\n");
mode = "xspi0";
if (uclass_get_device_by_name(UCLASS_SPI,
"spi@f1030000", &dev)) {
puts("Boot from QSPI but without QSPI enabled!\n");
return -1;
}
mode = "xspi";
bootseq = dev_seq(dev);
break;
case OSPI_MODE:
puts("OSPI_MODE\n");
mode = "xspi0";
if (uclass_get_device_by_name(UCLASS_SPI,
"spi@f1010000", &dev)) {
puts("Boot from OSPI but without OSPI enabled!\n");
return -1;
}
mode = "xspi";
bootseq = dev_seq(dev);
break;
case EMMC_MODE:
puts("EMMC_MODE\n");

2
board/xilinx/versal/Makefile
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2016 - 2018 Xilinx, Inc.
# Michal Simek <michal.simek@xilinx.com>
# Michal Simek <michal.simek@amd.com>
#
obj-y := board.o

2
board/xilinx/versal/board.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2014 - 2018 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#include <command.h>

2
board/xilinx/versal/cmds.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* (C) Copyright 2020 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#include <cpu_func.h>

2
board/xilinx/zynq/board.c
View File

@ -5,6 +5,8 @@
*/
#include <common.h>
#include <debug_uart.h>
#include <dfu.h>
#include <init.h>
#include <log.h>
#include <dm/uclass.h>

4
board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
View File

@ -12408,7 +12408,7 @@ unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
int
ps7_post_config()
ps7_post_config(void)
{
// Get the PS_VERSION on run time
unsigned long si_ver = ps7GetSiliconVersion ();
@ -12427,7 +12427,7 @@ ps7_post_config()
}
int
ps7_init()
ps7_init(void)
{
// Get the PS_VERSION on run time
unsigned long si_ver = ps7GetSiliconVersion ();

4
board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
View File

@ -12741,7 +12741,7 @@ unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
int
ps7_post_config()
ps7_post_config(void)
{
// Get the PS_VERSION on run time
unsigned long si_ver = ps7GetSiliconVersion ();
@ -12760,7 +12760,7 @@ ps7_post_config()
}
int
ps7_init()
ps7_init(void)
{
// Get the PS_VERSION on run time
unsigned long si_ver = ps7GetSiliconVersion ();

4
board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
View File

@ -12648,7 +12648,7 @@ unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
int
ps7_post_config()
ps7_post_config(void)
{
// Get the PS_VERSION on run time
unsigned long si_ver = ps7GetSiliconVersion ();
@ -12667,7 +12667,7 @@ ps7_post_config()
}
int
ps7_init()
ps7_init(void)
{
// Get the PS_VERSION on run time
unsigned long si_ver = ps7GetSiliconVersion ();

4
board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
View File

@ -12306,7 +12306,7 @@ unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
int
ps7_post_config()
ps7_post_config(void)
{
// Get the PS_VERSION on run time
unsigned long si_ver = ps7GetSiliconVersion ();
@ -12325,7 +12325,7 @@ ps7_post_config()
}
int
ps7_init()
ps7_init(void)
{
// Get the PS_VERSION on run time
unsigned long si_ver = ps7GetSiliconVersion ();

2
board/xilinx/zynqmp/Makefile
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@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2014 - 2016 Xilinx, Inc.
# Michal Simek <michal.simek@xilinx.com>
# Michal Simek <michal.simek@amd.com>
obj-y := zynqmp.o

2
board/xilinx/zynqmp/cmds.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* (C) Copyright 2018 Xilinx, Inc.
* Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/
#include <common.h>

2
board/xilinx/zynqmp/zynqmp.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
*/
#include <common.h>

3
common/event.c
View File

@ -36,6 +36,9 @@ const char *const type_name[] = {
/* init hooks */
"misc_init_f",
/* Fpga load hook */
"fpga_load",
/* fdt hooks */
"ft_fixup",

2
common/spl/spl_ram.c
View File

@ -6,7 +6,7 @@
* (C) Copyright 2016
* Toradex AG
*
* Michal Simek <michal.simek@xilinx.com>
* Michal Simek <michal.simek@amd.com>
* Stefan Agner <stefan.agner@toradex.com>
*/
#include <common.h>

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