From a24a1a19efca18a837d26a2cb6732ced47c3f071 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 13 Jun 2023 13:22:26 +0200 Subject: [PATCH 01/40] watchdog: versal: Use new compatible xlnx,versal-wwdt DT binding has been approved that's why use new compatible string. The old one is mark as deprecated and should be removed after some releases. Link: https://lore.kernel.org/r/20230420104231.2243079-3-srinivas.neeli@amd.com/ Reviewed-by: Stefan Roese Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/6e78d0d2e21f2f9e7f8f448bb8e0d27ced4de7d3.1686655339.git.michal.simek@amd.com --- drivers/watchdog/xilinx_wwdt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/xilinx_wwdt.c b/drivers/watchdog/xilinx_wwdt.c index d582e3cc8f4..8b6fc30edbe 100644 --- a/drivers/watchdog/xilinx_wwdt.c +++ b/drivers/watchdog/xilinx_wwdt.c @@ -191,7 +191,8 @@ static const struct wdt_ops xlnx_wwdt_ops = { }; static const struct udevice_id xlnx_wwdt_ids[] = { - { .compatible = "xlnx,versal-wwdt-1.0", }, + { .compatible = "xlnx,versal-wwdt", }, + { .compatible = "xlnx,versal-wwdt-1.0", }, /* deprecated */ {}, }; From 85a2d124cdcae616d651a90fca1c3e1e06e0b91b Mon Sep 17 00:00:00 2001 From: Sharath Kumar Dasari Date: Mon, 5 Jun 2023 13:59:51 +0200 Subject: [PATCH 02/40] arm64: zynqmp: Fix the memory node for k26/k24 kria som boards PMUFW requires top 1MB of the lower DDR memory reserved for its operation, this is missing in k26/k24 sm static dts files because of which U-Boot throws warning messages "efi_free_pool: illegal free" as EFI puts some code to that space which shouldn't happen. Signed-off-by: Sharath Kumar Dasari Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/57452d16df2d48593de206bebf877d2c2cfe7bf1.1685966389.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sm-k26-revA.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index f6ed047f3d9..eac0b55de36 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -50,6 +50,17 @@ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + pmu_region: pmu@7ff00000 { + reg = <0x0 0x7ff00000 0x0 0x100000>; + no-map; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; From 583cebb9ecaec824289a3e2b0dc53158b6030fbb Mon Sep 17 00:00:00 2001 From: Algapally Santosh Sagar Date: Wed, 14 Jun 2023 03:03:54 -0600 Subject: [PATCH 03/40] spi: xilinx_spi: Add missing prototype for xilinx_qspi_mem_exec_op Add missing prototype to fix the below sparse warning warning: no previous prototype for 'xilinx_qspi_mem_exec_op' [-Wmissing-prototypes] Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230614090359.10809-2-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- drivers/spi/xilinx_spi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 33575fe7575..b58a3f632a4 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -363,8 +363,8 @@ static int xilinx_qspi_check_buswidth(struct spi_slave *slave, u8 width) return -EOPNOTSUPP; } -bool xilinx_qspi_mem_exec_op(struct spi_slave *slave, - const struct spi_mem_op *op) +static bool xilinx_qspi_mem_exec_op(struct spi_slave *slave, + const struct spi_mem_op *op) { if (xilinx_qspi_check_buswidth(slave, op->cmd.buswidth)) return false; From fdae78b5f5a992f8dbeab7702badaf7e90446d90 Mon Sep 17 00:00:00 2001 From: Algapally Santosh Sagar Date: Wed, 14 Jun 2023 03:03:55 -0600 Subject: [PATCH 04/40] xilinx: zynq: Add missing prototype for zynqmp_mmio_write Add missing prototype to fix the sparse warning, warning: no previous prototype for 'zynqmp_mmio_write' [-Wmissing-prototypes]. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230614090359.10809-3-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- include/zynqmp_firmware.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 1192d5902dc..c56ad3f9206 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -454,6 +454,7 @@ int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value); int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config, u32 value); int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id); +int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); /* Type of Config Object */ #define PM_CONFIG_OBJECT_TYPE_BASE 0x1U From 0ebb68fb55f135b036fe20a74f2cfebd98ac0b76 Mon Sep 17 00:00:00 2001 From: Algapally Santosh Sagar Date: Wed, 14 Jun 2023 03:03:56 -0600 Subject: [PATCH 05/40] spi: zynq_qspi: Add missing prototype for zynq_qspi_mem_exec_op Add missing prototype to fix the sparse warning, warning: no previous prototype for 'zynq_qspi_mem_exec_op' [-Wmissing-prototypes]. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230614090359.10809-4-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- drivers/spi/zynq_qspi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index d1d40489665..cb52c0f3072 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -747,8 +747,8 @@ static int zynq_qspi_check_buswidth(struct spi_slave *slave, u8 width) return -EOPNOTSUPP; } -bool zynq_qspi_mem_exec_op(struct spi_slave *slave, - const struct spi_mem_op *op) +static bool zynq_qspi_mem_exec_op(struct spi_slave *slave, + const struct spi_mem_op *op) { if (zynq_qspi_check_buswidth(slave, op->cmd.buswidth)) return false; From 52279be25cf53491a605ce2ebcefd81b4e7ed9b3 Mon Sep 17 00:00:00 2001 From: Algapally Santosh Sagar Date: Wed, 14 Jun 2023 03:03:57 -0600 Subject: [PATCH 06/40] mtd: nand: zynq_nand: Change datatype of status and ecc_status to int status and ecc_status are of unsigned type where they are compared for negative value. This is pointed by below sparse warning. Change datatype to int to fix this. warning: comparison of unsigned expression in '< 0' is always false [-Wtype-limits] Signed-off-by: Algapally Santosh Sagar Reviewed-by: Michael Trimarchi Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230614090359.10809-5-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- drivers/mtd/nand/raw/zynq_nand.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/zynq_nand.c b/drivers/mtd/nand/raw/zynq_nand.c index 9e3ee7412d0..545fdd7b697 100644 --- a/drivers/mtd/nand/raw/zynq_nand.c +++ b/drivers/mtd/nand/raw/zynq_nand.c @@ -285,7 +285,7 @@ static int zynq_nand_init_nand_flash(struct mtd_info *mtd, int option) { struct nand_chip *nand_chip = mtd_to_nand(mtd); struct nand_drv *smc = nand_get_controller_data(nand_chip); - u32 status; + int status; /* disable interrupts */ writel(ZYNQ_NAND_CLR_CONFIG, &smc->reg->cfr); @@ -332,7 +332,7 @@ static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data, struct nand_drv *smc = nand_get_controller_data(nand_chip); u32 ecc_value = 0; u8 ecc_reg, ecc_byte; - u32 ecc_status; + int ecc_status; /* Wait till the ECC operation is complete */ ecc_status = zynq_nand_waitfor_ecc_completion(mtd); From 3bfc94ba9c35a1b9a73b608f54511d714c662fe0 Mon Sep 17 00:00:00 2001 From: Algapally Santosh Sagar Date: Wed, 14 Jun 2023 03:03:58 -0600 Subject: [PATCH 07/40] arm: zynq: Pass the missing argument type in function definition Pass missing argument type in the function definition to fix the sparse warning, warning: old-style function definition [-Wold-style-definition] Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230614090359.10809-6-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c | 4 ++-- board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c | 4 ++-- board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c | 4 ++-- board/xilinx/zynq/zynq-zed/ps7_init_gpl.c | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c index c2a6f9199ac..602a789e775 100644 --- a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c @@ -12408,7 +12408,7 @@ unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; int -ps7_post_config() +ps7_post_config(void) { // Get the PS_VERSION on run time unsigned long si_ver = ps7GetSiliconVersion (); @@ -12427,7 +12427,7 @@ ps7_post_config() } int -ps7_init() +ps7_init(void) { // Get the PS_VERSION on run time unsigned long si_ver = ps7GetSiliconVersion (); diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c index fd102a3ce4a..9343683f4d7 100644 --- a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c @@ -12741,7 +12741,7 @@ unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; int -ps7_post_config() +ps7_post_config(void) { // Get the PS_VERSION on run time unsigned long si_ver = ps7GetSiliconVersion (); @@ -12760,7 +12760,7 @@ ps7_post_config() } int -ps7_init() +ps7_init(void) { // Get the PS_VERSION on run time unsigned long si_ver = ps7GetSiliconVersion (); diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c index 796e5b0c5f6..6b153aa3796 100644 --- a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c @@ -12648,7 +12648,7 @@ unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; int -ps7_post_config() +ps7_post_config(void) { // Get the PS_VERSION on run time unsigned long si_ver = ps7GetSiliconVersion (); @@ -12667,7 +12667,7 @@ ps7_post_config() } int -ps7_init() +ps7_init(void) { // Get the PS_VERSION on run time unsigned long si_ver = ps7GetSiliconVersion (); diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c index baf89a58000..6f2edf16c24 100644 --- a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c @@ -12306,7 +12306,7 @@ unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; int -ps7_post_config() +ps7_post_config(void) { // Get the PS_VERSION on run time unsigned long si_ver = ps7GetSiliconVersion (); @@ -12325,7 +12325,7 @@ ps7_post_config() } int -ps7_init() +ps7_init(void) { // Get the PS_VERSION on run time unsigned long si_ver = ps7GetSiliconVersion (); From 340760ec0ffbe06c3dc1388ee605e031a11ff042 Mon Sep 17 00:00:00 2001 From: Algapally Santosh Sagar Date: Wed, 14 Jun 2023 03:03:59 -0600 Subject: [PATCH 08/40] xilinx: zynq: Add the missing function prototypes Add the missing prototypes for the functions pointed by the below sparse warnings warning: no previous prototype for 'set_dfu_alt_info' [-Wmissing-prototypes] warning: no previous prototype for 'board_debug_uart_init' [-Wmissing-prototypes] Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230614090359.10809-7-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- board/xilinx/zynq/board.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 9a59445b442..3b6581e3046 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -5,6 +5,8 @@ */ #include +#include +#include #include #include #include From 9a45365ae9cd80e0f060e480c544c17bb9a81e51 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Wed, 14 Jun 2023 03:30:58 -0600 Subject: [PATCH 09/40] arm64: versal-net: spi: Update boot sequence dynamically Currently xspi0 is used for all spi boot modes, it means it will use "sf probe 0 0 0" for all spi's irrespective of which node it is wired. Get boot sequence from dev_seq() and update boot command for xspi dynamically. As a result bootcmd for spi is updated as below when two instances of spi are present in DT node. bootcmd_xspi0=devnum_xspi=0; run xspi_boot bootcmd_xspi1=devnum_xspi=1; run xspi_boot xspi_boot=sf probe $devnum_xspi:0 0 0 && sf read $scriptaddr $script_offset_f $script_size_f && echo XSPI: Trying to boot script at ${scriptaddr} && source ${scriptaddr}; echo XSPI: SCRIPT FAILED: continuing...; Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230614093058.30438-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- board/xilinx/versal-net/board.c | 24 +++++++++++++++++++++--- include/configs/xilinx_versal_net.h | 23 ++++++++++++++--------- 2 files changed, 35 insertions(+), 12 deletions(-) diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c index a68b608b82c..f0d2224b332 100644 --- a/board/xilinx/versal-net/board.c +++ b/board/xilinx/versal-net/board.c @@ -227,15 +227,33 @@ int board_late_init(void) break; case QSPI_MODE_24BIT: puts("QSPI_MODE_24\n"); - mode = "xspi0"; + if (uclass_get_device_by_name(UCLASS_SPI, + "spi@f1030000", &dev)) { + puts("Boot from QSPI but without QSPI enabled!\n"); + return -1; + } + mode = "xspi"; + bootseq = dev_seq(dev); break; case QSPI_MODE_32BIT: puts("QSPI_MODE_32\n"); - mode = "xspi0"; + if (uclass_get_device_by_name(UCLASS_SPI, + "spi@f1030000", &dev)) { + puts("Boot from QSPI but without QSPI enabled!\n"); + return -1; + } + mode = "xspi"; + bootseq = dev_seq(dev); break; case OSPI_MODE: puts("OSPI_MODE\n"); - mode = "xspi0"; + if (uclass_get_device_by_name(UCLASS_SPI, + "spi@f1010000", &dev)) { + puts("Boot from OSPI but without OSPI enabled!\n"); + return -1; + } + mode = "xspi"; + bootseq = dev_seq(dev); break; case EMMC_MODE: puts("EMMC_MODE\n"); diff --git a/include/configs/xilinx_versal_net.h b/include/configs/xilinx_versal_net.h index 424ead038e3..613cce46f90 100644 --- a/include/configs/xilinx_versal_net.h +++ b/include/configs/xilinx_versal_net.h @@ -76,20 +76,24 @@ # define BOOT_TARGET_DEVICES_DHCP(func) #endif -#if defined(CONFIG_ZYNQMP_GQSPI) || defined(CONFIG_CADENCE_OSPI_VERSAL_NET) -# define BOOT_TARGET_DEVICES_XSPI(func) func(XSPI, xspi, 0) -#else -# define BOOT_TARGET_DEVICES_XSPI(func) -#endif - -#define BOOTENV_DEV_XSPI(devtypeu, devtypel, instance) \ - "bootcmd_xspi0=sf probe 0 0 0 && " \ +#if defined(CONFIG_ZYNQMP_GQSPI) || defined(CONFIG_CADENCE_OSPI_VERSAL) +# define BOOT_TARGET_DEVICES_XSPI(func) func(XSPI, xspi, 0) func(XSPI, xspi, 1) +# define BOOTENV_DEV_SHARED_XSPI \ + "xspi_boot=sf probe $devnum_xspi:0 0 0 && " \ "sf read $scriptaddr $script_offset_f $script_size_f && " \ "echo XSPI: Trying to boot script at ${scriptaddr} && " \ "source ${scriptaddr}; echo XSPI: SCRIPT FAILED: continuing...;\0" +#else +# define BOOT_TARGET_DEVICES_XSPI(func) +# define BOOTENV_DEV_SHARED_XSPI +#endif + +#define BOOTENV_DEV_XSPI(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "devnum_xspi=" #instance "; run " #devtypel "_boot\0" \ #define BOOTENV_DEV_NAME_XSPI(devtypeu, devtypel, instance) \ - "xspi0 " + "" #define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na) @@ -127,6 +131,7 @@ #define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV \ + BOOTENV_DEV_SHARED_XSPI \ DFU_ALT_INFO #endif From 22836f088d6027ee8e4bde17abbf71644a8388f5 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Mon, 19 Jun 2023 09:19:22 +0530 Subject: [PATCH 10/40] net: zynq_gem: Don't hardcode the MDC clock divisor As per spec MDC must not exceed 2.5MHz, read the pclk clock from the device tree and update the MDC clock divisor. GEM devices support larger clock divisors and have a different range of divisors. Program the MDIO clock divisors based on the clock rate of the pclk clock. Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20230619034922.24019-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- drivers/net/zynq_gem.c | 57 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 49 insertions(+), 8 deletions(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 211b2c6e556..f3cdfb0275d 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -67,11 +68,6 @@ #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */ #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */ #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */ -#ifdef CONFIG_ARM64 -#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */ -#else -#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */ -#endif #ifdef CONFIG_ARM64 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ @@ -81,8 +77,7 @@ #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ ZYNQ_GEM_NWCFG_FDEN | \ - ZYNQ_GEM_NWCFG_FSREM | \ - ZYNQ_GEM_NWCFG_MDCCLKDIV) + ZYNQ_GEM_NWCFG_FSREM) #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ @@ -141,6 +136,18 @@ #define RXCLK_EN BIT(0) +/* GEM specific constants for CLK. */ +#define GEM_CLK_DIV8 0 +#define GEM_CLK_DIV16 1 +#define GEM_CLK_DIV32 2 +#define GEM_CLK_DIV48 3 +#define GEM_CLK_DIV64 4 +#define GEM_CLK_DIV96 5 +#define GEM_CLK_DIV128 6 +#define GEM_CLK_DIV224 7 + +#define GEM_MDC_SET(val) FIELD_PREP(GENMASK(20, 18), val) + /* Device registers */ struct zynq_gem_regs { u32 nwctrl; /* 0x0 - Network Control reg */ @@ -220,6 +227,7 @@ struct zynq_gem_priv { struct mii_dev *bus; struct clk rx_clk; struct clk tx_clk; + struct clk pclk; u32 max_speed; bool int_pcs; bool dma_64bit; @@ -352,6 +360,32 @@ static int zynq_phy_init(struct udevice *dev) return phy_config(priv->phydev); } +static u32 gem_mdc_clk_div(struct zynq_gem_priv *priv) +{ + u32 config; + unsigned long pclk_hz; + + pclk_hz = clk_get_rate(&priv->pclk); + if (pclk_hz <= 20000000) + config = GEM_MDC_SET(GEM_CLK_DIV8); + else if (pclk_hz <= 40000000) + config = GEM_MDC_SET(GEM_CLK_DIV16); + else if (pclk_hz <= 80000000) + config = GEM_MDC_SET(GEM_CLK_DIV32); + else if (pclk_hz <= 120000000) + config = GEM_MDC_SET(GEM_CLK_DIV48); + else if (pclk_hz <= 160000000) + config = GEM_MDC_SET(GEM_CLK_DIV64); + else if (pclk_hz <= 240000000) + config = GEM_MDC_SET(GEM_CLK_DIV96); + else if (pclk_hz <= 320000000) + config = GEM_MDC_SET(GEM_CLK_DIV128); + else + config = GEM_MDC_SET(GEM_CLK_DIV224); + + return config; +} + static int zynq_gem_init(struct udevice *dev) { u32 i, nwconfig; @@ -460,7 +494,8 @@ static int zynq_gem_init(struct udevice *dev) return -1; } - nwconfig = ZYNQ_GEM_NWCFG_INIT; + nwconfig = gem_mdc_clk_div(priv); + nwconfig |= ZYNQ_GEM_NWCFG_INIT; /* * Set SGMII enable PCS selection only if internal PCS/PMA @@ -828,6 +863,12 @@ static int zynq_gem_probe(struct udevice *dev) } } + ret = clk_get_by_name(dev, "pclk", &priv->pclk); + if (ret < 0) { + dev_err(dev, "failed to get pclk clock\n"); + goto err2; + } + if (IS_ENABLED(CONFIG_DM_ETH_PHY)) priv->bus = eth_phy_get_mdio_bus(dev); From 34dec6a443df2adb5df2c65b2c441652c5976b44 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Wed, 14 Jun 2023 06:04:52 -0600 Subject: [PATCH 11/40] cadence_qspi: Enable flash reset for Versal NET platform Enable flash reset functionality for Versal NET platform. In cadence_qspi.c there is weak function defined for reset, hence remove the check for config, so that it will work for Versal and Versal NET platforms. Add register defines in Versal NET hardware.h for mini U-Boot flash reset. Add read_delay initialization for Versal NET also. Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230614120452.21019-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- arch/arm/mach-versal-net/include/mach/hardware.h | 11 +++++++++++ drivers/spi/cadence_ospi_versal.c | 3 +-- drivers/spi/cadence_qspi.c | 13 +++++-------- 3 files changed, 17 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-versal-net/include/mach/hardware.h b/arch/arm/mach-versal-net/include/mach/hardware.h index 3f04104961d..9bddb8b0072 100644 --- a/arch/arm/mach-versal-net/include/mach/hardware.h +++ b/arch/arm/mach-versal-net/include/mach/hardware.h @@ -81,3 +81,14 @@ enum versal_net_platform { #define VERSAL_SLCR_BASEADDR 0xF1060000 #define VERSAL_AXI_MUX_SEL (VERSAL_SLCR_BASEADDR + 0x504) #define VERSAL_OSPI_LINEAR_MODE BIT(1) + +#define FLASH_RESET_GPIO 0xc +#define WPROT_CRP 0xF126001C +#define RST_GPIO 0xF1260318 +#define WPROT_LPD_MIO 0xFF080728 +#define WPROT_PMC_MIO 0xF1060828 +#define BOOT_MODE_DIR 0xF1020204 +#define BOOT_MODE_OUT 0xF1020208 +#define MIO_PIN_12 0xF1060030 +#define BANK0_OUTPUT 0xF1020040 +#define BANK0_TRI 0xF1060200 diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index 434c6038f3b..a7685a2f512 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -130,7 +130,6 @@ int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv) #if defined(CONFIG_DM_GPIO) int cadence_qspi_versal_flash_reset(struct udevice *dev) { -#ifndef CONFIG_ARCH_VERSAL_NET struct gpio_desc gpio; u32 reset_gpio; int ret; @@ -166,7 +165,7 @@ int cadence_qspi_versal_flash_reset(struct udevice *dev) /* Set value 1 to pin */ dm_gpio_set_value(&gpio, 1); udelay(1); -#endif + return 0; } #else diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 2d715e478ca..cc3a54f2958 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -249,17 +249,14 @@ static int cadence_spi_probe(struct udevice *bus) priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz); - if (IS_ENABLED(CONFIG_ARCH_VERSAL)) { - /* Versal platform uses spi calibration to set read delay */ + /* Versal and Versal-NET use spi calibration to set read delay */ + if (CONFIG_IS_ENABLED(ARCH_VERSAL) || + CONFIG_IS_ENABLED(ARCH_VERSAL_NET)) if (priv->read_delay >= 0) priv->read_delay = -1; - /* Reset ospi flash device */ - ret = cadence_qspi_versal_flash_reset(bus); - if (ret) - return ret; - } - return 0; + /* Reset ospi flash device */ + return cadence_qspi_versal_flash_reset(bus); } static int cadence_spi_remove(struct udevice *dev) From 96683d3436081cd30010ea2d2e3dc7236fbffe7e Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Wed, 14 Jun 2023 06:13:49 -0600 Subject: [PATCH 12/40] xilinx: versal-net: Add mini qspi configuration Add support for Versal NET mini Quad SPI flash configuration. This runs from onchip memory, so it has to be compact. Hence only Quad SPI related settings are enabled. Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230614121351.21521-2-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 1 + arch/arm/dts/versal-net-mini-qspi-single.dts | 16 ++++ arch/arm/dts/versal-net-mini-qspi.dtsi | 72 ++++++++++++++++++ configs/xilinx_versal_net_mini_qspi_defconfig | 75 +++++++++++++++++++ 4 files changed, 164 insertions(+) create mode 100644 arch/arm/dts/versal-net-mini-qspi-single.dts create mode 100644 arch/arm/dts/versal-net-mini-qspi.dtsi create mode 100644 configs/xilinx_versal_net_mini_qspi_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 07b26df2750..f9bc0a99318 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -416,6 +416,7 @@ dtb-$(CONFIG_ARCH_VERSAL) += \ xilinx-versal-virt.dtb dtb-$(CONFIG_ARCH_VERSAL_NET) += \ versal-net-mini.dtb \ + versal-net-mini-qspi-single.dtb \ xilinx-versal-net-virt.dtb dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \ zynqmp-r5.dtb diff --git a/arch/arm/dts/versal-net-mini-qspi-single.dts b/arch/arm/dts/versal-net-mini-qspi-single.dts new file mode 100644 index 00000000000..fec1b514ed9 --- /dev/null +++ b/arch/arm/dts/versal-net-mini-qspi-single.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal NET QSPI single DTS + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + */ + +#include "versal-net-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal NET MINI QSPI SINGLE"; +}; + +&flash0 { + spi-rx-bus-width = <4>; +}; diff --git a/arch/arm/dts/versal-net-mini-qspi.dtsi b/arch/arm/dts/versal-net-mini-qspi.dtsi new file mode 100644 index 00000000000..097b58c633b --- /dev/null +++ b/arch/arm/dts/versal-net-mini-qspi.dtsi @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal NET Mini QSPI Configuration + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + * + * Michal Simek + * Ashok Reddy Soma + */ + +/dts-v1/; + +/ { + compatible = "xlnx,versal-net-mini"; + #address-cells = <2>; + #size-cells = <2>; + model = "Xilinx Versal NET MINI QSPI"; + + aliases { + serial0 = &dcc; + spi0 = &qspi; + }; + + chosen { + stdout-path = "serial0:115200"; + }; + + memory@bbf00000 { + device_type = "memory"; + reg = <0 0xbbf00000 0 0x100000>; + }; + + clk150: clk150 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <150000000>; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "okay"; + bootph-all; + }; + + amba: amba { + bootph-all; + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + qspi: spi@f1030000 { + compatible = "xlnx,versal-qspi-1.0"; + status = "okay"; + clock-names = "ref_clk", "pclk"; + num-cs = <1>; + reg = <0 0xf1030000 0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk150>, <&clk150>; + + flash0: flash@0 { + compatible = "n25q512a", "micron,m25p80", + "jedec,spi-nor"; + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-max-frequency = <20000000>; + }; + }; + }; +}; diff --git a/configs/xilinx_versal_net_mini_qspi_defconfig b/configs/xilinx_versal_net_mini_qspi_defconfig new file mode 100644 index 00000000000..a7ebc38cda1 --- /dev/null +++ b/configs/xilinx_versal_net_mini_qspi_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_versal_net_mini" +CONFIG_COUNTER_FREQUENCY=100000000 +CONFIG_ARCH_VERSAL_NET=y +CONFIG_TEXT_BASE=0xBBF00000 +CONFIG_SYS_MALLOC_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xBBF20000 +CONFIG_SF_DEFAULT_SPEED=30000000 +CONFIG_ENV_SIZE=0x80 +CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-qspi-single" +CONFIG_SYS_PROMPT="Versal NET> " +CONFIG_SYS_MEM_RSVD_FOR_MMU=y +# CONFIG_PSCI_RESET is not set +CONFIG_SYS_LOAD_ADDR=0xBBF80000 +# CONFIG_EXPERT is not set +CONFIG_REMAKE_ELF=y +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +# CONFIG_AUTOBOOT is not set +CONFIG_LOGLEVEL=0 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_BOARD_LATE_INIT is not set +# CONFIG_CMDLINE_EDITING is not set +# CONFIG_AUTO_COMPLETE is not set +# CONFIG_SYS_LONGHELP is not set +# CONFIG_SYS_XTRACE is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG is not set +# CONFIG_NET is not set +# CONFIG_DM_WARN is not set +# CONFIG_DM_DEVICE_REMOVE is not set +# CONFIG_GPIO is not set +# CONFIG_I2C is not set +# CONFIG_INPUT is not set +# CONFIG_MMC is not set +CONFIG_DM_SPI_FLASH=y +# CONFIG_SPI_FLASH_SMART_HWCAPS is not set +# CONFIG_SPI_FLASH_UNLOCK_ALL is not set +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +# CONFIG_POWER is not set +CONFIG_ARM_DCC=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ZYNQMP_GQSPI=y +# CONFIG_LMB is not set From 38e0fc06b20d527e99ae18bb99c71c5e83b86864 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Wed, 14 Jun 2023 06:13:50 -0600 Subject: [PATCH 13/40] xilinx: versal-net: Add mini ospi configuration Add support for Versal NET mini Octal SPI flash configuration. This runs from onchip memory, so it has to be compact. Hence only Octal SPI related settings are enabled. Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230614121351.21521-3-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 1 + arch/arm/dts/versal-net-mini-ospi-single.dts | 19 +++++ arch/arm/dts/versal-net-mini-ospi.dtsi | 78 +++++++++++++++++++ configs/xilinx_versal_net_mini_ospi_defconfig | 71 +++++++++++++++++ 4 files changed, 169 insertions(+) create mode 100644 arch/arm/dts/versal-net-mini-ospi-single.dts create mode 100644 arch/arm/dts/versal-net-mini-ospi.dtsi create mode 100644 configs/xilinx_versal_net_mini_ospi_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f9bc0a99318..5975f80a4a1 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -416,6 +416,7 @@ dtb-$(CONFIG_ARCH_VERSAL) += \ xilinx-versal-virt.dtb dtb-$(CONFIG_ARCH_VERSAL_NET) += \ versal-net-mini.dtb \ + versal-net-mini-ospi-single.dtb \ versal-net-mini-qspi-single.dtb \ xilinx-versal-net-virt.dtb dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \ diff --git a/arch/arm/dts/versal-net-mini-ospi-single.dts b/arch/arm/dts/versal-net-mini-ospi-single.dts new file mode 100644 index 00000000000..11a8e8b136a --- /dev/null +++ b/arch/arm/dts/versal-net-mini-ospi-single.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal NET OSPI single DTS + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + * + * Michal Simek + * Ashok Reddy Soma + */ + +#include "versal-net-mini-ospi.dtsi" + +/ { + model = "Xilinx Versal NET MINI OSPI SINGLE"; +}; + +&flash0 { + spi-rx-bus-width = <8>; +}; diff --git a/arch/arm/dts/versal-net-mini-ospi.dtsi b/arch/arm/dts/versal-net-mini-ospi.dtsi new file mode 100644 index 00000000000..ce8e2158f6e --- /dev/null +++ b/arch/arm/dts/versal-net-mini-ospi.dtsi @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal NET Mini OSPI Configuration + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + * + * Michal Simek + * Ashok Reddy Soma + */ + +/dts-v1/; + +/ { + compatible = "xlnx,versal-net-mini"; + #address-cells = <2>; + #size-cells = <2>; + model = "Xilinx Versal NET MINI OSPI"; + + aliases { + serial0 = &dcc; + spi0 = &ospi; + }; + + chosen { + stdout-path = "serial0:115200"; + }; + + memory@bbf00000 { + device_type = "memory"; + reg = <0 0xBBF00000 0 0x100000>; + }; + + clk125: clk125 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "okay"; + bootph-all; + }; + + amba: amba { + bootph-all; + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + + ospi: spi@f1010000 { + compatible = "cadence,qspi", "cdns,qspi-nor"; + status = "okay"; + reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>; + clock-names = "ref_clk", "pclk"; + clocks = <&clk125>, <&clk125>; + bus-num = <2>; + num-cs = <1>; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,is-dma = <1>; + cdns,is-stig-pgm = <1>; + cdns,trigger-address = <0xc0000000>; + #address-cells = <1>; + #size-cells = <0>; + + flash0: flash@0 { + compatible = "mt35xu02g", "micron,m25p80", + "jedec,spi-nor"; + reg = <0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <20000000>; + }; + }; + }; +}; diff --git a/configs/xilinx_versal_net_mini_ospi_defconfig b/configs/xilinx_versal_net_mini_ospi_defconfig new file mode 100644 index 00000000000..d11e180780d --- /dev/null +++ b/configs/xilinx_versal_net_mini_ospi_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_versal_net_mini" +CONFIG_COUNTER_FREQUENCY=100000000 +CONFIG_ARCH_VERSAL_NET=y +CONFIG_TEXT_BASE=0xBBF00000 +CONFIG_SYS_MALLOC_LEN=0x2000 +CONFIG_SYS_MALLOC_F_LEN=0x500 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xBBF20000 +CONFIG_SF_DEFAULT_SPEED=30000000 +CONFIG_ENV_SIZE=0x80 +# CONFIG_DM_GPIO is not set +CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-ospi-single" +CONFIG_SYS_PROMPT="Versal NET> " +CONFIG_SYS_MEM_RSVD_FOR_MMU=y +# CONFIG_PSCI_RESET is not set +CONFIG_SYS_LOAD_ADDR=0xBBF80000 +# CONFIG_EXPERT is not set +CONFIG_REMAKE_ELF=y +# CONFIG_AUTOBOOT is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_BOARD_LATE_INIT is not set +# CONFIG_CMDLINE_EDITING is not set +# CONFIG_AUTO_COMPLETE is not set +# CONFIG_SYS_LONGHELP is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_NET is not set +# CONFIG_DM_WARN is not set +# CONFIG_DM_DEVICE_REMOVE is not set +# CONFIG_MMC is not set +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_ARM_DCC=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_HAS_CQSPI_REF_CLK=y +CONFIG_CQSPI_REF_CLK=200000000 +CONFIG_CADENCE_OSPI_VERSAL=y +# CONFIG_LMB is not set From 37688da586c9e01b071efddb609b99bc49bd8126 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Wed, 14 Jun 2023 06:13:51 -0600 Subject: [PATCH 14/40] xilinx: versal-net: Add mini eMMC 5.1 configuration Add support for Versal NET mini eMMC 5.1 configuration. Add device tree and defconfig. Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230614121351.21521-4-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 1 + arch/arm/dts/versal-net-mini-emmc.dts | 64 +++++++++++++++++++ configs/xilinx_versal_net_mini_emmc_defconfig | 63 ++++++++++++++++++ 3 files changed, 128 insertions(+) create mode 100644 arch/arm/dts/versal-net-mini-emmc.dts create mode 100644 configs/xilinx_versal_net_mini_emmc_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5975f80a4a1..b13b26b861b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -416,6 +416,7 @@ dtb-$(CONFIG_ARCH_VERSAL) += \ xilinx-versal-virt.dtb dtb-$(CONFIG_ARCH_VERSAL_NET) += \ versal-net-mini.dtb \ + versal-net-mini-emmc.dtb \ versal-net-mini-ospi-single.dtb \ versal-net-mini-qspi-single.dtb \ xilinx-versal-net-virt.dtb diff --git a/arch/arm/dts/versal-net-mini-emmc.dts b/arch/arm/dts/versal-net-mini-emmc.dts new file mode 100644 index 00000000000..8a864ba3ed3 --- /dev/null +++ b/arch/arm/dts/versal-net-mini-emmc.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal NET Mini eMMC Configuration + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + * + * Michal Simek + * Ashok Reddy Soma + */ + +/dts-v1/; + +/ { + compatible = "xlnx,versal-net-mini"; + #address-cells = <2>; + #size-cells = <2>; + model = "Xilinx Versal NET MINI eMMC"; + + aliases { + serial0 = &dcc; + mmc0 = &sdhci1; + }; + + chosen { + stdout-path = "serial0:115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0 0 0 0x20000000>; + }; + + clk200: clk200 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "okay"; + bootph-all; + }; + + amba: amba { + bootph-all; + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sdhci1: sdhci@f1050000 { + compatible = "xlnx,versal-net-emmc"; + status = "okay"; + non-removable; + disable-wp; + bus-width = <8>; + reg = <0 0xf1050000 0 0x10000>; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&clk200>, <&clk200>; + xlnx,mio-bank = <0>; + }; + }; +}; diff --git a/configs/xilinx_versal_net_mini_emmc_defconfig b/configs/xilinx_versal_net_mini_emmc_defconfig new file mode 100644 index 00000000000..6d5affcd522 --- /dev/null +++ b/configs/xilinx_versal_net_mini_emmc_defconfig @@ -0,0 +1,63 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_versal_net_mini" +CONFIG_COUNTER_FREQUENCY=100000000 +CONFIG_ARCH_VERSAL_NET=y +CONFIG_TEXT_BASE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x80000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000 +CONFIG_ENV_SIZE=0x80 +CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-emmc" +CONFIG_SYS_PROMPT="Versal NET> " +# CONFIG_PSCI_RESET is not set +CONFIG_SYS_LOAD_ADDR=0x8000000 +# CONFIG_EXPERT is not set +CONFIG_REMAKE_ELF=y +# CONFIG_AUTOBOOT is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_BOARD_LATE_INIT is not set +# CONFIG_CMDLINE_EDITING is not set +# CONFIG_AUTO_COMPLETE is not set +# CONFIG_SYS_LONGHELP is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_EMBED=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +# CONFIG_DM_WARN is not set +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_ARM_DCC=y +CONFIG_FAT_WRITE=y +# CONFIG_GZIP is not set +# CONFIG_EFI_LOADER is not set +# CONFIG_LMB is not set From 5b90412cbfcbf7b1df9ed34e0dab255838f43ea5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 23 Jun 2023 14:51:57 +0200 Subject: [PATCH 15/40] xilinx: Consolidate zynqmp_mmio_read/write in zynqmp_firmware.h zynqmp_mmio_read/write() are firmware provided hooks that's why use only zynqmp_firmware.h for function declaration. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/e7489556f9e447c737a578c169d7e1e43586a273.1687524706.git.michal.simek@amd.com --- arch/arm/mach-versal-net/include/mach/sys_proto.h | 2 -- arch/arm/mach-versal/include/mach/sys_proto.h | 2 -- arch/arm/mach-zynqmp/include/mach/sys_proto.h | 3 --- arch/arm/mach-zynqmp/mp.c | 1 + drivers/clk/clk_zynqmp.c | 1 + include/zynqmp_firmware.h | 1 + 6 files changed, 3 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-versal-net/include/mach/sys_proto.h b/arch/arm/mach-versal-net/include/mach/sys_proto.h index a20cf02712b..23374d10a6b 100644 --- a/arch/arm/mach-versal-net/include/mach/sys_proto.h +++ b/arch/arm/mach-versal-net/include/mach/sys_proto.h @@ -7,5 +7,3 @@ #include void mem_map_fill(void); - -int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h index 433f9ba07c7..757bd873fbe 100644 --- a/arch/arm/mach-versal/include/mach/sys_proto.h +++ b/arch/arm/mach-versal/include/mach/sys_proto.h @@ -13,5 +13,3 @@ enum { void initialize_tcm(bool mode); void tcm_init(u8 mode); void mem_map_fill(void); - -int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index c6733ed1bbe..ede00d73fe0 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -48,9 +48,6 @@ enum { unsigned int zynqmp_get_silicon_version(void); -int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); -int zynqmp_mmio_read(const u32 address, u32 *value); - void initialize_tcm(bool mode); void mem_map_fill(void); #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP) diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c index b06c867e57f..4c514258ba6 100644 --- a/arch/arm/mach-zynqmp/mp.c +++ b/arch/arm/mach-zynqmp/mp.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index be0ee50e0e4..8320d491846 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index c56ad3f9206..18a87d27495 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -454,6 +454,7 @@ int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value); int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config, u32 value); int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id); +int zynqmp_mmio_read(const u32 address, u32 *value); int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); /* Type of Config Object */ From 378f4eef09e9d7eb09bf06643d7358abb3b0aec6 Mon Sep 17 00:00:00 2001 From: Raju Kumar Pothuraju Date: Mon, 10 Jul 2023 13:56:21 +0200 Subject: [PATCH 16/40] xilinx: zynq: Enable fdt apply utility for zynq Enables the FDT library (libfdt) overlay support for zynq platforms to be able to use fdt apply command. Signed-off-by: Raju Kumar Pothuraju Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/ab26dd186fb752b3d607e6160ae5baf6661d5de7.1688990179.git.michal.simek@amd.com --- configs/xilinx_zynq_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 474abc7f6b0..99005773459 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -7,6 +7,7 @@ CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_ENV_OFFSET=0xE00000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706" +CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL_STACK=0xfffffe00 CONFIG_SPL=y From 174d728471d50415fb60f4bcb560d0552591dfba Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 10 Jul 2023 14:35:49 +0200 Subject: [PATCH 17/40] arm64: zynqmp: Switch to amd.com emails Update my and DPs email address to match current setup. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com --- arch/arm/dts/avnet-ultra96-rev1.dts | 2 +- arch/arm/dts/versal-mini-emmc0.dts | 4 ++-- arch/arm/dts/versal-mini-emmc1.dts | 4 ++-- arch/arm/dts/versal-mini-ospi.dtsi | 4 ++-- arch/arm/dts/versal-mini-qspi.dtsi | 4 ++-- arch/arm/dts/versal-mini.dts | 2 +- arch/arm/dts/zynq-dlc20-rev1.0.dts | 2 +- arch/arm/dts/zynq-minized.dts | 2 +- arch/arm/dts/zynqmp-a2197-revA.dts | 2 +- arch/arm/dts/zynqmp-clk-ccf.dtsi | 2 +- arch/arm/dts/zynqmp-dlc21-revA.dts | 2 +- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 2 +- arch/arm/dts/zynqmp-mini-emmc0.dts | 2 +- arch/arm/dts/zynqmp-mini-emmc1.dts | 2 +- arch/arm/dts/zynqmp-mini-nand.dts | 4 ++-- arch/arm/dts/zynqmp-mini-qspi.dts | 4 ++-- arch/arm/dts/zynqmp-mini.dts | 2 +- arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-r5.dts | 2 +- arch/arm/dts/zynqmp-sck-kr-g-revA.dts | 2 +- arch/arm/dts/zynqmp-sck-kr-g-revB.dts | 2 +- arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 2 +- arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 2 +- arch/arm/dts/zynqmp-sm-k26-revA.dts | 2 +- arch/arm/dts/zynqmp-smk-k26-revA.dts | 2 +- arch/arm/dts/zynqmp-zc1232-revA.dts | 2 +- arch/arm/dts/zynqmp-zc1254-revA.dts | 4 ++-- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 4 ++-- arch/arm/dts/zynqmp-zcu100-revC.dts | 2 +- arch/arm/dts/zynqmp-zcu102-rev1.0.dts | 2 +- arch/arm/dts/zynqmp-zcu102-rev1.1.dts | 2 +- arch/arm/dts/zynqmp-zcu102-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu102-revB.dts | 2 +- arch/arm/dts/zynqmp-zcu104-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu104-revC.dts | 2 +- arch/arm/dts/zynqmp-zcu106-rev1.0.dts | 2 +- arch/arm/dts/zynqmp-zcu106-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu111-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu1275-revA.dts | 4 ++-- arch/arm/dts/zynqmp-zcu1275-revB.dts | 4 ++-- arch/arm/dts/zynqmp-zcu1285-revA.dts | 4 ++-- arch/arm/dts/zynqmp-zcu208-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu216-revA.dts | 2 +- arch/arm/dts/zynqmp.dtsi | 2 +- arch/arm/mach-tegra/arm64-mmu.c | 2 +- arch/arm/mach-versal/Makefile | 2 +- arch/arm/mach-versal/clk.c | 2 +- arch/arm/mach-versal/cpu.c | 2 +- arch/arm/mach-versal/mp.c | 2 +- arch/arm/mach-zynqmp/Makefile | 2 +- arch/arm/mach-zynqmp/clk.c | 2 +- arch/arm/mach-zynqmp/cpu.c | 2 +- arch/arm/mach-zynqmp/handoff.c | 2 +- arch/arm/mach-zynqmp/include/mach/clk.h | 2 +- arch/arm/mach-zynqmp/include/mach/hardware.h | 2 +- arch/arm/mach-zynqmp/include/mach/sys_proto.h | 2 +- arch/arm/mach-zynqmp/mp.c | 2 +- arch/arm/mach-zynqmp/psu_spl_init.c | 2 +- arch/arm/mach-zynqmp/spl.c | 2 +- arch/microblaze/cpu/spl.c | 2 +- arch/microblaze/cpu/u-boot-spl.lds | 2 +- arch/microblaze/include/asm/spl.h | 2 +- board/xilinx/common/Makefile | 2 +- board/xilinx/common/board.h | 2 +- board/xilinx/common/cpu-info.c | 2 +- board/xilinx/common/fru.h | 2 +- board/xilinx/versal/Makefile | 2 +- board/xilinx/versal/board.c | 2 +- board/xilinx/versal/cmds.c | 2 +- board/xilinx/zynqmp/Makefile | 2 +- board/xilinx/zynqmp/cmds.c | 2 +- board/xilinx/zynqmp/zynqmp.c | 2 +- common/spl/spl_ram.c | 2 +- drivers/ata/sata_ceva.c | 2 +- drivers/clk/clk_versal.c | 2 +- drivers/fpga/versalpl.c | 2 +- drivers/fpga/zynqmppl.c | 4 ++-- drivers/net/xilinx_axi_mrmac.c | 2 +- drivers/net/xilinx_axi_mrmac.h | 2 +- drivers/pinctrl/pinctrl-zynqmp.c | 2 +- drivers/soc/soc_xilinx_zynqmp.c | 2 +- drivers/watchdog/xilinx_tb_wdt.c | 2 +- drivers/watchdog/xilinx_wwdt.c | 2 +- include/configs/xilinx_versal.h | 2 +- include/configs/xilinx_versal_mini.h | 4 ++-- include/configs/xilinx_zynqmp.h | 2 +- include/configs/xilinx_zynqmp_mini.h | 4 ++-- include/configs/xilinx_zynqmp_mini_nand.h | 4 ++-- include/versalpl.h | 2 +- include/zynqmppl.h | 2 +- tools/zynqmp_psu_init_minimize.sh | 2 +- tools/zynqmpimage.c | 2 +- tools/zynqmpimage.h | 2 +- 101 files changed, 116 insertions(+), 116 deletions(-) diff --git a/arch/arm/dts/avnet-ultra96-rev1.dts b/arch/arm/dts/avnet-ultra96-rev1.dts index ddb8febaece..96a6403efaf 100644 --- a/arch/arm/dts/avnet-ultra96-rev1.dts +++ b/arch/arm/dts/avnet-ultra96-rev1.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018 - 2020, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/versal-mini-emmc0.dts b/arch/arm/dts/versal-mini-emmc0.dts index 1863d29d3da..bd685ddfdb4 100644 --- a/arch/arm/dts/versal-mini-emmc0.dts +++ b/arch/arm/dts/versal-mini-emmc0.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2018-2019, Xilinx, Inc. * - * Siva Durga Prasad - * Michal Simek + * Siva Durga Prasad > + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/versal-mini-emmc1.dts b/arch/arm/dts/versal-mini-emmc1.dts index 8701c3bb273..fbdcf5d77f5 100644 --- a/arch/arm/dts/versal-mini-emmc1.dts +++ b/arch/arm/dts/versal-mini-emmc1.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2018-2019, Xilinx, Inc. * - * Siva Durga Prasad - * Michal Simek + * Siva Durga Prasad > + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/versal-mini-ospi.dtsi b/arch/arm/dts/versal-mini-ospi.dtsi index 2d04521dd67..19caea7368a 100644 --- a/arch/arm/dts/versal-mini-ospi.dtsi +++ b/arch/arm/dts/versal-mini-ospi.dtsi @@ -4,8 +4,8 @@ * * (C) Copyright 2018-2019, Xilinx, Inc. * - * Siva Durga Prasad - * Michal Simek + * Siva Durga Prasad > + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/versal-mini-qspi.dtsi b/arch/arm/dts/versal-mini-qspi.dtsi index bb8819dd25f..2fec92ce3ec 100644 --- a/arch/arm/dts/versal-mini-qspi.dtsi +++ b/arch/arm/dts/versal-mini-qspi.dtsi @@ -4,8 +4,8 @@ * * (C) Copyright 2018-2019, Xilinx, Inc. * - * Siva Durga Prasad - * Michal Simek + * Siva Durga Prasad > + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/versal-mini.dts b/arch/arm/dts/versal-mini.dts index 769eb9e7b29..a213b745bc2 100644 --- a/arch/arm/dts/versal-mini.dts +++ b/arch/arm/dts/versal-mini.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019, Xilinx, Inc. * - * Siva Durga Prasad Paladugu + * Siva Durga Prasad Paladugu > */ /dts-v1/; diff --git a/arch/arm/dts/zynq-dlc20-rev1.0.dts b/arch/arm/dts/zynq-dlc20-rev1.0.dts index cfe07102297..d06838c5eeb 100644 --- a/arch/arm/dts/zynq-dlc20-rev1.0.dts +++ b/arch/arm/dts/zynq-dlc20-rev1.0.dts @@ -2,7 +2,7 @@ /* * Copyright (C) 2018 Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; #include "zynq-7000.dtsi" diff --git a/arch/arm/dts/zynq-minized.dts b/arch/arm/dts/zynq-minized.dts index 38365d1c0ec..3214ee49e28 100644 --- a/arch/arm/dts/zynq-minized.dts +++ b/arch/arm/dts/zynq-minized.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2018, Xilinx, Inc. * - * Ibai Erkiaga + * Ibai Erkiaga */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-a2197-revA.dts b/arch/arm/dts/zynqmp-a2197-revA.dts index 04f9f025e5c..84167050d10 100644 --- a/arch/arm/dts/zynqmp-a2197-revA.dts +++ b/arch/arm/dts/zynqmp-a2197-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 38dc9cd8fc0..173e4bc5f1d 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ #include diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts index 7460e4a4fde..e287a9b6591 100644 --- a/arch/arm/dts/zynqmp-dlc21-revA.dts +++ b/arch/arm/dts/zynqmp-dlc21-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index 3fa18f560c9..e24d070adb6 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index 02d2427809d..b185669b9c5 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index 2d7fe592c8f..aa4f7c23ede 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index e46748d32c0..7aa8c2b4d1f 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index f564817e2c8..459736abe6b 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts b/arch/arm/dts/zynqmp-mini-emmc0.dts index d1e58eb6d13..08ec2f7b4a9 100644 --- a/arch/arm/dts/zynqmp-mini-emmc0.dts +++ b/arch/arm/dts/zynqmp-mini-emmc0.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018, Xilinx, Inc. * - * Siva Durga Prasad + * Siva Durga Prasad > */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts index 0c139f82aa0..905de08fdb0 100644 --- a/arch/arm/dts/zynqmp-mini-emmc1.dts +++ b/arch/arm/dts/zynqmp-mini-emmc1.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018, Xilinx, Inc. * - * Siva Durga Prasad + * Siva Durga Prasad > */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-mini-nand.dts b/arch/arm/dts/zynqmp-mini-nand.dts index 8fae01b250d..e5688fd703e 100644 --- a/arch/arm/dts/zynqmp-mini-nand.dts +++ b/arch/arm/dts/zynqmp-mini-nand.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2018, Xilinx, Inc. * - * Siva Durga Prasad - * Michal Simek + * Siva Durga Prasad > + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts index a7cf4eff6cc..fc0a2e801e4 100644 --- a/arch/arm/dts/zynqmp-mini-qspi.dts +++ b/arch/arm/dts/zynqmp-mini-qspi.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2015 - 2020, Xilinx, Inc. * - * Siva Durga Prasad - * Michal Simek + * Siva Durga Prasad > + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-mini.dts b/arch/arm/dts/zynqmp-mini.dts index 15bee169a90..b9a24f04363 100644 --- a/arch/arm/dts/zynqmp-mini.dts +++ b/arch/arm/dts/zynqmp-mini.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts index d63deb83e3c..d5f4a16f20e 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-r5.dts b/arch/arm/dts/zynqmp-r5.dts index 9789d7144e6..77b15fe158c 100644 --- a/arch/arm/dts/zynqmp-r5.dts +++ b/arch/arm/dts/zynqmp-r5.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts index c82e1dfac9d..95347604a27 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ #include diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts index 9dd160c7a7c..26ac540e7b0 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2021 - 2022, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ #include diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts index 6f5a4260656..2b6c3946e85 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts @@ -9,7 +9,7 @@ * "Y" – A01 board modified with legacy interposer (Nexperia) * "Z" – A01 board modified with Diode interposer * - * Michal Simek + * Michal Simek */ #include diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts index 7764adf1295..308d7876b88 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2020 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ #include diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index eac0b55de36..e9ec4b79fc1 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2020 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-smk-k26-revA.dts b/arch/arm/dts/zynqmp-smk-k26-revA.dts index c70966c1f34..85b0d167724 100644 --- a/arch/arm/dts/zynqmp-smk-k26-revA.dts +++ b/arch/arm/dts/zynqmp-smk-k26-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2020 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ #include "zynqmp-sm-k26-revA.dts" diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts index 63c553f7724..a288029797b 100644 --- a/arch/arm/dts/zynqmp-zc1232-revA.dts +++ b/arch/arm/dts/zynqmp-zc1232-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts index 343033cc7e8..5c4acd17cc5 100644 --- a/arch/arm/dts/zynqmp-zc1254-revA.dts +++ b/arch/arm/dts/zynqmp-zc1254-revA.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2015 - 2020, Xilinx, Inc. * - * Michal Simek - * Siva Durga Prasad Paladugu + * Michal Simek + * Siva Durga Prasad Paladugu > */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 7ea2a1c96f4..b663651583c 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index b6bc2f5be03..9d0cf11665c 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts index 6021f8b4e1b..69ad58039e7 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index e153a64f4fb..3017c9b29a2 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index ae2d03d9832..7f973fcf4da 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Siva Durga Prasad - * Michal Simek + * Siva Durga Prasad > + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index 742a5398646..116037dbe73 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek * Nathalie Chan King Choy */ diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts index d508f335994..c0a4d913afe 100644 --- a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts +++ b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2020, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ #include "zynqmp-zcu102-revB.dts" diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.1.dts b/arch/arm/dts/zynqmp-zcu102-rev1.1.dts index b6798394fcf..705369766a5 100644 --- a/arch/arm/dts/zynqmp-zcu102-rev1.1.dts +++ b/arch/arm/dts/zynqmp-zcu102-rev1.1.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2020, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ #include "zynqmp-zcu102-rev1.0.dts" diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index d78bfb8987f..8823eb2462e 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts index de3b5ab9d93..ce0a6e5f60a 100644 --- a/arch/arm/dts/zynqmp-zcu102-revB.dts +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2020, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ #include "zynqmp-zcu102-revA.dts" diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index b9d82afc518..92e01ac921e 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 6f24e335a19..c61d8b15ee2 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu106-rev1.0.dts b/arch/arm/dts/zynqmp-zcu106-rev1.0.dts index f43c477a17f..a9b5826a777 100644 --- a/arch/arm/dts/zynqmp-zcu106-rev1.0.dts +++ b/arch/arm/dts/zynqmp-zcu106-rev1.0.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2022, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ #include "zynqmp-zcu106-revA.dts" diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 266c24e4125..67775eceaa8 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 8535cc08913..7fc1aa238a6 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts index e88fc23b1f1..9404c139a24 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek - * Siva Durga Prasad Paladugu + * Michal Simek + * Siva Durga Prasad Paladugu > */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts index 97ae1b2d2d7..c06d262506d 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revB.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2018 - 2021, Xilinx, Inc. * - * Michal Simek - * Siva Durga Prasad Paladugu + * Michal Simek + * Siva Durga Prasad Paladugu > */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts index eaf99a9fa82..99ea143c02e 100644 --- a/arch/arm/dts/zynqmp-zcu1285-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2018 - 2021, Xilinx, Inc. * - * Michal Simek - * Siva Durga Prasad Paladugu + * Michal Simek + * Siva Durga Prasad Paladugu > */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 7e7e1577eb5..1fac632d631 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index 35a30971cb7..ea96f5c8014 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 6a166381fa7..c9640c44451 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -4,7 +4,7 @@ * * (C) Copyright 2014 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c index d45b1faaa2c..ea4eac392d9 100644 --- a/arch/arm/mach-tegra/arm64-mmu.c +++ b/arch/arm/mach-tegra/arm64-mmu.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek + * Michal Simek * (This file derived from arch/arm/mach-zynqmp/cpu.c) * * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. diff --git a/arch/arm/mach-versal/Makefile b/arch/arm/mach-versal/Makefile index ca12e29170d..864b3053d69 100644 --- a/arch/arm/mach-versal/Makefile +++ b/arch/arm/mach-versal/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # # (C) Copyright 2016 - 2018 Xilinx, Inc. -# Michal Simek +# Michal Simek # obj-y += clk.o diff --git a/arch/arm/mach-versal/clk.c b/arch/arm/mach-versal/clk.c index 249e050cc8d..5e3f44c7782 100644 --- a/arch/arm/mach-versal/clk.c +++ b/arch/arm/mach-versal/clk.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2016 - 2018 Xilinx, Inc. - * Michal Simek + * Michal Simek */ #include diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index 9dc308bbc3d..e4dc305d928 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2016 - 2018 Xilinx, Inc. - * Michal Simek + * Michal Simek */ #include diff --git a/arch/arm/mach-versal/mp.c b/arch/arm/mach-versal/mp.c index 5b850f3f89f..7bd39289fac 100644 --- a/arch/arm/mach-versal/mp.c +++ b/arch/arm/mach-versal/mp.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * (C) Copyright 2019 Xilinx, Inc. - * Siva Durga Prasad + * Siva Durga Prasad > */ #include diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile index bb1830c8462..3f255549439 100644 --- a/arch/arm/mach-zynqmp/Makefile +++ b/arch/arm/mach-zynqmp/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # # (C) Copyright 2014 - 2015 Xilinx, Inc. -# Michal Simek +# Michal Simek obj-y += clk.o obj-y += cpu.o diff --git a/arch/arm/mach-zynqmp/clk.c b/arch/arm/mach-zynqmp/clk.c index 1e6e726e879..3b05f8455bf 100644 --- a/arch/arm/mach-zynqmp/clk.c +++ b/arch/arm/mach-zynqmp/clk.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek + * Michal Simek */ #include diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index 26e285c24fe..6ae27894ecd 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek + * Michal Simek */ #include diff --git a/arch/arm/mach-zynqmp/handoff.c b/arch/arm/mach-zynqmp/handoff.c index 511b241462f..dce92438926 100644 --- a/arch/arm/mach-zynqmp/handoff.c +++ b/arch/arm/mach-zynqmp/handoff.c @@ -2,7 +2,7 @@ /* * Copyright 2016 - 2017 Xilinx, Inc. * - * Michal Simek + * Michal Simek */ #include diff --git a/arch/arm/mach-zynqmp/include/mach/clk.h b/arch/arm/mach-zynqmp/include/mach/clk.h index cfd44c8e0f7..9918d469122 100644 --- a/arch/arm/mach-zynqmp/include/mach/clk.h +++ b/arch/arm/mach-zynqmp/include/mach/clk.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek + * Michal Simek */ #ifndef _ASM_ARCH_CLK_H_ diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h index 70221e03057..634bf169c63 100644 --- a/arch/arm/mach-zynqmp/include/mach/hardware.h +++ b/arch/arm/mach-zynqmp/include/mach/hardware.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek + * Michal Simek */ #ifndef _ASM_ARCH_HARDWARE_H diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index ede00d73fe0..15b69e77712 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek + * Michal Simek */ #ifndef _ASM_ARCH_SYS_PROTO_H diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c index 4c514258ba6..aff9054212c 100644 --- a/arch/arm/mach-zynqmp/mp.c +++ b/arch/arm/mach-zynqmp/mp.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek + * Michal Simek */ #include diff --git a/arch/arm/mach-zynqmp/psu_spl_init.c b/arch/arm/mach-zynqmp/psu_spl_init.c index 5c5c7d136e7..b4d7f44bbee 100644 --- a/arch/arm/mach-zynqmp/psu_spl_init.c +++ b/arch/arm/mach-zynqmp/psu_spl_init.c @@ -2,7 +2,7 @@ /* * Copyright 2018 Xilinx, Inc. * - * Michal Simek + * Michal Simek */ #include #include diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c index b428fd53121..a0f35f36faa 100644 --- a/arch/arm/mach-zynqmp/spl.c +++ b/arch/arm/mach-zynqmp/spl.c @@ -2,7 +2,7 @@ /* * Copyright 2015 - 2016 Xilinx, Inc. * - * Michal Simek + * Michal Simek */ #include diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c index eaa095ba99f..c21beafdb81 100644 --- a/arch/microblaze/cpu/spl.c +++ b/arch/microblaze/cpu/spl.c @@ -2,7 +2,7 @@ /* * (C) Copyright 2013 - 2014 Xilinx, Inc * - * Michal Simek + * Michal Simek */ #include diff --git a/arch/microblaze/cpu/u-boot-spl.lds b/arch/microblaze/cpu/u-boot-spl.lds index 597095195ca..09abbea84d0 100644 --- a/arch/microblaze/cpu/u-boot-spl.lds +++ b/arch/microblaze/cpu/u-boot-spl.lds @@ -2,7 +2,7 @@ /* * (C) Copyright 2013 - 2014 Xilinx, Inc * - * Michal Simek + * Michal Simek */ #include diff --git a/arch/microblaze/include/asm/spl.h b/arch/microblaze/include/asm/spl.h index 350d283124e..7557dc2a5a3 100644 --- a/arch/microblaze/include/asm/spl.h +++ b/arch/microblaze/include/asm/spl.h @@ -2,7 +2,7 @@ /* * (C) Copyright 2013 - 2014 Xilinx, Inc * - * Michal Simek + * Michal Simek */ #ifndef _ASM_MICROBLAZE_SPL_H_ diff --git a/board/xilinx/common/Makefile b/board/xilinx/common/Makefile index cdc3c967743..d563290ab90 100644 --- a/board/xilinx/common/Makefile +++ b/board/xilinx/common/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 # # (C) Copyright 2020 Xilinx, Inc. -# Michal Simek +# Michal Simek # obj-y += board.o diff --git a/board/xilinx/common/board.h b/board/xilinx/common/board.h index 922c9d557af..64d657673e9 100644 --- a/board/xilinx/common/board.h +++ b/board/xilinx/common/board.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * (C) Copyright 2020 Xilinx, Inc. - * Michal Simek + * Michal Simek */ #ifndef _BOARD_XILINX_COMMON_BOARD_H diff --git a/board/xilinx/common/cpu-info.c b/board/xilinx/common/cpu-info.c index 4eccc7abbea..bfe7f5b7e38 100644 --- a/board/xilinx/common/cpu-info.c +++ b/board/xilinx/common/cpu-info.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 - 2020 Xilinx, Inc. - * Michal Simek + * Michal Simek */ #include diff --git a/board/xilinx/common/fru.h b/board/xilinx/common/fru.h index 586c41b66ef..2b3fa05a613 100644 --- a/board/xilinx/common/fru.h +++ b/board/xilinx/common/fru.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2019 Xilinx, Inc. - * Siva Durga Prasad Paladugu + * Siva Durga Prasad Paladugu > */ #ifndef __FRU_H diff --git a/board/xilinx/versal/Makefile b/board/xilinx/versal/Makefile index 4a46ca02d70..d912f2e74f3 100644 --- a/board/xilinx/versal/Makefile +++ b/board/xilinx/versal/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # # (C) Copyright 2016 - 2018 Xilinx, Inc. -# Michal Simek +# Michal Simek # obj-y := board.o diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 81e1b69905e..60bf37d3c90 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 - 2018 Xilinx, Inc. - * Michal Simek + * Michal Simek */ #include diff --git a/board/xilinx/versal/cmds.c b/board/xilinx/versal/cmds.c index 797c1a5d689..148fa51266d 100644 --- a/board/xilinx/versal/cmds.c +++ b/board/xilinx/versal/cmds.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * (C) Copyright 2020 Xilinx, Inc. - * Michal Simek + * Michal Simek */ #include diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile index 732f909fc21..204e4fadf0e 100644 --- a/board/xilinx/zynqmp/Makefile +++ b/board/xilinx/zynqmp/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # # (C) Copyright 2014 - 2016 Xilinx, Inc. -# Michal Simek +# Michal Simek obj-y := zynqmp.o diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c index dd1ad66f90c..ea404d547f6 100644 --- a/board/xilinx/zynqmp/cmds.c +++ b/board/xilinx/zynqmp/cmds.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * (C) Copyright 2018 Xilinx, Inc. - * Siva Durga Prasad Paladugu + * Siva Durga Prasad Paladugu > */ #include diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 39da96bcfb0..309f24a5f43 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek + * Michal Simek */ #include diff --git a/common/spl/spl_ram.c b/common/spl/spl_ram.c index 8139a203273..93cf420d810 100644 --- a/common/spl/spl_ram.c +++ b/common/spl/spl_ram.c @@ -6,7 +6,7 @@ * (C) Copyright 2016 * Toradex AG * - * Michal Simek + * Michal Simek * Stefan Agner */ #include diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c index 43bcc59cd28..47366438fdf 100644 --- a/drivers/ata/sata_ceva.c +++ b/drivers/ata/sata_ceva.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2015 - 2016 Xilinx, Inc. - * Michal Simek + * Michal Simek */ #include #include diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index faebbab1c6d..b3b33331235 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2019 Xilinx, Inc. - * Siva Durga Prasad Paladugu + * Siva Durga Prasad Paladugu > */ #include diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c index d3876a8f541..be58db54275 100644 --- a/drivers/fpga/versalpl.c +++ b/drivers/fpga/versalpl.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * (C) Copyright 2019, Xilinx, Inc, - * Siva Durga Prasad Paladugu + * Siva Durga Prasad Paladugu > */ #include diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index 7b5128fe27a..b1f201fb18b 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* * (C) Copyright 2015 - 2016, Xilinx, Inc, - * Michal Simek - * Siva Durga Prasad + * Michal Simek + * Siva Durga Prasad > */ #include diff --git a/drivers/net/xilinx_axi_mrmac.c b/drivers/net/xilinx_axi_mrmac.c index 6d15386c66c..410fb25ddef 100644 --- a/drivers/net/xilinx_axi_mrmac.c +++ b/drivers/net/xilinx_axi_mrmac.c @@ -3,7 +3,7 @@ * Xilinx Multirate Ethernet MAC(MRMAC) driver * * Author(s): Ashok Reddy Soma - * Michal Simek + * Michal Simek * * Copyright (C) 2021 Xilinx, Inc. All rights reserved. */ diff --git a/drivers/net/xilinx_axi_mrmac.h b/drivers/net/xilinx_axi_mrmac.h index 4f875857cf7..e2c2105450c 100644 --- a/drivers/net/xilinx_axi_mrmac.h +++ b/drivers/net/xilinx_axi_mrmac.h @@ -3,7 +3,7 @@ * Xilinx Multirate Ethernet MAC(MRMAC) driver * * Author(s): Ashok Reddy Soma - * Michal Simek + * Michal Simek * * Copyright (C) 2021 Xilinx, Inc. All rights reserved. */ diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index ee6529b3c29..02626a7561e 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -3,7 +3,7 @@ * Xilinx pinctrl driver for ZynqMP * * Author(s): Ashok Reddy Soma - * Michal Simek + * Michal Simek * * Copyright (C) 2021 Xilinx, Inc. All rights reserved. */ diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c index afa277f6049..d9a5944965b 100644 --- a/drivers/soc/soc_xilinx_zynqmp.c +++ b/drivers/soc/soc_xilinx_zynqmp.c @@ -3,7 +3,7 @@ * Xilinx ZynqMP SOC driver * * Copyright (C) 2021 Xilinx, Inc. - * Michal Simek + * Michal Simek * * Copyright (C) 2022 Weidmüller Interface GmbH & Co. KG * Stefan Herbrechtsmeier diff --git a/drivers/watchdog/xilinx_tb_wdt.c b/drivers/watchdog/xilinx_tb_wdt.c index 0f9fb020028..b38c4000161 100644 --- a/drivers/watchdog/xilinx_tb_wdt.c +++ b/drivers/watchdog/xilinx_tb_wdt.c @@ -2,7 +2,7 @@ /* * Xilinx AXI platforms watchdog timer driver. * - * Author(s): Michal Simek + * Author(s): Michal Simek * Shreenidhi Shedi * * Copyright (c) 2011-2018 Xilinx Inc. diff --git a/drivers/watchdog/xilinx_wwdt.c b/drivers/watchdog/xilinx_wwdt.c index 8b6fc30edbe..963ab22fb45 100644 --- a/drivers/watchdog/xilinx_wwdt.c +++ b/drivers/watchdog/xilinx_wwdt.c @@ -2,7 +2,7 @@ /* * Xilinx window watchdog timer driver. * - * Author(s): Michal Simek + * Author(s): Michal Simek * Ashok Reddy Soma * * Copyright (c) 2020, Xilinx Inc. diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index e70acd93bac..a403999977e 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -2,7 +2,7 @@ /* * Configuration for Xilinx Versal * (C) Copyright 2016 - 2018 Xilinx, Inc. - * Michal Simek + * Michal Simek * * Based on Configuration for Xilinx ZynqMP */ diff --git a/include/configs/xilinx_versal_mini.h b/include/configs/xilinx_versal_mini.h index 23655a47522..628fd80baa6 100644 --- a/include/configs/xilinx_versal_mini.h +++ b/include/configs/xilinx_versal_mini.h @@ -3,8 +3,8 @@ * Configuration for Xilinx Versal MINI configuration * * (C) Copyright 2018-2019 Xilinx, Inc. - * Michal Simek - * Siva Durga Prasad Paladugu + * Michal Simek + * Siva Durga Prasad Paladugu > */ #ifndef __CONFIG_VERSAL_MINI_H diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 995427db63c..74264b7bee8 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -2,7 +2,7 @@ /* * Configuration for Xilinx ZynqMP * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek + * Michal Simek * * Based on Configuration for Versatile Express */ diff --git a/include/configs/xilinx_zynqmp_mini.h b/include/configs/xilinx_zynqmp_mini.h index 9af05456640..8afccb7f737 100644 --- a/include/configs/xilinx_zynqmp_mini.h +++ b/include/configs/xilinx_zynqmp_mini.h @@ -3,8 +3,8 @@ * Configuration for Xilinx ZynqMP Flash utility * * (C) Copyright 2018 Xilinx, Inc. - * Michal Simek - * Siva Durga Prasad Paladugu + * Michal Simek + * Siva Durga Prasad Paladugu > */ #ifndef __CONFIG_ZYNQMP_MINI_H diff --git a/include/configs/xilinx_zynqmp_mini_nand.h b/include/configs/xilinx_zynqmp_mini_nand.h index 1b6e26ee396..cf3747aab14 100644 --- a/include/configs/xilinx_zynqmp_mini_nand.h +++ b/include/configs/xilinx_zynqmp_mini_nand.h @@ -3,8 +3,8 @@ * Configuration for Xilinx ZynqMP Nand Flash utility * * (C) Copyright 2018 Xilinx, Inc. - * Michal Simek - * Siva Durga Prasad Paladugu + * Michal Simek + * Siva Durga Prasad Paladugu > */ #ifndef __CONFIG_ZYNQMP_MINI_NAND_H diff --git a/include/versalpl.h b/include/versalpl.h index 0cc101be2f8..7dae56b2360 100644 --- a/include/versalpl.h +++ b/include/versalpl.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * (C) Copyright 2019 Xilinx, Inc, - * Siva Durga Prasad Paladugu + * Siva Durga Prasad Paladugu > */ #ifndef _VERSALPL_H_ diff --git a/include/zynqmppl.h b/include/zynqmppl.h index acf75a8f079..3fd334a54d3 100644 --- a/include/zynqmppl.h +++ b/include/zynqmppl.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * (C) Copyright 2015 Xilinx, Inc, - * Michal Simek + * Michal Simek */ #ifndef _ZYNQMPPL_H_ diff --git a/tools/zynqmp_psu_init_minimize.sh b/tools/zynqmp_psu_init_minimize.sh index 16c622f6ce7..5c8b73703bf 100755 --- a/tools/zynqmp_psu_init_minimize.sh +++ b/tools/zynqmp_psu_init_minimize.sh @@ -1,6 +1,6 @@ #!/bin/bash # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2018 Michal Simek +# Copyright (C) 2018 Michal Simek # Copyright (C) 2019 Luca Ceresoli # Copyright (C) 2022 Weidmüller Interface GmbH & Co. KG # Stefan Herbrechtsmeier diff --git a/tools/zynqmpimage.c b/tools/zynqmpimage.c index 5113ba895f0..bb54f41a153 100644 --- a/tools/zynqmpimage.c +++ b/tools/zynqmpimage.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2016 Michal Simek + * Copyright (C) 2016 Michal Simek * Copyright (C) 2015 Nathan Rossi * * The following Boot Header format/structures and values are defined in the diff --git a/tools/zynqmpimage.h b/tools/zynqmpimage.h index 9d526a17cdd..ca7489835a8 100644 --- a/tools/zynqmpimage.h +++ b/tools/zynqmpimage.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2016 Michal Simek + * Copyright (C) 2016 Michal Simek * Copyright (C) 2015 Nathan Rossi * * The following Boot Header format/structures and values are defined in the From 752e4b6c8efb5bd624f316f7a9686d9956d55dd7 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Mon, 10 Jul 2023 14:11:59 +0200 Subject: [PATCH 18/40] mmc: zynq_sdhci: Dll reset only for ZynqMP platform Dll reset is needed only for ZynqMP platforms, add condition in tuning to call arasan_zynqmp_dll_reset() just for ZynqMP platforms. On other platforms like Versal NET, If this condition is not added, we see PLM error messages when dll reset smc is called. Signed-off-by: Ashok Reddy Soma Reviewed-by: Jaehoon Chung Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/d673ff3bdc5c236a7f0403c920e719684abd6059.1688991117.git.michal.simek@amd.com --- drivers/mmc/zynq_sdhci.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index e779251ce34..935540d1719 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -422,7 +422,8 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) mdelay(1); - arasan_zynqmp_dll_reset(host, priv->node_id); + if (device_is_compatible(mmc->dev, "xlnx,zynqmp-8.9a")) + arasan_zynqmp_dll_reset(host, priv->node_id); sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); @@ -468,7 +469,9 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) } udelay(1); - arasan_zynqmp_dll_reset(host, priv->node_id); + + if (device_is_compatible(mmc->dev, "xlnx,zynqmp-8.9a")) + arasan_zynqmp_dll_reset(host, priv->node_id); /* Enable only interrupts served by the SD controller */ sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, From ed4a0ccb6e7d7fa2e8b92f5c07590a361a6efd30 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 4 Jul 2023 14:04:04 +0200 Subject: [PATCH 19/40] mtd: Add missing MTD dependency for cfi_mtd cfi_mtd requires add_mtd_device() which is available only when MTD is enabled that's why record this dependency. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/76ae01ce2b2c988758b69e0f0cdcc21bf301c01e.1688472227.git.michal.simek@amd.com --- drivers/mtd/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 5fa88dae5f3..c56840c8497 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -128,7 +128,7 @@ config FLASH_SPANSION_S29WS_N config FLASH_CFI_MTD bool "Enable CFI MTD driver" - depends on FLASH_CFI_DRIVER + depends on FLASH_CFI_DRIVER && MTD help This option enables the building of the cfi_mtd driver in the drivers directory. The driver exports CFI flash From 39bdb9649810a1d664e21e92ae8b9553e798a0e8 Mon Sep 17 00:00:00 2001 From: Varalaxmi Bingi Date: Mon, 10 Jul 2023 14:37:27 +0200 Subject: [PATCH 20/40] arm: xilinx: Setting default i2c clock frequency to 400kHz Setting default i2c clock frequency for Zynq and ZynqMP to maximum rate of 400kHz. Current default value is 100kHz. Signed-off-by: Varalaxmi Bingi Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/fb46fe911a68b79c8e4d150ca90c4e94eb5fb9e1.1688992653.git.michal.simek@amd.com --- arch/arm/dts/zynq-7000.dtsi | 2 ++ arch/arm/dts/zynqmp.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 97a9e49a19c..8c6eafec1d4 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -153,6 +153,7 @@ clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; + clock-frequency = <400000>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; @@ -164,6 +165,7 @@ clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; + clock-frequency = <400000>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index c9640c44451..5f1e163e87f 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -611,6 +611,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; + clock-frequency = <400000>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; @@ -622,6 +623,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; + clock-frequency = <400000>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; From 28dc356e66c98daedffc4960919f13aeb4b159de Mon Sep 17 00:00:00 2001 From: Manikanta Guntupalli Date: Mon, 10 Jul 2023 14:37:28 +0200 Subject: [PATCH 21/40] xilinx: dts: Fix open drain warning on Zynq, ZynqMP and Versal Fix for below open drain warning on Zynq, ZynqMP and Versal reported by Linux. "enforced open drain please flag it properly in DT/ACPI DSDT/board file." Signed-off-by: Manikanta Guntupalli Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/056b6f60f89fa2addb762669b80640cd5b31b001.1688992653.git.michal.simek@amd.com --- arch/arm/dts/zynq-zc702.dts | 5 +++-- arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 4 ++-- arch/arm/dts/zynqmp-sck-kr-g-revA.dts | 4 ++-- arch/arm/dts/zynqmp-sck-kr-g-revB.dts | 4 ++-- arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 4 ++-- arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 4 ++-- arch/arm/dts/zynqmp-sm-k26-revA.dts | 4 ++-- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 4 ++-- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 4 ++-- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 8 ++++---- arch/arm/dts/zynqmp-zcu100-revC.dts | 4 ++-- arch/arm/dts/zynqmp-zcu102-revA.dts | 8 ++++---- arch/arm/dts/zynqmp-zcu104-revA.dts | 4 ++-- arch/arm/dts/zynqmp-zcu104-revC.dts | 4 ++-- arch/arm/dts/zynqmp-zcu106-revA.dts | 8 ++++---- arch/arm/dts/zynqmp-zcu111-revA.dts | 8 ++++---- arch/arm/dts/zynqmp-zcu208-revA.dts | 8 ++++---- arch/arm/dts/zynqmp-zcu216-revA.dts | 8 ++++---- 18 files changed, 49 insertions(+), 48 deletions(-) diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index 27fb194fc9e..8d47f24b757 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -5,6 +5,7 @@ */ /dts-v1/; #include "zynq-7000.dtsi" +#include / { model = "Xilinx ZC702 board"; @@ -102,8 +103,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio0 50 0>; - sda-gpios = <&gpio0 51 0>; + scl-gpios = <&gpio0 50 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 51 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { compatible = "nxp,pca9548"; diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index b185669b9c5..11142401151 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -131,8 +131,8 @@ &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; - scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { /* u94 */ compatible = "nxp,pca9548"; #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts index 95347604a27..5ac66bc1ec5 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts @@ -68,8 +68,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts index 26ac540e7b0..401de9efb91 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts @@ -68,8 +68,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts index 2b6c3946e85..8229244d241 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts @@ -34,8 +34,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts index 308d7876b88..96a51219f42 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts @@ -28,8 +28,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index e9ec4b79fc1..4b88b57e0c2 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -267,8 +267,8 @@ status = "okay"; bootph-all; clock-frequency = <400000>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ bootph-all; diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index b663651583c..cffad447406 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -118,8 +118,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index 9d0cf11665c..bb0477825a9 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -109,8 +109,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index 7f973fcf4da..74a5b020e86 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -91,8 +91,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 74 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 75 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 74 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 75 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; }; &i2c1 { @@ -100,8 +100,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 76 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 77 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 76 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 77 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; }; diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index 116037dbe73..78c32507600 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -188,8 +188,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 8823eb2462e..79d67c495de 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -232,8 +232,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; @@ -496,8 +496,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 92e01ac921e..90fbfca87f2 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -139,8 +139,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index c61d8b15ee2..69470f8dede 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -144,8 +144,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 67775eceaa8..7a8094a16b7 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -232,8 +232,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; @@ -495,8 +495,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 7fc1aa238a6..c9ff99f8a83 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -204,8 +204,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; @@ -384,8 +384,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 1fac632d631..5ad07d30b8b 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -231,8 +231,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; @@ -397,8 +397,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index ea96f5c8014..574e4845be8 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -241,8 +241,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; @@ -407,8 +407,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ From d95fc99a740583f8656f0b048071f1ec34c963a4 Mon Sep 17 00:00:00 2001 From: Parth Gajjar Date: Mon, 10 Jul 2023 14:37:29 +0200 Subject: [PATCH 22/40] arm64: zynqmp: Update MALI 400 interrupt and clock names Motivation for the commit is to utilize the upstream community device tree so that the either modified ARM Mali 400 driver or upstream lima driver can be used. Signed-off-by: Parth Gajjar Signed-off-by: Vishal Sagar Link: https://lore.kernel.org/r/1678181001-2327-2-git-send-email-parth.gajjar@amd.com Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/89d046a9da5638e8b4918f80f3245d73ea46f99f.1688992653.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-clk-ccf.dtsi | 2 +- arch/arm/dts/zynqmp.dtsi | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 173e4bc5f1d..4d44924f663 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -126,7 +126,7 @@ }; &gpu { - clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>; + clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>; }; &lpd_dma_chan1 { diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 5f1e163e87f..38114d55386 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -396,12 +396,12 @@ gpu: gpu@fd4b0000 { status = "disabled"; - compatible = "arm,mali-400", "arm,mali-utgard"; + compatible = "xlnx,zynqmp-mali", "arm,mali-400"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; - interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; - clock-names = "gpu", "gpu_pp0", "gpu_pp1"; + interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1"; + clock-names = "bus", "core"; power-domains = <&zynqmp_firmware PD_GPU>; }; From f6689614856b7eb9099dbbe21c8880ffbd80514e Mon Sep 17 00:00:00 2001 From: Harini Katakam Date: Mon, 10 Jul 2023 14:37:30 +0200 Subject: [PATCH 23/40] arm64: zynqmp: Assign TSU clock frequency for KR260 Set TSU clock frequency as 250MHz (minimum when running at 1G) on KR260 CC to allow PTP functionality. Signed-off-by: Harini Katakam Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/d065b5c2c6450910bf57d104d65946111493caaa.1688992653.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-clk-ccf.dtsi | 4 ++++ arch/arm/dts/zynqmp-sck-kr-g-revA.dts | 2 ++ arch/arm/dts/zynqmp-sck-kr-g-revB.dts | 2 ++ 3 files changed, 8 insertions(+) diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 4d44924f663..a21dca87d24 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -169,24 +169,28 @@ clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>; + assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gem1 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>; + assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gem2 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>; + assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gem3 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>; + assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gpio { diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts index 5ac66bc1ec5..caaf71d729e 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts @@ -188,6 +188,7 @@ phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; + assigned-clock-rates = <250000000>; }; &gem1 { /* mdio mio50/51, gem mio38 - mio49 */ @@ -196,6 +197,7 @@ pinctrl-0 = <&pinctrl_gem1_default>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; + assigned-clock-rates = <250000000>; mdio: mdio { #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts index 401de9efb91..f9d87559a71 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts @@ -188,6 +188,7 @@ phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; + assigned-clock-rates = <250000000>; }; &gem1 { /* mdio mio50/51, gem mio38 - mio49 */ @@ -196,6 +197,7 @@ pinctrl-0 = <&pinctrl_gem1_default>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; + assigned-clock-rates = <250000000>; mdio: mdio { #address-cells = <1>; From 369d04d6430f1cd3678b99be4e0baaee26b865b5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 10 Jul 2023 14:37:31 +0200 Subject: [PATCH 24/40] arm64: zynqmp: Fix gpio comment about No of gpios There are total 174 gpios but from 0 - 173 that's why fix comment to reflect it. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/c7e94b334e7dd6297e0d3a36a6a3d04bd7e9e967.1688992653.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-dlc21-revA.dts | 2 +- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 2 +- arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-sm-k26-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu208-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu216-revA.dts | 2 +- 10 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts index e287a9b6591..1b247bfa894 100644 --- a/arch/arm/dts/zynqmp-dlc21-revA.dts +++ b/arch/arm/dts/zynqmp-dlc21-revA.dts @@ -131,7 +131,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO34/35 */ diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index e24d070adb6..bf6ffb778b6 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -201,7 +201,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index 11142401151..d5cfc61faf7 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -125,7 +125,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index aa4f7c23ede..97500b13287 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -154,7 +154,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index 7aa8c2b4d1f..3bdcf052a55 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -149,7 +149,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index 459736abe6b..9a693a57a93 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -149,7 +149,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts index d5f4a16f20e..16691a85e15 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts @@ -134,7 +134,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index 4b88b57e0c2..d718fec7606 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -363,7 +363,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ }; &xilinx_ams { diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 5ad07d30b8b..9b3ae67bff1 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -222,7 +222,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ }; &i2c0 { diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index 574e4845be8..43eeaec5b15 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -228,7 +228,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ }; &gpu { From 414fc91f4ecbcd00a7d23e33baf39a0e2f6bac96 Mon Sep 17 00:00:00 2001 From: Harini Katakam Date: Mon, 10 Jul 2023 14:37:32 +0200 Subject: [PATCH 25/40] arm64: zynqmp: Increase reset assert time for TI SGMII PHY Increase reset assert time for TI SGMII PHY on KR260 CC starting 6.1 kernel. This PHY does not come out of reset with the existing 100us pulse width as per testing on multiple carrier cards. The reset is driven via a PCA9570 I2C expander. The expander driver was updated to an upstream version in 6.1 where gpio_chip _set was optimized. Delays in earlier kernels may have masked this issue. This is a safe workaround value for assert pulse width before the discussions are resolved with TI. Signed-off-by: Harini Katakam Reviewed-by: Radhey Shyam Pandey Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/8fb9f17d43a43ef504c9f29006cd686cce8ac98b.1688992653.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sck-kr-g-revA.dts | 2 +- arch/arm/dts/zynqmp-sck-kr-g-revB.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts index caaf71d729e..d318773bd9d 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts @@ -210,7 +210,7 @@ ti,tx-internal-delay = ; ti,fifo-depth = ; ti,dp83867-rxctrl-strap-quirk; - reset-assert-us = <100>; + reset-assert-us = <300>; reset-deassert-us = <280>; reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts index f9d87559a71..69dba0761b3 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts @@ -210,7 +210,7 @@ ti,tx-internal-delay = ; ti,fifo-depth = ; ti,dp83867-rxctrl-strap-quirk; - reset-assert-us = <100>; + reset-assert-us = <300>; reset-deassert-us = <280>; reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>; }; From 6a251f24888b1ae3a1d20e21b5886e9cbd0e289b Mon Sep 17 00:00:00 2001 From: Harini Katakam Date: Mon, 10 Jul 2023 14:37:33 +0200 Subject: [PATCH 26/40] arm64: zynqmp: Assign TSU clock frequency for KV and KD boards Set TSU clock frequency as 250MHz (minimum when running at 1G) on KV and KD carrier cards to allow PTP functionality. Signed-off-by: Harini Katakam Reviewed-by: Radhey Shyam Pandey Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/4b758d503ef545e4d25d3930b0eb0793f1c415d2.1688992653.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 1 + arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts index 8229244d241..a81b3f6f51a 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts @@ -165,6 +165,7 @@ pinctrl-0 = <&pinctrl_gem3_default>; phy-handle = <&phy0>; phy-mode = "rgmii-id"; + assigned-clock-rates = <250000000>; mdio: mdio { #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts index 96a51219f42..0ac20869b37 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts @@ -152,6 +152,7 @@ pinctrl-0 = <&pinctrl_gem3_default>; phy-handle = <&phy0>; phy-mode = "rgmii-id"; + assigned-clock-rates = <250000000>; mdio: mdio { #address-cells = <1>; From efa1ddea07f4b8e0ca968458bde98827b49e42fb Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 10 Jul 2023 14:37:34 +0200 Subject: [PATCH 27/40] arm64: zynqmp: Record compatible string for kv260 rev2 PCB rev2 compare to rev1 has some changes in PL side (IAS sensor AR1335 autofocus feature). PS side is completely unchanged. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/42f78dee8429eeac016d73de5c73af46fdaf4a98.1688992653.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts index 0ac20869b37..f935f25c887 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts @@ -16,7 +16,8 @@ /plugin/; &{/} { - compatible = "xlnx,zynqmp-sk-kv260-rev1", + compatible = "xlnx,zynqmp-sk-kv260-rev2", + "xlnx,zynqmp-sk-kv260-rev1", "xlnx,zynqmp-sk-kv260-revB", "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; model = "ZynqMP KV260 revB"; From 58601fbb8f6ab1122abe5569ac572c44d4f97d77 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 10 Jul 2023 14:37:35 +0200 Subject: [PATCH 28/40] arm64: zynqmp: Cover K24 revB/1 SOM Extend compatible versions for K24 SOM. Changes are not affecting SW behavior that's why all versions are compatible to each other. Describing all revisions is done by purpose because user space SW is reading compatible string for logic around DT overlays and bitstreams. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/92eba01ac316e58bd2d3508b0e63bbfafbedbb73.1688992653.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sm-k24-revA.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynqmp-sm-k24-revA.dts b/arch/arm/dts/zynqmp-sm-k24-revA.dts index 24514409cb9..653bd936226 100644 --- a/arch/arm/dts/zynqmp-sm-k24-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k24-revA.dts @@ -11,8 +11,9 @@ #include "zynqmp-sm-k26-revA.dts" / { - model = "ZynqMP SM-K24 RevA"; - compatible = "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24", + model = "ZynqMP SM-K24 RevA/B/1"; + compatible = "xlnx,zynqmp-sm-k24-rev1", "xlnx,zynqmp-sm-k24-revB", + "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24", "xlnx,zynqmp"; memory@0 { From 1ea11e8138767a262e576d5b08bb1509fed62dd9 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 10 Jul 2023 14:37:36 +0200 Subject: [PATCH 29/40] arm64: zynqmp: Fix usb reset over bootmode pins on zcu100 The commit a4180c369607 ("arm64: zynqmp: Add mode-pin GPIO controller DT node") added usb phy reset over bootmode pins by default on usb0 only. zcu100 is using usb0 as peripheral and usb1 as host. Unfortunately reset line is shared for both usb ulpi phys but usb_rst_b is connected to usb5744 hub which is used only in host mode. Especially this chip requires reset to operate properly that's why better assign gpio reset to usb1 instead of usb0. Without this change usb start crashed when runs. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/1ca80ec5bf7a595c03822f3e4e3683298205067a.1688992653.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-zcu100-revC.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index 78c32507600..a84cd86694e 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -569,6 +569,7 @@ pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 0>; + /delete-property/ reset-gpios; }; &dwc3_0 { @@ -584,6 +585,7 @@ pinctrl-0 = <&pinctrl_usb1_default>; phy-names = "usb3-phy"; phys = <&psgtr 3 PHY_TYPE_USB3 1 0>; + reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; }; &dwc3_1 { From a8d4b6700069f6717c65ee8ced63e525836ba855 Mon Sep 17 00:00:00 2001 From: Radhey Shyam Pandey Date: Mon, 10 Jul 2023 14:37:37 +0200 Subject: [PATCH 30/40] arm64: zynqmp: Add L2 cache nodes Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache node and let each CPU point to it. Reported-by: John Toomey Signed-off-by: Radhey Shyam Pandey Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/c8dfabab12c97922aaad7fa91be0cbc7e4021528.1688992653.git.michal.simek@amd.com --- arch/arm/dts/zynqmp.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 38114d55386..59b52919f13 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -33,6 +33,7 @@ operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu1: cpu@1 { @@ -42,6 +43,7 @@ reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu2: cpu@2 { @@ -51,6 +53,7 @@ reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu3: cpu@3 { @@ -60,6 +63,13 @@ reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; }; idle-states { From 606121cdf48d8e33fc6531bf94a58b7b08fe875e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 10 Jul 2023 14:37:38 +0200 Subject: [PATCH 31/40] arm64: zynqmp: Sync node name address with reg (mailbox) Address in node name should match with the first reg property in DT. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/47bea10bbc3c88727c1fe839ff20e15a0c79c339.1688992653.git.michal.simek@amd.com --- arch/arm/dts/zynqmp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 59b52919f13..b9cfd562c91 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -121,7 +121,7 @@ #size-cells = <2>; ranges; - ipi_mailbox_pmu1: mailbox@ff990400 { + ipi_mailbox_pmu1: mailbox@ff9905c0 { bootph-all; reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, From 7cfddb4c07332fbe0968de48c00f4463bcda5e8b Mon Sep 17 00:00:00 2001 From: Radhey Shyam Pandey Date: Mon, 10 Jul 2023 14:37:39 +0200 Subject: [PATCH 32/40] arm64: zynqmp: add pmu interrupt-affinity Explicitly specify interrupt affinity to avoid HW perfevents need to guess. This avoids the following error upon linux boot: armv8-pmu pmu: hw perfevents: no interrupt-affinity property, guessing. Reported-by: John Toomey Signed-off-by: Radhey Shyam Pandey Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/c2f55a10cf54c6004f5dfe2ea18bcb4cf04f5723.1688992653.git.michal.simek@amd.com --- arch/arm/dts/zynqmp.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index b9cfd562c91..11eaf4b6a19 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -149,6 +149,10 @@ <0 144 4>, <0 145 4>, <0 146 4>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; }; psci { From a876a5112e2871b3d91d7b4da6a6afbc19f2e286 Mon Sep 17 00:00:00 2001 From: Piyush Mehta Date: Mon, 10 Jul 2023 14:37:40 +0200 Subject: [PATCH 33/40] arm64: zynqmp: remove snps, enable_guctl1_resume_quirk quirk for usb To sync with the upstream code, removed 'snps,enable_guctl1_resume_quirk' quirk for usb. This quirk is no more available in linux after the xilinx release 2022.2. This functionality is taken care of by the 'snps,resume-hs-terminations' quirk. Signed-off-by: Piyush Mehta Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/4b7a132116bf0248cdb558e04de3b06b412c4a0f.1688992653.git.michal.simek@amd.com --- arch/arm/dts/zynqmp.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 11eaf4b6a19..223cdab5f93 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -892,7 +892,6 @@ iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; - snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; snps,resume-hs-terminations; @@ -924,7 +923,6 @@ iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; - snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; snps,resume-hs-terminations; From 20beff0ddbc2068bd931bbd764f0e07218bf7be0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 10 Jul 2023 14:37:41 +0200 Subject: [PATCH 34/40] arm64: zynqmp: Remove interrupt/reg-names for AMS These two properties are not described in DT binding and also not used by driver that's why remove them. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/b123c7e537dcf70802e828bbcd484a761a264186.1688992653.git.michal.simek@amd.com --- arch/arm/dts/zynqmp.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 223cdab5f93..299ad1e7c03 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -954,9 +954,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 56 4>; - interrupt-names = "ams-irq"; reg = <0x0 0xffa50000 0x0 0x800>; - reg-names = "ams-base"; #address-cells = <1>; #size-cells = <1>; #io-channel-cells = <1>; From 4c360f6cfd4340cc2c320a320943b4e5e1081ff1 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 10 Jul 2023 14:37:42 +0200 Subject: [PATCH 35/40] arm64: zynqmp: Rename ams_ps/pl node names Fix child node names to be aligned with dt-binding available in the Linux kernel which requires names as ams-ps@ and ams-pl@. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/8f1451d614f654cb0d0da1e799e876c078fbf2c9.1688992653.git.michal.simek@amd.com --- arch/arm/dts/zynqmp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 299ad1e7c03..6228149b886 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -960,13 +960,13 @@ #io-channel-cells = <1>; ranges = <0 0 0xffa50800 0x800>; - ams_ps: ams_ps@0 { + ams_ps: ams-ps@0 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x0 0x400>; }; - ams_pl: ams_pl@400 { + ams_pl: ams-pl@400 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x400 0x400>; From c310c98201925e525d86b1d78447ee985cc37848 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 10 Jul 2023 14:37:43 +0200 Subject: [PATCH 36/40] arm64: zynqmp: Remove clock-names from pcap node Clock is not used in driver and also not described in binding. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/0a0fa0ba197fa4051a2c8a24e1451cefadce7517.1688992653.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-clk-ccf.dtsi | 4 ---- arch/arm/dts/zynqmp.dtsi | 1 - 2 files changed, 5 deletions(-) diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index a21dca87d24..1ae8ea2e43f 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -289,10 +289,6 @@ clocks = <&zynqmp_clk AMS_REF>; }; -&zynqmp_pcap { - clocks = <&zynqmp_clk PCAP>; -}; - &zynqmp_dpdma { clocks = <&zynqmp_clk DPDMA_REF>; assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */ diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 6228149b886..1632be843b1 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -193,7 +193,6 @@ zynqmp_pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; - clock-names = "ref_clk"; }; xlnx_aes: zynqmp-aes { From 3fb4ef7d39abbb2f8f6cd349e4af11082bf8c8c4 Mon Sep 17 00:00:00 2001 From: Maksim Kiselev Date: Wed, 19 Jul 2023 09:53:37 +0300 Subject: [PATCH 37/40] net: axi_emac: Change return value to -EAGAIN if RX is not ready If there is no incoming package than axiemac_recv will return -1 which in turn leads to printing `eth_rx: recv() returned error -1` error message in eth_rx function. But missing a package is not an fatal error, so return -EAGAIN in that case would be more suitable. Signed-off-by: Maksim Kiselev Link: https://lore.kernel.org/r/20230719065337.69280-1-bigunclemax@gmail.com Signed-off-by: Michal Simek --- drivers/net/xilinx_axi_emac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index 3e9919993d0..39cb3cc260b 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -748,7 +748,7 @@ static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp) /* Wait for an incoming packet */ if (!isrxready(priv)) - return -1; + return -EAGAIN; debug("axiemac: RX data ready\n"); From 7a480fd995e279dd883b9e4e24741f9c71d66143 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Wed, 19 Jul 2023 02:49:12 -0600 Subject: [PATCH 38/40] clk: zynqmp: Add set_rate support for gem rx and tsu clks gem0_rx till gem3_rx and gem_tsu are missing from set rate function. Add them, so that they can be set from pmu firmware via clock framework. Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230719084912.30209-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- drivers/clk/clk_zynqmp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 8320d491846..53327cf9adc 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -719,6 +719,8 @@ static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate) switch (id) { case gem0_ref ... gem3_ref: case gem0_tx ... gem3_tx: + case gem0_rx ... gem3_rx: + case gem_tsu: case qspi_ref ... can1_ref: case usb0_bus_ref ... usb3_dual_ref: return zynqmp_clk_set_peripheral_rate(priv, id, From 2a907542c77610817504321f32a78422f9a23d1d Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Thu, 20 Jul 2023 01:28:59 -0600 Subject: [PATCH 39/40] clk: zynqmp: Add gem rx and tsu clocks to return register Add gem_tsu and gem0_rx till gem3_rx to return proper register from zynqmp_clk_get_register. Otherwise firmware won't be able to set clock for these due to incorrect register address. Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230720072859.3724-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- drivers/clk/clk_zynqmp.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 53327cf9adc..1cfe0e25b10 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -270,17 +270,22 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id) case usb3_dual_ref: return CRL_APB_USB3_DUAL_REF_CTRL; case gem_tsu_ref: + case gem_tsu: return CRL_APB_GEM_TSU_REF_CTRL; case gem0_tx: + case gem0_rx: case gem0_ref: return CRL_APB_GEM0_REF_CTRL; case gem1_tx: + case gem1_rx: case gem1_ref: return CRL_APB_GEM1_REF_CTRL; case gem2_tx: + case gem2_rx: case gem2_ref: return CRL_APB_GEM2_REF_CTRL; case gem3_tx: + case gem3_rx: case gem3_ref: return CRL_APB_GEM3_REF_CTRL; case usb0_bus_ref: From a1190b4d6a9bf3a45038e3eba4a11de4be2b1cca Mon Sep 17 00:00:00 2001 From: Christian Taedcke Date: Thu, 20 Jul 2023 09:27:24 +0200 Subject: [PATCH 40/40] event: Add fpga load event This enables implementing custom logic after a bitstream was loaded into the fpga. Signed-off-by: Christian Taedcke Reviewed-by: Simon Glass Reviewed-by: Tom Rini Link: https://lore.kernel.org/r/20230720072724.11516-1-christian.taedcke-oss@weidmueller.com Signed-off-by: Michal Simek --- common/event.c | 3 +++ drivers/fpga/fpga.c | 20 ++++++++++++++++++++ include/event.h | 17 +++++++++++++++++ 3 files changed, 40 insertions(+) diff --git a/common/event.c b/common/event.c index 164c95f8f52..20720c52839 100644 --- a/common/event.c +++ b/common/event.c @@ -36,6 +36,9 @@ const char *const type_name[] = { /* init hooks */ "misc_init_f", + /* Fpga load hook */ + "fpga_load", + /* fdt hooks */ "ft_fixup", diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index 7f6b6bc73a1..81e6d8ffc0b 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -244,6 +244,21 @@ int fpga_loads(int devnum, const void *buf, size_t size, } #endif +static int fpga_load_event_notify(const void *buf, size_t bsize, int result) +{ + if (CONFIG_IS_ENABLED(EVENT)) { + struct event_fpga_load load = { + .buf = buf, + .bsize = bsize, + .result = result + }; + + return event_notify(EVT_FPGA_LOAD, &load, sizeof(load)); + } + + return 0; +} + /* * Generic multiplexing code */ @@ -251,6 +266,7 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype, int flags) { int ret_val = FPGA_FAIL; /* assume failure */ + int ret_notify; const fpga_desc *desc = fpga_validate(devnum, buf, bsize, (char *)__func__); @@ -284,6 +300,10 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype, } } + ret_notify = fpga_load_event_notify(buf, bsize, ret_val); + if (ret_notify) + return ret_notify; + return ret_val; } diff --git a/include/event.h b/include/event.h index fe41080fa63..daf44bf8a83 100644 --- a/include/event.h +++ b/include/event.h @@ -11,6 +11,7 @@ #define __event_h #include +#include /** * enum event_t - Types of events supported by U-Boot @@ -31,6 +32,9 @@ enum event_t { /* Init hooks */ EVT_MISC_INIT_F, + /* Fpga load hook */ + EVT_FPGA_LOAD, + /* Device tree fixups before booting */ EVT_FT_FIXUP, @@ -59,6 +63,19 @@ union event_data { struct udevice *dev; } dm; + /** + * struct event_fpga_load - fpga load event + * + * @buf: The buffer that was loaded into the fpga + * @bsize: The size of the buffer that was loaded into the fpga + * @result: Result of the load operation + */ + struct event_fpga_load { + const void *buf; + size_t bsize; + int result; + } fpga_load; + /** * struct event_ft_fixup - FDT fixup before booting *